CN107230703B - Wafer - Google Patents
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- CN107230703B CN107230703B CN201710229601.3A CN201710229601A CN107230703B CN 107230703 B CN107230703 B CN 107230703B CN 201710229601 A CN201710229601 A CN 201710229601A CN 107230703 B CN107230703 B CN 107230703B
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- 239000002184 metal Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 abstract description 82
- 239000000758 substrate Substances 0.000 abstract description 19
- 230000000694 effects Effects 0.000 abstract description 13
- 238000002955 isolation Methods 0.000 abstract description 12
- 238000005520 cutting process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application provides a wafer, the wafer includes a plurality of wafers of arranging according to the order, the wafer includes first circuit portion, connecting portion and second circuit portion, the both ends of connecting portion are connected respectively first circuit portion with second circuit portion, the structure that first circuit portion, connecting portion and second circuit portion formed has the concave part, and the partial embedding of the first circuit portion of a wafer is in the concave part of its adjacent wafer, and the partial embedding of the second circuit portion of this wafer is in the concave part of another adjacent wafer, is formed with the scribing groove between the adjacent wafer, obtains independent a plurality of wafers along scribing groove cutting wafer. Because the wafer that this application provided has increased connecting portion between first circuit portion and second circuit portion, has increased the substrate resistance value between first circuit portion and the second circuit portion, the substrate resistance is big more, the electrical isolation effect is better, heat conduction length is longer, the thermal isolation effect is also better to circuit performance has been improved.
Description
Technical Field
The present application relates to the field of electronic circuit technology, and in particular, to a wafer.
Background
In the prior art, the chip is generally designed to be approximately square, so that the chip arrangement is easier. Fig. 1 is a schematic diagram of the arrangement of chips (Die) on a Wafer (Wafer) in the prior art, where each Chip (Die) is cut and packaged to be called a Chip (Chip), for example: an 8-inch wafer generally refers to a wafer having a diameter of 8 inches, and is generally a silicon wafer on which a chip pattern is formed by a processing step such as photolithography. There are some incomplete chip patterns around the wafer, which are all waste products. In a typical design, a pitch is provided between wafers, and this pitch is called a Scribe line (Scribe line).
Fig. 2 is a schematic view of a wafer after enlargement, on which two modules are present: the module a on the left of the dotted line and the module B on the right of the dotted line, the module a may be a sensitive analog circuit or a radio frequency circuit, and the module B may be a digital circuit or a power circuit with a relatively large noise.
As technology is continuously improved, the precision requirement of analog circuits or radio frequency circuits is higher and higher, and the noise design of the analog circuits or the radio frequency circuits needs to be smaller. The better the noise (noise) performance, the better the performance can be achieved by analog and radio frequency circuits.
However, current analog circuits and rf circuits are generally noisy and can also affect sensitive analog circuits and rf circuits, resulting in poor circuit performance.
Disclosure of Invention
The embodiment of the application provides a wafer, which is used for solving the technical problem that the circuit performance is poor due to large noise in the prior art.
The embodiment of the application provides a wafer, the wafer includes a plurality of chips of arranging in order, the wafer includes first circuit end, connecting portion and second circuit end, the both ends of connecting portion are connected respectively first circuit end with the second circuit end, there is the concave part in the structure that first circuit end, connecting portion and second circuit end formed, in the concave part of its adjacent one of its wafer of partial embedding of the first circuit portion of one of them wafer, in the concave part of the adjacent another wafer of partial embedding of the second circuit portion of this one wafer, be formed with the scribing groove between the adjacent wafer, follow the scribing groove cutting the wafer obtains independent a plurality of chips.
The beneficial effects are as follows:
because the wafer that this application embodiment provided has increased the connecting portion between first circuit portion and second circuit portion, is equivalent to having increased the substrate resistance between first circuit portion and the second circuit portion when manufacturing the chip, has increased the substrate resistance value between first circuit portion and the second circuit portion, and the substrate resistance is bigger, the electrical isolation effect is better, and heat conduction length is longer, the thermal isolation effect is also better to circuit performance has been improved.
Drawings
Specific embodiments of the present application will be described below with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a wafer layout on a prior art wafer;
FIG. 2 is an enlarged view of a die on a prior art wafer;
FIG. 3 shows a first schematic structural diagram of a wafer according to an embodiment of the present application;
FIG. 4 shows a first schematic diagram of a wafer according to an embodiment of the present disclosure;
FIG. 5 shows a second schematic structural view of the wafer in an embodiment of the present application;
FIG. 6 shows a second schematic diagram of the wafer in the embodiment of the present application;
FIG. 7 shows a third schematic structural view of a wafer as described in an embodiment of the present application;
fig. 8 shows a third schematic view of the wafer in its own parent embodiment.
Detailed Description
In order to make the technical solutions and advantages of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and not an exhaustive list of all embodiments. And the embodiments and features of the embodiments in the present description may be combined with each other without conflict.
The inventor notices in the process of invention that:
in the prior art, digital circuits and power circuits often make a lot of noise, and since in complex circuit designs, both noise sensitive analog circuits and digital circuits may be present on the same wafer, and they are carried by a common substrate through which noise is conducted. The prior art is generally improved by designing an isolating ring (isolating ring), but the effect is limited. Next, the digital circuit generates a large amount of heat when operating at high speed, and the power circuit generates a large amount of heat when operating at a large current. The high temperature is also conducted to the sensitive circuitry side through the underlying common liner. Sensitive analog circuits and radio frequency circuits can be affected, on one hand, the performance of the analog circuits and the performance of the radio frequency circuits can be reduced due to high temperature, the performance of the analog circuits and the performance of the radio frequency circuits can be unstable due to unstable temperature, and on the other hand, the noise of the analog circuits and the noise of the radio frequency circuits can be increased due to the increase of the temperature under the common condition, so that the performance of the circuits can be affected.
In view of the above disadvantages, the embodiments of the present application provide a wafer, which will be described below.
The wafer provided by the embodiment of the application comprises a plurality of wafers which are arranged in sequence, wherein each wafer comprises a first circuit part, a connecting part and a second circuit part, two ends of each connecting part are respectively connected with the first circuit part and the second circuit part, a concave part exists in a structure formed by the first circuit part, the connecting parts and the second circuit parts, part of the first circuit part of one wafer is embedded into the concave part of the adjacent wafer, part of the second circuit part of the wafer is embedded into the concave part of the adjacent wafer, a scribing groove is formed between the adjacent wafers, and the wafer is cut along the scribing groove to obtain a plurality of independent wafers.
In an implementation, the first circuit portion, the connection portion, and the second circuit portion may each have a rectangular shape, and the width of the connection portion is smaller than the width of the first circuit portion and the width of the second circuit portion.
In a specific implementation, the long side of the connecting portion may be perpendicular to the first side of the first circuit portion and the first side of the second circuit portion, and the length of the first side of the first circuit portion may be the same as the length of the first side of the second circuit portion and may be greater than the width of the connecting portion.
In a specific implementation, the first side of the first circuit portion may be a rectangle, and the first side of the second circuit portion may be a rectangle, and the side length of the first side of the first circuit portion is the same as the side length of the first side of the second circuit portion and may be much larger than the width of the connection portion, for example: the side length of the first side of the first circuit part is the same as that of the first side of the second circuit part and is N times of the width of the connecting part, and N is a natural number such as 5, 6, 6.1, 7 … and the like; the length of the connection portion may be much greater than the width of the connection portion, for example: the length is 6 times the width, etc.
The first circuit portion may be a high-noise circuit, the second circuit portion may be a circuit sensitive to noise, and the first circuit portion and the second circuit portion are connected by the connecting portion after dicing.
In specific implementation, the high-noise circuit may be a circuit in which the high-frequency noise exceeds a preset threshold, for example: digital circuits or power circuits; the circuit that is sensitive to noise may then be an analog circuit.
The connecting part can be a narrow and long structure, and can achieve the effects of isolating noise and heat.
The first embodiment,
Fig. 3 shows a first structural diagram of the wafer in the embodiment of the present application, and as shown in the figure, two ends of the connection portion of the wafer are respectively connected to one end of the first circuit portion and one end of the second circuit portion, and the other end of the first circuit portion and the other end of the second circuit portion face the same direction.
In a specific implementation, the width of the first circuit portion may be the same as or different from the width of the second circuit portion. Assuming that the width of the first circuit portion (left part in the figure) is b, b can be designed as a sensitive analog circuit; the second circuit portion (right portion in the figure) has a width c, which can be designed as a noise circuit (e.g., a digital circuit or a power circuit), and the third portion is a middle connection portion for electrically connecting the left portion and the right portion to each other, and a plurality of metal wires can be provided for connection, or polysilicon wiring can be used for connection.
Fig. 4 is a first schematic diagram of the wafer according to the embodiment of the present disclosure, and as shown in the figure, in order to achieve effective utilization of the wafer area, the plurality of chips are arranged in a nested and staggered manner according to the embodiment of the present disclosure.
In particular implementations, the first circuit portion of the second wafer may be embedded in the recess of the wafer near one side of the recess, and the second circuit portion of the third wafer may be embedded in the recess of the wafer near the other side of the recess.
In specific implementation, after the first repeated pattern is placed, a second repeated pattern can be generated through upper and lower mirror images, the right part of the second repeated pattern is embedded into the concave part of the first repeated pattern and is placed close to the left side of the concave part of the first repeated pattern; and generating a third repeated pattern by upper and lower mirror images, embedding the left part of the third repeated pattern into the concave part of the first repeated pattern, and placing the left part of the third repeated pattern close to the right side of the concave part of the first repeated pattern.
And repeating the placing process until the whole wafer area is filled.
If the width of the left part of the repeating pattern is designed as b, the width of the right part of the repeating pattern is designed as c, and the width of the scribe line is designed as a, the length d of the connection part may be designed as d ═ b + c +3a, so that the wafer area may be just and closely filled.
The dashed lines in fig. 4 depict the locations where dicing is performed after the wafer fabrication is completed, and dicing is performed along the dashed-dotted lines to create the effect of singulation and isolation.
In specific implementation, scribing can be performed by adopting a laser cutting mode and the like.
Example II,
Fig. 5 shows a structural schematic diagram of the wafer in the embodiment of the present application, as shown in the figure, two ends of the connection portion are respectively connected to the middle portions of the first circuit portion and the second circuit portion, a straight line where two ends of the first circuit portion are located is parallel to a straight line where two ends of the second circuit portion are located, and a structure formed by the first circuit portion, the connection portion, and the second circuit portion has two concave portions, and opening directions of the two concave portions are opposite.
As shown in the figure, the difference from the first embodiment is that the connecting portion is disposed at the middle position in the vertical direction of the left portion and the right portion.
Fig. 6 shows a second schematic diagram of the wafer in the embodiment of the present application, and as shown in the drawing, in order to achieve effective utilization of the wafer area, a plurality of chips are arranged in a nested and staggered manner in the embodiment of the present application.
When the wafer is implemented, the first circuit part of the second wafer is embedded into the first concave part of the wafer and is close to one side of the first concave part, and the second circuit part of the third wafer is embedded into the first concave part of the wafer and is close to the other side of the first concave part; the first circuit portion of the fourth wafer is fitted into the second recess of the wafer near one side of the second recess, and the second circuit portion of the fifth wafer is fitted into the second recess of the wafer near the other side of the second recess.
When the design satisfies d ═ b + c +3a, a very tight arrangement can be achieved.
The dashed lines in fig. 6 depict the positions where dicing is performed after the wafer fabrication is completed, and the dicing is performed along the dashed lines to create the effects of dicing and isolation.
In specific implementation, scribing can be performed by adopting a laser cutting mode and the like.
Example III,
Fig. 7 shows a third schematic structural diagram of the wafer in the embodiment of the present application, and as shown in the figure, the connecting portion includes a first horizontal end, a second horizontal end and a U-shaped portion, the first horizontal end is used for connecting the first circuit portion and the U-shaped portion, and the second horizontal end is used for connecting the U-shaped portion and the second circuit portion.
In the embodiment of the present application, the connecting portion may be designed in a curved shape, such as a U shape.
Fig. 8 shows a third schematic diagram of the wafer in the self-consistent embodiment, as shown, the plurality of chips may be arranged in sequence, and the dotted line depicts the position where dicing is performed after the wafer is manufactured.
In a specific implementation, the number of the U-shaped portions may be multiple, and the connecting portion may further include a third horizontal end, where the third horizontal end is used to connect the U-shaped portion and the U-shaped portion.
Because the wafer that this application embodiment provided has increased the connecting portion between first circuit portion and second circuit portion, is equivalent to having increased the substrate resistance between first circuit portion and the second circuit portion when manufacturing the chip, has increased the substrate resistance value between first circuit portion and the second circuit portion, and the substrate resistance is bigger, the electrical isolation effect is better, and heat conduction length is longer, the thermal isolation effect is also better to circuit performance has been improved.
In a specific implementation, the connecting portion may connect the first circuit portion and the second circuit portion by providing a plurality of metal wires, or connect the first circuit portion and the second circuit portion by a polysilicon interconnection.
The connection part may further include a Contact hole (Contact) for connecting the polysilicon and the metal.
The connection part may further include a VIA hole (VIA) for connecting different layers of metal.
In specific implementation, alternating P + and N + isolation layers, or P +/Pwell and N +/Nwell isolation layers can be arranged on the lower layer.
Wherein, P + can be connected to the lowest potential of the chip through the metal, and N + can be connected to the highest potential of the chip through the metal.
In the prior art, as shown in fig. 2, when calculating the number of substrate resistor squares between the equivalent left circuit and right circuit, the length of the substrate resistor squares can be approximated to the distance from the left middle to the right middle. If the left width is b, the right width is c, and the height of the chip is e, the number of blocks of substrate resistance between the left circuit and the right circuit can be approximated to be (b/2+ c/2)/e, and the equivalent substrate resistance between the left circuit and the right circuit is Rsq (b/2+ c/2)/e.
By adopting the technical solution provided by the embodiment of the present application, taking fig. 4 as an example, since the substrate resistance between the left circuit and the right circuit is increased in the embodiment of the present application, assuming that the square resistance value of the substrate resistance is Rsq, the number of the substrate resistance squares between the equivalent left circuit and the equivalent right circuit can be approximated to ((b/2+ c/2)/e + d/w), and the substrate resistance value between the equivalent left circuit and the equivalent right circuit is Rsq ((b/2+ c/2)/e + d/w). Where d is the length of the intermediate link and w is the width of the intermediate link.
Obviously, the scheme provided by the embodiment of the application has the advantages of larger equivalent resistance and better electrical isolation effect.
Taking fig. 7 as an example, the substrate resistance between the equivalent left circuit and the equivalent right circuit can be approximately proportional to the length of the bending connection, so the more bending, the larger the bending length, the larger the substrate resistance between the equivalent left circuit and the equivalent right circuit, and the better the isolation effect. Also, the longer the heat conduction length, the better the heat insulation effect.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
Claims (8)
1. A wafer is characterized by comprising a plurality of chips which are arranged in sequence, wherein each chip comprises a first circuit part, a connecting part and a second circuit part, two ends of each connecting part are respectively connected with the first circuit part and the second circuit part, and a structure formed by the first circuit part, the connecting parts and the second circuit parts is provided with a concave part, wherein part of the first circuit part of the first chip is embedded into the concave parts of the adjacent second chips, part of the second circuit part of the first chip is embedded into the concave parts of the adjacent third chips, a scribing groove is formed between the adjacent chips, and the wafer is cut along the scribing groove to obtain a plurality of independent chips;
the first circuit part is a digital circuit or a power circuit, and the second circuit part is an analog circuit;
the connecting part is a plurality of metal wires or polysilicon wirings; the first circuit portion and the second circuit portion are connected by a plurality of metal wires or polysilicon wirings.
2. The wafer according to claim 1, wherein two ends of the connecting portion are respectively connected to one end of the first circuit portion and one end of the second circuit portion, and the other end of the first circuit portion and the other end of the second circuit portion face in the same direction.
3. The wafer of claim 2, wherein a first circuit portion of a second die is embedded in the recess of the first die near one side of the recess, and a second circuit portion of a third die is embedded in the recess of the first die near the other side of the recess.
4. The wafer according to claim 1, wherein two ends of the connecting portion are respectively connected to a middle portion of the first circuit portion and a middle portion of the second circuit portion, a side where the first circuit portion and the connecting portion are connected is parallel to a side where the second circuit portion and the connecting portion are connected, and a structure formed by the first circuit portion, the connecting portion and the second circuit portion has two concave portions, and opening directions of the two concave portions are opposite.
5. The wafer of claim 4, wherein the first circuit portion of the second die is embedded in the first recess of the first die and is adjacent to one side of the first recess, and the second circuit portion of the third die is embedded in the first recess of the first die and is adjacent to the other side of the first recess; the first circuit part of the fourth wafer is embedded in the second concave part of the first wafer and is close to one side of the second concave part, and the second circuit part of the fifth wafer is embedded in the second concave part of the first wafer and is close to the other side of the second concave part.
6. The wafer of claim 1, wherein the connecting portion comprises a first horizontal end, a second horizontal end and a U-shaped portion, the first horizontal end is used for connecting the first circuit portion and the U-shaped portion, and the second horizontal end is used for connecting the U-shaped portion and the second circuit portion.
7. The wafer of claim 6, wherein the U-shaped portion is plural, and the connecting portion further comprises a third horizontal end for connecting the U-shaped portion and the U-shaped portion.
8. The wafer of claim 1, wherein the first circuit portion and the second circuit portion are both rectangular, and wherein the width of the connection portion is smaller than the width of the first circuit portion and the second circuit portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710229601.3A CN107230703B (en) | 2017-04-10 | 2017-04-10 | Wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710229601.3A CN107230703B (en) | 2017-04-10 | 2017-04-10 | Wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107230703A CN107230703A (en) | 2017-10-03 |
| CN107230703B true CN107230703B (en) | 2020-04-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710229601.3A Active CN107230703B (en) | 2017-04-10 | 2017-04-10 | Wafer |
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| CN (1) | CN107230703B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109686734B (en) * | 2018-11-27 | 2021-05-07 | 合肥中感微电子有限公司 | Chip with isolation structure |
| CN109599358B (en) * | 2018-11-27 | 2021-05-04 | 合肥中感微电子有限公司 | Method for manufacturing chip with isolation structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6528864B1 (en) * | 1999-11-19 | 2003-03-04 | Disco Corporation | Semiconductor wafer having regular or irregular chip pattern and dicing method for the same |
| CN101093824A (en) * | 2006-06-20 | 2007-12-26 | 台湾积体电路制造股份有限公司 | Interconnected lines structure and wafer |
| CN102157448A (en) * | 2010-01-18 | 2011-08-17 | 半导体元件工业有限责任公司 | Method of forming a semiconductor die |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10031252A1 (en) * | 2000-06-27 | 2002-01-10 | Bosch Gmbh Robert | Sectioning of substrate wafer into substrate chips comprises separating substrate chips from one another by selective deep patterning |
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2017
- 2017-04-10 CN CN201710229601.3A patent/CN107230703B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6528864B1 (en) * | 1999-11-19 | 2003-03-04 | Disco Corporation | Semiconductor wafer having regular or irregular chip pattern and dicing method for the same |
| CN101093824A (en) * | 2006-06-20 | 2007-12-26 | 台湾积体电路制造股份有限公司 | Interconnected lines structure and wafer |
| CN102157448A (en) * | 2010-01-18 | 2011-08-17 | 半导体元件工业有限责任公司 | Method of forming a semiconductor die |
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| CN107230703A (en) | 2017-10-03 |
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