CN107230703A - A kind of wafer - Google Patents
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- CN107230703A CN107230703A CN201710229601.3A CN201710229601A CN107230703A CN 107230703 A CN107230703 A CN 107230703A CN 201710229601 A CN201710229601 A CN 201710229601A CN 107230703 A CN107230703 A CN 107230703A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims 1
- 230000037431 insertion Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 68
- 239000000758 substrate Substances 0.000 abstract description 21
- 238000002955 isolation Methods 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 9
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000003698 laser cutting Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
本申请提供了一种晶圆，所述晶圆包括按次序排布的多个晶片，所述晶片包括第一电路部、连接部和第二电路部，所述连接部的两端分别连接所述第一电路部和所述第二电路部，所述第一电路部、连接部和第二电路部形成的结构存在凹部，一个晶片的第一电路部的部分嵌入其相邻的一个晶片的凹部内，该晶片的第二电路部的部分嵌入相邻的另一个晶片的凹部内，相邻的晶片之间形成有划片槽，沿划片槽切割晶圆得到独立的多个晶片。由于本申请所提供的晶圆，在第一电路部和第二电路部之间增加了连接部，增大了第一电路部和第二电路部之间的衬底电阻值，衬底电阻越大、电气隔离效果越好，热传导长度越长、热隔离效果也越好，从而提高了电路性能。
The present application provides a wafer, the wafer includes a plurality of chips arranged in sequence, the chip includes a first circuit part, a connection part and a second circuit part, and the two ends of the connection part are respectively connected The first circuit part and the second circuit part, the structure formed by the first circuit part, the connection part and the second circuit part has a concave part, and the part of the first circuit part of one wafer is embedded in the adjacent one of the wafers. In the concave portion, the second circuit part of the wafer is embedded in the concave portion of another adjacent wafer, and a dicing groove is formed between adjacent wafers, and the wafer is cut along the dicing groove to obtain a plurality of independent wafers. Due to the wafer provided by the present application, a connection portion is added between the first circuit portion and the second circuit portion, which increases the substrate resistance value between the first circuit portion and the second circuit portion, and the substrate resistance increases. Larger, better electrical isolation, longer thermal conduction length, better thermal isolation, thereby improving circuit performance.
Description
技术领域technical field
本申请涉及电子电路技术领域，尤其涉及一种晶圆。The present application relates to the technical field of electronic circuits, in particular to a wafer.
背景技术Background technique
现有技术中芯片一般被设计为近似方型，这样比较容易进行芯片的排布。图1为现有技术晶圆(Wafer)上晶片(Die)的排布示意图，每个晶片(Die)被切割、经过封装后叫芯片(Chip)，例如：8英寸晶圆通常指直径为8英寸的圆片，一般为硅片，通过光刻等加工步骤在晶圆上形成晶片图形。晶圆周围会存在一些不完整的晶片图形，这些都是废品。一般设计中会在晶片间设置一个间距，这个间距被称为划片槽或划片道(Scribe line)。Chips in the prior art are generally designed to be approximately square, which makes it easier to arrange the chips. Figure 1 is a schematic diagram of the arrangement of chips (Die) on a wafer (Wafer) in the prior art. Each chip (Die) is cut and packaged and called a chip (Chip). For example, an 8-inch wafer usually refers to a chip with a diameter of 8 Inch wafers, usually silicon wafers, form wafer patterns on wafers through photolithography and other processing steps. There will be some incomplete wafer pattern around the wafer, these are rejects. In the general design, a distance is set between the wafers, and this distance is called a scribe groove or a scribe line.
图2为放大后的一个晶片的示意图，其上存在两个模块：点划线左边的模块A和点划线右边的模块B，模块A可以为敏感的模拟电路或射频电路，模块B可以为噪声比较大的数字电路或功率电路。Figure 2 is an enlarged schematic diagram of a wafer, on which there are two modules: module A on the left side of the dotted line and module B on the right side of the dotted line, module A can be a sensitive analog circuit or a radio frequency circuit, and module B can be Digital circuits or power circuits with relatively large noise.
随着技术不断提高，模拟电路或射频电路的精度要求越来越高，其噪声设计需要更小。噪声(noise)性能越好，则模拟电路和射频电路可以实现更佳性能。With the continuous improvement of technology, the accuracy requirements of analog circuits or radio frequency circuits are getting higher and higher, and their noise design needs to be smaller. The better the noise performance, the better performance can be achieved by analog and radio frequency circuits.
然而，目前的模拟电路和射频电路通常噪声较大，而且还会影响敏感模拟电路和射频电路，导致电路性能不佳。However, current analog and RF circuits are often noisy and can also affect sensitive analog and RF circuits, resulting in poor circuit performance.
发明内容Contents of the invention
本申请实施例提出了一种晶圆，以解决现有技术中噪声大导致电路性能不佳的技术问题。The embodiment of the present application proposes a wafer to solve the technical problem of poor circuit performance due to high noise in the prior art.
本申请实施例提供了一种晶圆，所述晶圆包括按次序排布的多个晶片，所述晶片包括第一电路端、连接部和第二电路端，所述连接部的两端分别连接所述第一电路端和所述第二电路端，所述第一电路端、连接部和第二电路端形成的结构存在凹部，其中一个晶片的第一电路部的部分嵌入其相邻的一个晶片的凹部内，该一个晶片的第二电路部的部分嵌入相邻的另一个晶片的凹部内，相邻的晶片之间形成有划片槽，沿所述划片槽切割所述晶圆得到独立的多个晶片。An embodiment of the present application provides a wafer. The wafer includes a plurality of wafers arranged in sequence. The wafer includes a first circuit terminal, a connecting portion, and a second circuit end. The two ends of the connecting portion are respectively Connecting the first circuit end and the second circuit end, the structure formed by the first circuit end, the connection part and the second circuit end has a concave part, wherein a part of the first circuit part of one chip is embedded in its adjacent In the concave portion of one wafer, the second circuit part of the one wafer is embedded in the concave portion of another adjacent wafer, and a dicing groove is formed between the adjacent wafers, and the wafer is cut along the dicing groove Individual multiple wafers are obtained.
有益效果如下：Beneficial effects are as follows:
由于本申请实施例所提供的晶圆，在第一电路部和第二电路部之间增加了连接部，在制造芯片时相当于增加了第一电路部和第二电路部之间的衬底电阻，增大了第一电路部和第二电路部之间的衬底电阻值，衬底电阻越大、电气隔离效果越好，热传导长度越长、热隔离效果也越好，从而提高了电路性能。Due to the wafer provided by the embodiment of the present application, a connection part is added between the first circuit part and the second circuit part, which is equivalent to adding a substrate between the first circuit part and the second circuit part when manufacturing a chip The resistance increases the substrate resistance value between the first circuit part and the second circuit part. The larger the substrate resistance, the better the electrical isolation effect, the longer the heat conduction length, the better the thermal isolation effect, thus improving the circuit performance.
附图说明Description of drawings
下面将参照附图描述本申请的具体实施例，其中：Specific embodiments of the application will be described below with reference to the accompanying drawings, wherein:
图1为现有技术晶圆上晶片的排布示意图；FIG. 1 is a schematic diagram of the arrangement of chips on a wafer in the prior art;
图2为现有技术晶圆上的一个晶片放大后的示意图；FIG. 2 is an enlarged schematic diagram of a wafer on a wafer of the prior art;
图3示出了本申请实施例中所述晶片的结构示意图一；Fig. 3 shows the structural schematic diagram 1 of the wafer described in the embodiment of the present application;
图4示出了本申请实施例中所述晶圆的示意图一；FIG. 4 shows a first schematic diagram of the wafer described in the embodiment of the present application;
图5示出了本申请实施例中所述晶片的结构示意图二；Fig. 5 shows the structural schematic diagram II of the wafer described in the embodiment of the present application;
图6示出了本申请实施例中所述晶圆的示意图二；FIG. 6 shows a second schematic diagram of the wafer described in the embodiment of the present application;
图7示出了本申请实施例中所述晶片的结构示意图三；Fig. 7 shows a schematic structural diagram III of the wafer described in the embodiment of the present application;
图8示出了本身亲实施例中所述晶圆的示意图三。FIG. 8 shows a schematic diagram of the wafer described in the present embodiment.
具体实施方式detailed description
为了使本申请的技术方案及优点更加清楚明白，以下结合附图对本申请的示例性实施例进行进一步详细的说明，显然，所描述的实施例仅是本申请的一部分实施例，而不是所有实施例的穷举。并且在不冲突的情况下，本说明中的实施例及实施例中的特征可以互相结合。In order to make the technical solutions and advantages of the present application clearer, the exemplary embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all implementations. Exhaustive list of examples. And in the case of no conflict, the embodiments in this description and the features in the embodiments can be combined with each other.
发明人在发明过程中注意到：The inventor noticed during the invention that:
现有技术中，数字电路和功率电路则往往制造很大噪声，由于复杂的电路设计中，可能在同一个晶片上同时存在对噪声敏感模拟电路和数字电路，它们通过一个共同衬底承载，噪声会通过衬底进行传导。现有技术中一般通过设计隔离环(isolation ring)来改善，但效果有限。其次，数字电路高速工作时发热较大，功率电路以大电流工作时也会发热较大，根据其工作情况，发热还会变化，有时热、有时不热。高温也会通过下面的公共衬体传导到敏感的电路那侧。敏感的模拟电路和射频电路会被影响，一方面高温本身可能让模拟电路和射频电路的性能下降，另外温度不稳定也会导致其性能不稳定，还有一般情况下，温度升高也会导致模拟电路和射频电路自身的器件噪声增大，从而影响电路性能。In the prior art, digital circuits and power circuits often make a lot of noise. Due to the complex circuit design, noise-sensitive analog circuits and digital circuits may exist on the same chip at the same time, and they are carried by a common substrate, and the noise conduction through the substrate. In the prior art, it is generally improved by designing an isolation ring, but the effect is limited. Secondly, the digital circuit generates a lot of heat when it works at high speed, and the power circuit also generates a lot of heat when it works with a high current. According to its working conditions, the heat will change, sometimes it is hot, sometimes it is not hot. High temperatures are also conducted through the underlying common substrate to the sensitive circuit side. Sensitive analog circuits and radio frequency circuits will be affected. On the one hand, high temperature itself may degrade the performance of analog circuits and radio frequency circuits. In addition, unstable temperature will also lead to unstable performance. In general, temperature rise will also cause The device noise of the analog circuit and the radio frequency circuit itself increases, thereby affecting circuit performance.
针对上述不足，本申请实施例提出了一种晶圆，下面进行说明。In view of the above disadvantages, an embodiment of the present application proposes a wafer, which will be described below.
本申请实施例所提供的晶圆包括按次序排布的多个晶片，所述晶片包括第一电路部、连接部和第二电路部，所述连接部的两端分别连接所述第一电路部和所述第二电路部，所述第一电路部、连接部和第二电路部形成的结构存在凹部，其中一个晶片的第一电路部的部分嵌入其相邻的一个晶片的凹部内，该一个晶片的第二电路部的部分嵌入相邻的另一个晶片的凹部内，相邻的晶片之间形成有划片槽，沿所述划片槽切割所述晶圆得到独立的多个晶片。The wafer provided by the embodiment of the present application includes a plurality of wafers arranged in order, the wafer includes a first circuit part, a connection part and a second circuit part, and the two ends of the connection part are respectively connected to the first circuit part and the second circuit part, the structure formed by the first circuit part, the connection part and the second circuit part has a concave part, wherein a part of the first circuit part of one wafer is embedded in the concave part of an adjacent wafer, A part of the second circuit portion of one wafer is embedded in a concave portion of another adjacent wafer, a dicing groove is formed between adjacent wafers, and the wafer is cut along the dicing groove to obtain a plurality of independent wafers .
实施中，所述第一电路部、连接部和第二电路部均可以为矩形，所述连接部的宽度小于第一电路部和第二电路部的宽度。In implementation, the first circuit part, the connection part and the second circuit part may all be rectangular, and the width of the connection part is smaller than the width of the first circuit part and the second circuit part.
具体实施时，所述连接部的长边可以与所述第一电路部的第一边以及第二电路部的第一边垂直，所述第一电路部的第一边的边长和第二电路部的第一边的边长可以相同且大于所述连接部的宽度。During specific implementation, the long side of the connecting part may be perpendicular to the first side of the first circuit part and the first side of the second circuit part, and the length of the first side of the first circuit part and the second side The length of the first side of the circuit part may be the same and greater than the width of the connecting part.
具体实施时，所述第一电路部的第一边可以为矩形的长或宽，所述第二电路部的第一边可以为矩形的长或宽，所述第一电路部的第一边的边长和第二电路部的第一边的边长相同且可以远远大于所述连接部的宽度，例如：所述第一电路部的第一边的边长和第二电路部的第一边的边长相同且为所述连接部的宽度的N倍，N为5、6、6.1、7…等自然数；所述连接部的长度可以远远大于所述连接部的宽度，例如：所述长度是宽度的6倍等。During specific implementation, the first side of the first circuit part can be the length or width of a rectangle, the first side of the second circuit part can be the length or width of a rectangle, and the first side of the first circuit part can be The side length of the first side of the second circuit part is the same as the side length of the first side and can be much larger than the width of the connecting part, for example: the side length of the first side of the first circuit part and the second side of the second circuit part The length of one side is the same and is N times the width of the connecting portion, and N is a natural number such as 5, 6, 6.1, 7…; the length of the connecting portion can be much greater than the width of the connecting portion, for example: The length is 6 times the width, etc.
其中，所述第一电路部可以为高噪声电路，所述第二电路部可以为对噪声敏感的电路，所述第一电路部与第二电路部在划片后由所述连接部连接。Wherein, the first circuit part may be a high-noise circuit, the second circuit part may be a noise-sensitive circuit, and the first circuit part and the second circuit part are connected by the connecting part after dicing.
具体实施时，高噪声电路可以为高频噪声超过预设阈值的电路，例如：数字电路或者功率电路；对噪声敏感的电路则可以为模拟电路。During specific implementation, the high-noise circuit may be a circuit whose high-frequency noise exceeds a preset threshold, such as a digital circuit or a power circuit; the noise-sensitive circuit may be an analog circuit.
所述连接部可以为窄长型结构，可以起到隔离噪声和隔离热的效果。The connection part can be a narrow and long structure, which can have the effect of isolating noise and heat.
实施例一、Embodiment one,
图3示出了本申请实施例中所述晶片的结构示意图一，如图所示，所述晶片的连接部的两端分别连接所述第一电路部的一端和所述第二电路部的一端，所述第一电路部的另一端和所述第二电路部的另一端朝向同一方向。Fig. 3 shows a schematic diagram of the structure of the chip in the embodiment of the present application. As shown in the figure, the two ends of the connection part of the chip are respectively connected to one end of the first circuit part and one end of the second circuit part. One end, the other end of the first circuit part and the other end of the second circuit part face the same direction.
具体实施时，所述第一电路部的宽度与所述第二电路部的宽度可以相同、可以不同。假设第一电路部(图中左边部分)的宽度为b，b可以设计为敏感的模拟电路；第二电路部(图中右边部分)的宽度为c，c可以设计为噪声电路(例如：数字电路或功率电路)，第三部分为中间的连接部，用于左边部分和右边部分的相互电气连接，可以设置多根金属线来连接，也可以用多晶硅布线实现连接。During specific implementation, the width of the first circuit part and the width of the second circuit part may be the same or different. Assuming that the width of the first circuit part (the left part in the figure) is b, b can be designed as a sensitive analog circuit; the width of the second circuit part (the right part in the figure) is c, and c can be designed as a noise circuit (for example: digital circuit or power circuit), the third part is the connecting part in the middle, which is used for the mutual electrical connection of the left part and the right part, which can be connected by a plurality of metal wires, or can be connected by polysilicon wiring.
图4示出了本申请实施例中所述晶圆的示意图一，如图所示，为了实现晶圆面积的有效利用，本申请实施例将多个晶片进行如图所示的排列，以嵌套交错的方式排布。Fig. 4 shows a schematic diagram of the wafer described in the embodiment of the present application. Sets are arranged in a staggered manner.
具体实施时，第二晶片的第一电路部可以嵌入所述晶片的所述凹部并靠近所述凹部的一侧，第三晶片的第二电路部可以嵌入所述晶片的所述凹部并靠近所述凹部的另一侧。During specific implementation, the first circuit part of the second chip can be embedded in the concave part of the chip and close to one side of the concave part, and the second circuit part of the third chip can be embedded in the concave part of the chip and close to the side of the concave part. the other side of the recess.
具体实施时，第一个重复图形放置后，可以通过上下镜像产生第二个重复图形，以第二个重复图形的右边部分嵌入第一个重复图形的凹部，且靠近第一个重复图形的凹部的左侧放置；再通过上下镜像产生第三个重复图形，以第三个重复图形的左边部分嵌入第一个重复图形的凹部，且靠近第一个重复图形的凹部的右侧放置。In specific implementation, after the first repeated pattern is placed, the second repeated pattern can be generated by mirroring up and down, and the right part of the second repeated pattern is embedded in the concave part of the first repeated pattern, and it is close to the concave part of the first repeated pattern place on the left side; and generate a third repeated pattern by mirroring up and down, insert the left part of the third repeated pattern into the concave part of the first repeated pattern, and place it close to the right side of the concave part of the first repeated pattern.
以此类推，不断重复放置，直至填充满整个晶圆面积。By analogy, the placement is repeated until the entire wafer area is filled.
如果重复图形的左边部分宽度设计为b，重复图形的右边部分宽度设计为c，划片槽宽度设计为a，则连接部的长度d可以设计为d＝b+c+3a，这样可以正好紧密的填充晶圆面积。If the width of the left part of the repeating pattern is designed as b, the width of the right part of the repeating pattern is designed as c, and the width of the scribe groove is designed as a, then the length d of the connecting part can be designed as d=b+c+3a, which can be just tight of filled wafer area.
图4中的虚线描述了晶圆制造完成后进行划片的位置，划片时沿着点划线进行划片，以形成分割和隔离的效果。The dotted line in Figure 4 describes the dicing position after the wafer is manufactured, and the dicing is performed along the dotted line to form the effect of segmentation and isolation.
具体实施时，可以采用激光切割等方式进行划片。During specific implementation, scribing may be performed by means of laser cutting or the like.
实施例二、Embodiment two,
图5示出了本申请实施例中所述晶片的结构示意图二，如图所示，所述连接部的两端分别连接所述第一电路部的中部和所述第二电路部的中部，所述第一电路部的两端所在的直线与所述第二电路部的两端所在的直线平行，所述第一电路部、连接部和第二电路部形成的结构存在两个凹部，所述两个凹部的开口方向相反。Fig. 5 shows a schematic structural diagram II of the wafer in the embodiment of the present application. As shown in the figure, the two ends of the connecting part are respectively connected to the middle part of the first circuit part and the middle part of the second circuit part, The straight line where the two ends of the first circuit part are located is parallel to the straight line where the two ends of the second circuit part are located, and there are two concave parts in the structure formed by the first circuit part, the connecting part and the second circuit part, so The opening directions of the two recesses are opposite.
如图所示，与实施例一不同之处在于，所述连接部设置于左边部分和右边部分的上下方向的中间位置。As shown in the figure, the difference from the first embodiment is that the connecting portion is arranged at the middle position in the up-down direction of the left part and the right part.
图6示出了本申请实施例中所述晶圆的示意图二，如图所示，为了实现晶圆面积的有效利用，本申请实施例将多个晶片进行如图所示的排列，以嵌套交错的方式排布。Fig. 6 shows the second schematic diagram of the wafer described in the embodiment of the present application. As shown in the figure, in order to realize the effective utilization of the wafer area, the embodiment of the present application arranges a plurality of wafers as shown in the figure to embed Sets are arranged in a staggered manner.
具体实施时，第二晶片的第一电路部嵌入所述晶片的第一凹部并靠近所述第一凹部的一侧，第三晶片的第二电路部嵌入所述晶片的第一凹部并靠近所述第一凹部的另一侧；第四晶片的第一电路部嵌入所述晶片的第二凹部并靠近所述第二凹部的一侧，第五晶片的第二电路部嵌入所述晶片的第二凹部并靠近所述第二凹部的另一侧。During specific implementation, the first circuit portion of the second chip is embedded in the first concave portion of the chip and is close to one side of the first concave portion, and the second circuit portion of the third chip is embedded in the first concave portion of the chip and is close to the side of the first concave portion. the other side of the first recess; the first circuit part of the fourth chip is embedded in the second recess of the chip and is close to the side of the second recess, and the second circuit part of the fifth chip is embedded in the first part of the chip The second recess is close to the other side of the second recess.
当设计满足d＝b+c+3*a时，可以实现正好紧密的排布方式。When the design satisfies d=b+c+3*a, a just tight arrangement can be achieved.
图6中点划线描述了晶圆制造完成后进行划片的位置，划片时沿着点划线进行划片，以形成分割和隔离的效果。The dot-dash line in FIG. 6 describes the position for dicing after the wafer is manufactured, and the dicing is performed along the dot-dash line to form the effect of segmentation and isolation.
具体实施时，可以采用激光切割等方式进行划片。During specific implementation, scribing may be performed by means of laser cutting or the like.
实施例三、Embodiment three,
图7示出了本申请实施例中所述晶片的结构示意图三，如图所示，所述连接部包括第一水平端、第二水平端和U型部，所述第一水平端用于连接第一电路部与U型部，所述第二水平端用于连接U型部与第二电路部。Fig. 7 shows the third structural schematic view of the wafer in the embodiment of the present application. As shown in the figure, the connecting part includes a first horizontal end, a second horizontal end and a U-shaped part, and the first horizontal end is used for The first circuit part is connected with the U-shaped part, and the second horizontal end is used for connecting the U-shaped part with the second circuit part.
本申请实施例中所述连接部可以设计为曲线形状，例如U型。In the embodiment of the present application, the connecting part may be designed in a curved shape, such as a U shape.
图8示出了本身亲实施例中所述晶圆的示意图三，如图所示，所述多个晶片可以依次排列，所述点划线描述了晶圆制造完成后进行划片的位置。FIG. 8 shows a schematic diagram 3 of the wafer in the first embodiment. As shown in the figure, the plurality of wafers can be arranged in sequence, and the dotted line describes the position for dicing after the wafer is manufactured.
具体实施时，所述U型部可以为多个，所述连接部还可以包括第三水平端，所述第三水平端用于连接U型部与U型部。In a specific implementation, there may be multiple U-shaped parts, and the connecting part may further include a third horizontal end, and the third horizontal end is used to connect the U-shaped parts with the U-shaped parts.
由于本申请实施例所提供的晶圆，在第一电路部和第二电路部之间增加了连接部，在制造芯片时相当于增加了第一电路部和第二电路部之间的衬底电阻，增大了第一电路部和第二电路部之间的衬底电阻值，衬底电阻越大、电气隔离效果越好，热传导长度越长、热隔离效果也越好，从而提高了电路性能。Due to the wafer provided by the embodiment of the present application, a connection part is added between the first circuit part and the second circuit part, which is equivalent to adding a substrate between the first circuit part and the second circuit part when manufacturing a chip The resistance increases the substrate resistance value between the first circuit part and the second circuit part. The larger the substrate resistance, the better the electrical isolation effect, the longer the heat conduction length, the better the thermal isolation effect, thus improving the circuit performance.
具体实施时，所述连接部可以通过设置多根金属线连接所述第一电路部和第二电路部，或者，通过多晶硅布线连接所述第一电路部和第二电路部。During specific implementation, the connection part may connect the first circuit part and the second circuit part by arranging a plurality of metal wires, or connect the first circuit part and the second circuit part by polysilicon wiring.
所述连接部还可以包括接触孔(Contact)，所述接触孔用于连接多晶硅和金属。The connection part may further include a contact hole (Contact), and the contact hole is used for connecting polysilicon and metal.
所述连接部还可以包括通孔(VIA)，所述通孔用于连接不同层的金属。The connection part may also include a via (VIA) for connecting metals of different layers.
具体实施时，还可以在下层设置交替的P+和N+隔离层、或者P+/Pwell和N+/Nwell隔离层。During specific implementation, alternate P+ and N+ isolation layers, or P+/Pwell and N+/Nwell isolation layers can also be arranged on the lower layer.
其中，P+可以通过金属连接到芯片的最低电位，N+可以通过金属连接到芯片的最高电位。Among them, P+ can be connected to the lowest potential of the chip through metal, and N+ can be connected to the highest potential of the chip through metal.
现有技术中，如图2所示，计算等效的左部电路和右部电路之间的衬底电阻方块数时，衬底电阻方块的长度可以近似为从左部中间到右部中间的距离。如果左部宽度为b，右部宽度为c，芯片的高度为e，则左部电路和右部电路之间的衬底电阻方块数可以近似为(b/2+c/2)/e，等效的左部电路和右部电路之间的衬底电阻值为Rsq*(b/2+c/2)/e。In the prior art, as shown in Figure 2, when calculating the number of substrate resistance squares between the equivalent left circuit and the right circuit, the length of the substrate resistance squares can be approximately from the middle of the left part to the middle of the right part distance. If the width of the left part is b, the width of the right part is c, and the height of the chip is e, the number of substrate resistance squares between the left circuit and the right circuit can be approximated as (b/2+c/2)/e, The equivalent substrate resistance between the left and right circuits is Rsq*(b/2+c/2)/e.
而采用本申请实施例所提供的技术方案，以图4为例，由于本申请实施例增加了左部电路和右部电路之间的衬底电阻，假设衬底电阻的方块阻值为Rsq，等效的左部电路和右部电路之间的衬底电阻方块数可以近似为((b/2+c/2)/e+d/w)，等效的左部电路和右部电路之间的衬底电阻值为Rsq*((b/2+c/2)/e+d/w)。其中d为中间连接部的长度，w中间连接部的宽度。Using the technical solution provided by the embodiment of the present application, taking Fig. 4 as an example, since the embodiment of the present application increases the substrate resistance between the left circuit and the right circuit, assuming that the square resistance of the substrate resistance is Rsq, The number of substrate resistance squares between the equivalent left circuit and the right circuit can be approximated as ((b/2+c/2)/e+d/w), the equivalent left circuit and the right circuit The substrate resistance value between them is Rsq*((b/2+c/2)/e+d/w). Wherein d is the length of the middle connecting part, w is the width of the middle connecting part.
很明显的可以看出，采用本申请实施例所提供的方案，等效电阻较大，电气隔离的效果更佳。It can be clearly seen that, by adopting the solution provided by the embodiment of the present application, the equivalent resistance is larger, and the effect of electrical isolation is better.
以图7为例，等效的左部电路和右部电路之间的衬底电阻可以近似正比于弯曲连接部的长度，因此弯曲越多，弯曲长度越大，其等效左部电路和右部电路之间的衬底电阻越大，隔离效果越好。同样，热传导长度越长，热隔离效果也越佳。Taking Fig. 7 as an example, the substrate resistance between the equivalent left circuit and the right circuit can be approximately proportional to the length of the bent connection part, so the more bends, the greater the bend length, and the equivalent left and right circuits The greater the substrate resistance between internal circuits, the better the isolation. Likewise, the longer the heat conduction length, the better the thermal isolation.
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。While preferred embodiments of the present application have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once the basic inventive concept is appreciated. Therefore, the appended claims are intended to be construed to cover the preferred embodiment and all changes and modifications which fall within the scope of the application.
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| CN109686734A (en) * | 2018-11-27 | 2019-04-26 | 合肥中感微电子有限公司 | Chip with isolation structure |
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| US20010055855A1 (en) * | 2000-06-27 | 2001-12-27 | Frank Fischer | Method for sectioning a substrate wafer into a plurality of substrate chips |
| CN101093824A (en) * | 2006-06-20 | 2007-12-26 | 台湾积体电路制造股份有限公司 | Interconnect structure and chip |
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