CN112071899A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN112071899A
CN112071899A CN202011243355.5A CN202011243355A CN112071899A CN 112071899 A CN112071899 A CN 112071899A CN 202011243355 A CN202011243355 A CN 202011243355A CN 112071899 A CN112071899 A CN 112071899A
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region
substrate
injection region
lead
doping type
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李晓锋
黄富强
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Zhejiang Liyang Semiconductor Co ltd
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Zhejiang Liyang Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A semiconductor structure and its preparation method, its structure includes the substrate of the first doping type, cross-over area, first injection region and second injection region are the second doping type, define the ditch groove area on the cross-over area, the ditch groove area divides the substrate into multiple chip areas; the first injection region and the second injection region are both communicated with the penetration region. The first injection region and the substrate form a PN junction, the second injection region and the substrate also form a PN junction, and the first injection region and the second injection region are communicated through the through region, so various devices of the PN junction can be formed in the substrate, the device can select to lead out electrodes at different positions according to the requirement of circuit design, and the device can be processed into devices with different functions.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
Different doping processes are adopted, and a P-type semiconductor and an N-type semiconductor are manufactured on the same semiconductor (usually silicon or germanium) substrate through diffusion, and space charge regions called PN junctions are formed at the interfaces of the P-type semiconductor and the N-type semiconductor. PN junctions have unidirectional conductivity and are a property utilized by many devices in electronics, and PN junctions are the material basis for commonly used devices such as semiconductor diodes, bipolar transistors. With the development of Integrated Circuits (ICs), the semiconductor industry has experienced rapid growth due to continued improvements in the integration density of individual semiconductor devices (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the ever-decreasing minimum feature size, which allows more components to be integrated into a given area.
With the development of intelligent household appliances of various sizes, the usage scenarios of semiconductor devices are more and more frequent, even multiple semiconductor devices need to be integrated in one integrated circuit board, and different customers have different circuit designs, so that semiconductor devices with different functions need to be integrated in an application circuit board in different packaging modes, and the semiconductor devices with different functions and different packaging modes need different processing or manufacturing modes, resulting in higher manufacturing cost.
Therefore, it is desirable to provide a semiconductor structure and a method for fabricating the same, which can be used in different usage scenarios, and can be processed into devices with different functions according to the requirements of circuit design, thereby improving efficiency and reducing production cost.
Disclosure of Invention
The invention provides a semiconductor structure and a manufacturing method thereof, which can be rapidly processed into devices with different functions according to requirements, improve the production efficiency and reduce the production cost.
According to a first aspect, an embodiment provides a method of fabricating a semiconductor structure, comprising:
providing a substrate of a first doping type, the substrate having a first surface and a second surface opposite to the first surface;
adopting a punch-through process to punch through the substrate to form a punch-through area, wherein the punch-through area is of a second doping type, a groove area is defined on the punch-through area, and the groove area divides the substrate into a plurality of chip areas;
forming a first injection region on the first surface of the substrate and a second injection region on the second surface of the substrate by adopting a diffusion process; the first injection region is positioned in the substrate which is deep along part of the first surface, and the first injection region and the through region have the same doping type and are communicated with each other; the second injection region is positioned in the substrate which is deep along the second surface, and the second injection region and the through region have the same doping type and are communicated with each other.
In some embodiments, further comprising: and forming a third injection region by adopting a diffusion process, wherein the third injection region is positioned in the substrate which is deep along part of the first surface and is not communicated with the first injection region, and the third injection region and the through region have the same doping type.
In some embodiments, further comprising:
passivating the surface of the substrate by adopting a passivation process;
adopting a photoetching process, using a light resistance as a mask, and etching to expose a lead-out electrode window;
and depositing a metal layer on the conductive window to form an electrode.
In some embodiments, the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and etching includes:
etching to expose the surface of the second injection region and the surface of the rest part of the first surface except the first injection region as a lead-out electrode window;
in some embodiments, the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and etching includes:
etching to expose the surface of the first implantation region and the surface of the rest part of the first surface except the first implantation region as a lead-out electrode window.
In some embodiments, the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and etching includes:
etching to expose the surface of the first implantation region, the surface of the third implantation region and the surface of the rest part of the first surface except the first implantation region and the third implantation region to be used as a lead-out electrode window.
In some embodiments, the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and etching includes:
etching to expose the surface of the second injection region, the surface of the third injection region and the surface of the rest part of the first surface except the first injection region and the third injection region to be used as a lead-out electrode window.
In some embodiments, the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and etching includes:
etching to expose the surface of the first implantation region and the surface of the third implantation region as a lead-out electrode window.
In some embodiments, the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and etching includes:
etching to expose the second and third implantation region surfaces as a lead-out electrode window.
In some embodiments, after depositing the metal layer on the conductive window and forming the electrode, the method further includes:
and cutting in the defined groove region to separate the chip regions.
According to a second aspect, an embodiment provides a semiconductor structure comprising:
a substrate of a first doping type, the substrate having a first surface and a second surface opposite the first surface;
the through area is arranged in the substrate, the through area is of a second doping type, a groove area is defined on the through area, and the groove area divides the substrate into a plurality of chip areas;
the first injection region is positioned in the substrate which is deep along part of the first surface, and the first injection region and the through region have the same doping type and are communicated with each other;
and a second implantation region located inside the substrate deep along the second surface, the second implantation region having the same doping type as the through region and being in communication with the through region.
In some embodiments, further comprising: and the third injection region is positioned in the substrate which is deep along part of the first surface and is not communicated with the first injection region, and the doping type of the third injection region is the same as that of the through region.
According to the manufacturing method of the semiconductor structure of the embodiment, the first injection region and the second injection region are respectively arranged in the directions of the first surface and the second surface of the substrate, wherein the first injection region and the substrate can form a PN junction, the second injection region and the substrate can also form a PN junction, and the first injection region and the second injection region are communicated through the through region, so that various devices of the PN junction can be formed in the substrate, and the devices can select to lead out electrodes at different positions according to the requirements of circuit design, so that the devices with different functions are processed, the application flexibility is improved, and because the preorder process is fixed, a mask or other etching steps are not required to be designed any more, the production efficiency can be improved, and the manufacturing cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
FIGS. 2-4 are schematic views of semiconductor device structures provided in various embodiments of the present invention;
FIG. 5 is a schematic view of a semiconductor structure according to another embodiment of the present invention;
fig. 6-10 are schematic views of semiconductor device structures provided in various embodiments of the present invention;
fig. 11 and 12 are flowcharts of methods for manufacturing semiconductor devices according to various embodiments of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
It can be known from analysis that different semiconductor devices need to be designed according to different integrated circuits when packaged, and different package structures affect the chip design structures of the semiconductor devices, so that the manufacturing process needs to be redesigned according to the semiconductor devices required by each customer in the manufacturing process of the semiconductor devices, and particularly, various photolithographic mask designs are involved in the manufacturing process, which greatly increases the production and manufacturing costs, and the process has low repeatability, and the design and manufacturing needs to consume time and labor, thereby greatly reducing the production efficiency.
Semiconductor devices with different functions are required to be integrated in an application circuit board in different packaging modes, and the semiconductor devices with different functions and different packaging modes require different processing or manufacturing modes, so that the manufacturing cost is high.
In an embodiment of the present invention, a semiconductor structure and a manufacturing method thereof are provided, in which the semiconductor structure manufactured by the method includes a substrate of a first doping type, a punch-through region, a first injection region and a second injection region, the punch-through region, the first injection region and the second injection region are of a second doping type, a trench region is defined on the punch-through region, and the substrate is divided into a plurality of chip regions by the trench region; the first injection region is positioned in the substrate which is deep along part of the first surface and is communicated with the through region; and the second injection region is positioned in the substrate deep along the second surface and communicated with the through region. The first injection region and the substrate form a PN junction, the second injection region and the substrate also form a PN junction, and the first injection region and the second injection region are communicated through the through region, so various devices of the PN junction can be formed in the substrate, the device can select to lead out electrodes at different positions according to the requirement of circuit design, and the device can be processed into devices with different functions.
Example one
Referring to fig. 1, the present embodiment provides a semiconductor structure, including: the semiconductor device comprises a substrate of a first doping type, a through region, a first injection region and a second injection region.
The substrate 100 of the first doping type has a first surface 101 and a second surface 102 opposite to said first surface 101.
In this embodiment, the substrate 100 is a silicon substrate, and impurity doping is performed in the silicon substrate to form the substrate 100 of the first doping type.
The first doping type can be N-type semiconductor doping or P-type semiconductor doping. When an N-type semiconductor is doped, a small amount of phosphorus (or antimony) as an impurity may be doped into the substrate 100; when the P-type semiconductor is doped, a small amount of boron (or indium) as an impurity may be doped into the substrate 100.
In this embodiment, the substrate 100 is doped N-type.
In some embodiments, the substrate 100 is doped P-type.
The through region 110 disposed inside the substrate is of the second doping type, and a trench region (not shown) is defined on the through region 110, and the trench region divides the substrate 100 into a plurality of chip regions.
The second doping type can be N-type semiconductor doping or P-type semiconductor doping. When an N-type semiconductor is doped, a small amount of phosphorus (or antimony) as an impurity may be doped into the substrate 100; when the P-type semiconductor is doped, a small amount of boron (or indium) as an impurity may be doped into the substrate 100.
It should be noted that, when the first doping type is N-type semiconductor doping, the second doping type is P-type semiconductor doping; when the first doping type is P-type semiconductor doping, the second doping type is N-type semiconductor doping.
In this embodiment, the punch-through region 110 is a P-type doped punch-through along the thickness of the substrate 100.
In some embodiments, the punch-through region 110 is an N-type doped punch-through along the thickness of the substrate 100.
As shown in fig. 1, a first implantation region 201 is located inside the substrate along a portion of the first surface 101, and the first implantation region 201 has the same doping type as the through region 110 and is communicated with the through region 110.
A second implanted region 202 is located within the substrate deep along the second surface 102, the second implanted region 202 having the same doping type as the pass-through region 110 and being in communication with the pass-through region 110.
Because the first injection region 201 in this embodiment is P-type, it forms a PN junction with the N-type substrate 100, the second injection region 202 also forms a PN junction with the substrate 100, and because the first injection region 201 and the second injection region 202 are communicated through the punch-through region 110, it forms a PN junction, and the device can select to lead out electrodes at different positions according to the requirement of circuit design, thereby processing into devices with different functions, and having strong application flexibility.
Referring to fig. 2, the PN junction semiconductor structure of the present embodiment may have three external electrode positions, which are a first electrode position 301, a second electrode position 302 and a third electrode position 303, respectively, where the first electrode position 301 is located on the surface of the rest portion of the first surface except the first injection region 201; the second electrode site 302 is located at the surface of the second implant region 202 and the third electrode site 303 is located at the surface of the first implant region.
In some embodiments, referring to fig. 3, the second implantation region 202 has a metal layer on the surface thereof, and the rest of the surface of the first surface 101 has a metal layer thereon.
In some embodiments, referring to fig. 4, the first implantation region 201 has a metal layer on a surface thereof, and the rest of the first surface has a metal layer on a surface thereof.
In this embodiment, a flow chart of a method for fabricating a semiconductor structure is also provided, with reference to fig. 11, the method includes:
step 1, providing a substrate of a first doping type, wherein the substrate is provided with a first surface and a second surface opposite to the first surface.
In this embodiment, the substrate 100 is a silicon substrate, and impurity doping is performed in the silicon substrate to form the substrate 100 of the first doping type.
The first doping type can be N-type semiconductor doping or P-type semiconductor doping. When an N-type semiconductor is doped, a small amount of phosphorus (or antimony) as an impurity may be doped into the substrate 100; when the P-type semiconductor is doped, a small amount of boron (or indium) as an impurity may be doped into the substrate 100.
In this embodiment, the substrate 100 is doped N-type.
In some embodiments, the substrate 100 is doped P-type.
And 2, adopting a punch-through process to punch through the substrate to form a punch-through area, wherein the punch-through area is of a second doping type, a groove area is defined on the punch-through area, and the groove area divides the substrate into a plurality of chip areas.
The second doping type can be N-type semiconductor doping or P-type semiconductor doping. When an N-type semiconductor is doped, a small amount of phosphorus (or antimony) as an impurity may be doped into the substrate 100; when the P-type semiconductor is doped, a small amount of boron (or indium) as an impurity may be doped into the substrate 100.
It should be noted that, when the first doping type is N-type semiconductor doping, the second doping type is P-type semiconductor doping; when the first doping type is P-type semiconductor doping, the second doping type is N-type semiconductor doping.
For example, a punch-through process is used to fabricate a P-type punch-through region on an N-type silicon wafer, which may also function as a punch-through isolation layer.
In this embodiment, the punch-through region 110 is a P-type doped punch-through along the thickness of the substrate 100.
In some embodiments, the punch-through region 110 is an N-type doped punch-through along the thickness of the substrate 100.
Step 3, forming a first injection region on the first surface of the substrate and forming a second injection region on the second surface by adopting a diffusion process; the first injection region is positioned in the substrate which is deep along part of the first surface, and the first injection region and the through region have the same doping type and are communicated with each other; the second injection region is positioned in the substrate which is deep along the second surface, and the second injection region and the through region have the same doping type and are communicated with each other.
In this embodiment, the mask layer in the diffusion process is made of silicon dioxide.
And manufacturing a P-type layer or an N-type layer on two sides of the substrate by using a planar diffusion method to form a PN junction.
The size and number of PN junctions to be formed can be adjusted as desired.
In this embodiment, the junction depth of the PN junction formed by the diffusion process may be 30 to 60 um; the longer the diffusion time, the deeper the junction; the longer the diffusion time, the higher the voltage. Different voltage products need different diffusion time and can be manufactured according to the requirements of specific products.
And 4, passivating the surface of the substrate by adopting a passivation process.
In this embodiment, the passivation may be performed by thermal oxidation, for example: oxygen + dry oxygen or hydrogen-oxygen synthesis, or Silicon (Semi-Insulating polysilicon) deposition or Silicon nitride deposition, or Silicon + Silicon nitride, or Silicon + thermal Oxidation, or LTO (Low Temperature Silicon dioxide) is added on the passivation layer.
In this embodiment, when the oxide layer is used as the passivation layer, the thickness thereof may be 12 k a-14 k a, which may be adjusted according to the process requirements.
When the passivation layer is Sipos, the thickness of the passivation layer can be 3k A-23 k A and can be adjusted according to the process requirement.
When LTO is selected as the passivation layer, the thickness of the LTO can be 4 kA-8 kA and can be adjusted according to the process requirement.
When the passivation layer is selected from Si3N4 (silicon nitride), the thickness thereof can be 700-.
And 5, adopting a photoetching process, using the light resistance as a mask, and etching to expose the lead-out electrode window.
After the process is carried out, when the lead-out electrode window is exposed by etching, various etching methods can be adopted, so that the lead-out electrode window can be used at different positions to form devices with different functions.
And 6, depositing a metal layer on the conductive window to form an electrode.
For example, there may be three positions of the external electrodes, which are a first electrode position 301, a second electrode position 302 and a third electrode position 303, respectively, wherein the first electrode position 301 is located on the surface of the rest part of the first surface except the first implantation region 201; the second electrode site 302 is located at the surface of the second implant region 202 and the third electrode site 303 is located at the surface of the first implant region.
In some embodiments, a metal layer is located at first electrode location 301 and third electrode location 303.
In some embodiments, metal layers are located at second electrode locations 302 and first electrode locations 301, which may be suitable for encapsulation when circuit terminals are across the device.
In this embodiment, depositing a metal layer on the conductive window, and after forming an electrode, further includes:
and cutting in the defined groove region to separate the chip regions.
In some embodiments, after each of the chip regions is diced and separated, the side surfaces of the chip regions can be passivated to ensure the effectiveness of the function of the device.
Example two
The difference between this embodiment and the first embodiment is that the structure further includes a third implantation region, where the third implantation region is located inside the substrate deep along a portion of the first surface and is not connected to the first implantation region. The rest of the embodiment is the same as the embodiment, and in order to avoid redundancy of the article, the embodiment only provides detailed description for the difference.
Referring to fig. 5, in the present embodiment, the structure further includes a third implantation region 203 located inside the substrate 100 along a portion of the first surface 101, and not connected to the first implantation region 201, where the third implantation region 203 and the through region 110 have the same doping type.
Since the third implantation region 203 in this embodiment is P-type and forms a PN junction with the N-type substrate 100, a PN junction is formed, and the structure has two PN junctions, and is a PNP structure or an NPN structure, electrodes are selectively led out at different positions according to the requirements of circuit design, and can be processed into devices with different functions, such as a triode or a bidirectional TVS, or can be used as a diode or a unidirectional TVS.
Referring to fig. 6, the PN junction semiconductor structure of the present embodiment may have four external electrode positions, which are a first electrode position 401, a second electrode position 402, a third electrode position 403, and a fourth electrode position 404, where the first electrode position 401 is located on the surface of the first injection region 201, the second electrode position 402 is located on the surface of the rest of the first surface except the first injection region and the third injection region, the third electrode position 403 is located on the surface of the third injection region 203, and the fourth electrode position 404 is located on the surface of the second injection region 202.
Referring to fig. 7, in some embodiments, the surface of the first implantation region 201 has a metal layer, the surface of the third implantation region 203 has a metal layer, and the rest of the surface of the first surface 101 except the first implantation region 201 and the third implantation region 203 has a metal layer, that is, the metal layers are located at the first electrode position 401 and the second electrode position 402.
By the access mode of the electrode, a unidirectional TVS can be formed, and also can be a rectifier diode or other PN junction devices, and the external electrodes of the devices are on the same surface, so that the device can be suitable for a packaging form directly attached to a PCB.
Referring to fig. 8, in some embodiments, the surface of the second implantation region 202 has a metal layer, the surface of the third implantation region 203 has a metal layer, and the rest of the surface of the first surface 101 except the first implantation region 201 and the third implantation region 203 has a metal layer, that is, the metal layer is located at the fourth electrode position 404, the third electrode position 403 and the second electrode position 402.
By the access mode of the electrode, a device with a PNP structure can be formed, the PNP device can be a triode device, and the device is suitable for packaging when a circuit terminal is arranged at two ends of the device.
Referring to fig. 9, in some embodiments, the surface of the first injection region 201 has a metal layer, and the surface of the third injection region 203 has a metal layer, that is, the metal layers are located at the first electrode position 401 and the third electrode position 403.
By the electrode wiring mode, the formed device can be a bidirectional TVS device, and the external electrodes of the device are on the same surface, so that the device can be suitable for packaging directly attached to a PCB.
Referring to fig. 10, in some embodiments, the second implant region 202 has a metal layer on its surface and the third implant region 203 has a metal layer on its surface, i.e., the metal layers are located at the fourth electrode location 404 and the third electrode location 403.
Through such an electrode wiring manner, the formed device may be a bidirectional TVS device, which may be the same as the device in the embodiment corresponding to fig. 9, but external electrodes of the device in this embodiment are respectively at two ends, which may be suitable for packaging when circuit terminals are at two ends of the device.
Referring to fig. 12, a method for fabricating a semiconductor structure is further provided in this embodiment, which is different from the first embodiment in that the method further includes forming a third implantation region by using a diffusion process, where the third implantation region is located in the substrate deep along a portion of the first surface and is not connected to the first implantation region. The rest of the embodiment is the same as the first embodiment, and in order to avoid redundancy of the text, the embodiment only provides detailed descriptions for the difference.
Step 1, providing a substrate of a first doping type, wherein the substrate is provided with a first surface and a second surface opposite to the first surface.
And 2, adopting a punch-through process to punch through the substrate to form a punch-through area, wherein the punch-through area is of a second doping type, a groove area is defined on the punch-through area, and the groove area divides the substrate into a plurality of chip areas.
Step 3, forming a first injection region on the first surface of the substrate and forming a second injection region on the second surface by adopting a diffusion process; the first injection region is positioned in the substrate which is deep along part of the first surface, and the first injection region and the through region have the same doping type and are communicated with each other; the second injection region is positioned in the substrate which is deep along the second surface, and the second injection region and the through region have the same doping type and are communicated with each other.
In this embodiment, between step 3 and step 4, the method further includes:
and 31, forming a third injection region by adopting a diffusion process, wherein the third injection region is positioned in the substrate which is deep along part of the first surface and is not communicated with the first injection region, and the doping type of the third injection region is the same as that of the through region.
And 4, passivating the surface of the substrate by adopting a passivation process.
And 5, adopting a photoetching process, using the light resistance as a mask, and etching to expose the lead-out electrode window.
Referring to fig. 6, in this embodiment, a photolithography process is adopted, a photoresist is used as a mask, etching is performed, and a lead-out electrode window is exposed, and the formed semiconductor structure may have four positions of an external electrode, which are a first electrode position 401, a second electrode position 402, a third electrode position 403, and a fourth electrode position 404, respectively, where the first electrode position 401 is located on the surface of the first injection region 201, the second electrode position 402 is located on the surface of the first surface except for the rest surfaces of the first injection region and the third injection region, the third electrode position 403 is located on the surface of the third injection region 203, and the fourth electrode position 404 is located on the surface of the second injection region 202.
And 6, depositing a metal layer on the conductive window to form an electrode.
In some embodiments, by using a photolithography process and a photoresist as a mask, and performing etching, the surface of the first implantation region, the surface of the third implantation region, and the surface of the remaining portion of the first surface excluding the first implantation region and the third implantation region may be exposed to serve as a lead-out electrode window.
In some embodiments, by using a photolithography process and a photoresist as a mask, and performing etching, the surface of the second implantation region, the surface of the third implantation region, and the surface of the remaining portion of the first surface excluding the first implantation region and the third implantation region may be exposed to serve as a lead-out electrode window.
In some embodiments, by using a photolithography process and a photoresist as a mask, and performing etching, the surface of the first injection region and the surface of the third injection region may be exposed to serve as a lead-out electrode window.
In some embodiments, the surface of the second injection region and the surface of the third injection region may be exposed as a lead-out electrode window by etching using a photolithography process and using a photoresist as a mask.
In this embodiment, depositing a metal layer on the conductive window, and after forming an electrode, further includes:
and cutting the defined groove region to separate each chip region, and passivating the side surface of each chip region to ensure the functional effectiveness of the device.
The semiconductor structure and the manufacturing method thereof provided in this embodiment can select to lead out electrodes at different positions according to the requirements of circuit design, so as to process the semiconductor structure into devices with different functions, thereby improving the flexibility of application.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims (10)

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate of a first doping type, the substrate having a first surface and a second surface opposite to the first surface;
adopting a punch-through process to punch through the substrate to form a punch-through area, wherein the punch-through area is of a second doping type, a groove area is defined on the punch-through area, and the groove area divides the substrate into a plurality of chip areas;
forming a first injection region on the first surface of the substrate and a second injection region on the second surface of the substrate by adopting a diffusion process; the first injection region is positioned in the substrate which is deep along part of the first surface, and the first injection region and the through region have the same doping type and are communicated with each other; the second injection region is positioned in the substrate which is deep along the second surface, and the second injection region and the through region have the same doping type and are communicated with each other.
2. The method of manufacturing of claim 1, further comprising: and forming a third injection region by adopting a diffusion process, wherein the third injection region is positioned in the substrate which is deep along part of the first surface and is not communicated with the first injection region, and the third injection region and the through region have the same doping type.
3. The method of manufacturing of claim 2, further comprising:
passivating the surface of the substrate by adopting a passivation process;
adopting a photoetching process, using a light resistance as a mask, and etching to expose a lead-out electrode window;
and depositing a metal layer on the lead-out electrode window to form an electrode.
4. The method of claim 3, wherein the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and performing etching comprises:
etching to expose the surface of the second injection region and the surface of the rest part of the first surface except the first injection region as a lead-out electrode window;
alternatively, the first and second electrodes may be,
etching to expose the surface of the first implantation region and the surface of the rest part of the first surface except the first implantation region as a lead-out electrode window.
5. The method of claim 3, wherein the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and performing etching comprises:
etching to expose the surface of the first implantation region, the surface of the third implantation region and the surface of the rest part of the first surface except the first implantation region and the third implantation region to be used as a lead-out electrode window.
6. The method of claim 3, wherein the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and performing etching comprises:
etching to expose the surface of the second injection region, the surface of the third injection region and the surface of the rest part of the first surface except the first injection region and the third injection region to be used as a lead-out electrode window.
7. The method of claim 3, wherein the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and performing etching comprises:
etching to expose the surface of the first injection region and the surface of the third injection region as a lead-out electrode window;
alternatively, the first and second electrodes may be,
etching to expose the second and third implantation region surfaces as a lead-out electrode window.
8. The method of claim 3, wherein depositing a metal layer over the exit electrode window, after forming the electrode, further comprises:
and cutting in the defined groove region to separate the chip regions.
9. A semiconductor structure, comprising:
a substrate of a first doping type, the substrate having a first surface and a second surface opposite the first surface;
the through area is arranged in the substrate, the through area is of a second doping type, a groove area is defined on the through area, and the groove area divides the substrate into a plurality of chip areas;
the first injection region is positioned in the substrate which is deep along part of the first surface, and the first injection region and the through region have the same doping type and are communicated with each other;
and a second implantation region located inside the substrate deep along the second surface, the second implantation region having the same doping type as the through region and being in communication with the through region.
10. The semiconductor structure of claim 9, further comprising:
and the third injection region is positioned in the substrate which is deep along part of the first surface and is not communicated with the first injection region, and the doping type of the third injection region is the same as that of the through region.
CN202011243355.5A 2020-11-10 2020-11-10 Semiconductor structure and manufacturing method thereof Pending CN112071899A (en)

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Publication number Priority date Publication date Assignee Title
JPS6316669A (en) * 1986-07-08 1988-01-23 Nec Kansai Ltd Planar type scr
US20020008247A1 (en) * 2000-05-05 2002-01-24 Franck Galtie Single-control monolithic component for a composite bridge
US6593600B1 (en) * 1999-08-09 2003-07-15 Stmicroelectronics S.A. Responsive bidirectional static switch
CN110444596A (en) * 2019-07-26 2019-11-12 浙江里阳半导体有限公司 A kind of controlled silicon chip and its manufacturing method
CN111816553A (en) * 2020-05-29 2020-10-23 济宁东方芯电子科技有限公司 Production method of silicon-controlled chip with punch-through structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6316669A (en) * 1986-07-08 1988-01-23 Nec Kansai Ltd Planar type scr
US6593600B1 (en) * 1999-08-09 2003-07-15 Stmicroelectronics S.A. Responsive bidirectional static switch
US20020008247A1 (en) * 2000-05-05 2002-01-24 Franck Galtie Single-control monolithic component for a composite bridge
CN110444596A (en) * 2019-07-26 2019-11-12 浙江里阳半导体有限公司 A kind of controlled silicon chip and its manufacturing method
CN111816553A (en) * 2020-05-29 2020-10-23 济宁东方芯电子科技有限公司 Production method of silicon-controlled chip with punch-through structure

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Application publication date: 20201211