CN111180344A - Three-dimensional stacked structure and preparation method - Google Patents
Three-dimensional stacked structure and preparation method Download PDFInfo
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- CN111180344A CN111180344A CN202010000514.2A CN202010000514A CN111180344A CN 111180344 A CN111180344 A CN 111180344A CN 202010000514 A CN202010000514 A CN 202010000514A CN 111180344 A CN111180344 A CN 111180344A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention provides a three-dimensional stacked structure and a preparation method thereof.A deep N-type well comprising an isolation region is formed in a P-type substrate, and the projection of the isolation region on the first surface of the P-type substrate can cover the first end of a through array connecting line, so that a PN junction and an NP junction can be formed in the P-type substrate above the first end of the through array connecting line, and a large amount of charges generated when a groove of the through substrate connecting line is formed by adopting plasma etching are blocked by the PN junction or the NP junction, thereby avoiding the influence on the reliability of a peripheral circuit.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a three-dimensional stacking structure and a preparation method thereof.
Background
With the rapid development of integrated circuits and the continuous improvement of the demand of people for higher function integration of chips, the three-dimensional structure functional chips enter the lives of people.
The three-dimensional structure functional chip supports more functional modules integrated in a smaller space, and therefore cost and energy consumption are effectively reduced. The novel three-dimensional structure functional chip mainly comprises a functional Array and a peripheral circuit, the functional Array and the peripheral circuit are electrically connected in a wafer bonding mode, and then the circuit bonded with the wafer is led out by preparing Through substrate connecting lines (TSC and Through silicon Contact) and Through Array connecting lines (TAC) so as to form the three-dimensional structure functional chip. However, when the trench of the TSC is formed by plasma etching during the process of manufacturing the TSC, a large amount of charges generated by the plasma etching may be transmitted to the peripheral circuit through the substrate bond wires and the array bond wires, and thus may be accumulated in the peripheral circuit, thereby affecting the reliability of the peripheral circuit, such as reduced time dependent breakdown (TDDB) performance and Negative Bias Temperature Instability (NBTI).
Therefore, it is necessary to provide a three-dimensional stacked structure and a manufacturing method thereof to solve the influence on the peripheral circuit when manufacturing the TSC.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a three-dimensional stacked structure and a method for manufacturing the same, which are used to solve the problem of the prior art that the reliability of the peripheral circuit is affected due to charge transfer when the TSC is manufactured.
To achieve the above and other related objects, the present invention provides a method for preparing a three-dimensional stacked structure, comprising the steps of:
providing a P-type substrate, wherein the P-type substrate comprises a first surface and a second surface corresponding to the first surface;
forming a deep N-type well in the P-type substrate, wherein the deep N-type well comprises an isolation region;
forming a functional array layer on the first surface of the P-type substrate to form a first wafer, wherein the functional array layer comprises through array bonding wires, first ends of the through array bonding wires are in contact with the first surface of the P-type substrate, and projections of the isolation regions on the first surface of the P-type substrate cover the first ends of the through array bonding wires;
providing a second wafer, wherein the second wafer comprises a peripheral circuit layer which is arranged corresponding to the functional array layer;
bonding the first wafer and the second wafer to form a bonded wafer, so that the functional array layer is electrically connected with the peripheral circuit layer, and the peripheral circuit layer is electrically connected with the second end of the through array connecting line;
performing plasma etching on the second surface of the P-type substrate to form a groove penetrating through the P-type substrate and the isolation region, wherein the first end of the penetrating array connecting line is exposed from the bottom of the groove;
and forming a through substrate bonding wire in the groove, wherein the through substrate bonding wire is electrically connected with the first end of the through array bonding wire so as to lead out the circuit of the bonded wafer through the through substrate bonding wire and the through array bonding wire.
Optionally, the method comprises forming a P-type well and an N-type well in the P-type substrate.
Optionally, a step of forming a backside deep trench insulator in the P-type substrate is included.
Optionally, the method includes a step of forming a CMOS transistor layer and a CMOS interconnection layer on the CMOS transistor layer in the peripheral circuit layer, and a step of forming an array interconnection layer including an array core layer and an array interconnection layer on the array core layer in the functional array layer, where the CMOS interconnection layer is electrically connected to the array interconnection layer.
Optionally, the functional array layer is formed to include a stepped gate stack structure and a channel pillar penetrating through the gate stack structure.
The present invention also provides a three-dimensional stacked structure, comprising:
a first wafer, wherein the first wafer comprises a P-type substrate and a functional array layer, the P-type substrate comprises a first surface and a second surface corresponding to the first surface, the P-type substrate comprises a deep N-type well, the deep N-type well comprises an isolation region, the P-type substrate comprises a through substrate tie line, the through substrate tie line penetrates through the P-type substrate and the isolation region, the functional array layer is located on the first surface of the P-type substrate, the functional array layer comprises a through array tie line, a projection of the isolation region on the first surface of the P-type substrate covers a first end of the through array tie line, and the first end of the through array tie line is electrically connected with the through substrate tie line;
and the second wafer comprises a peripheral circuit layer which is arranged corresponding to the functional array layer, the peripheral circuit layer is electrically connected with the second end of the through array connecting line to form a bonded wafer, and the circuit of the bonded wafer is led out through the through substrate connecting line and the through array connecting line.
Optionally, the P-type substrate further includes a P-type well and an N-type well.
Optionally, the P-type substrate further comprises a backside deep trench insulator.
Optionally, the peripheral circuit layer includes a CMOS transistor layer and a CMOS interconnection layer located on the CMOS transistor layer, the functional array layer includes an array core layer and an array interconnection layer located on the array core layer, and the CMOS interconnection layer is electrically connected to the array interconnection layer.
Optionally, the functional array layer includes a stepped gate stack structure and a channel pillar penetrating the gate stack structure.
As described above, according to the three-dimensional stacked structure and the manufacturing method of the present invention, the deep N-well including the isolation region is formed in the P-type substrate, and the projection of the isolation region on the first surface of the P-type substrate can cover the first end of the through array connecting line, so that the PN junction and the NP junction can be formed in the P-type substrate above the first end of the through array connecting line, so that a large amount of charges generated when the trench of the through substrate connecting line is formed by plasma etching are blocked by the PN junction or the NP junction, and thus cannot be transmitted to the through array connecting line, thereby avoiding the influence on the reliability of the peripheral circuit.
Drawings
FIG. 1 is a flow chart illustrating a process for fabricating a three-dimensional stacked structure according to one embodiment.
Fig. 2 is a schematic structural diagram illustrating the formation of an insulating layer according to the first embodiment.
Fig. 3 is a schematic structural diagram illustrating a patterned insulating layer according to an embodiment.
Fig. 4 is a schematic structural diagram illustrating a three-dimensional stacked structure according to an embodiment.
Fig. 5 is a flow chart illustrating a process for fabricating a three-dimensional stacked structure according to a second embodiment.
Fig. 6 is a schematic diagram illustrating a structure of forming a deep N-well according to a second embodiment.
Fig. 7 is a schematic structural diagram illustrating the formation of a three-dimensional stacked structure according to a second embodiment.
Description of the element reference numerals
100 first wafer
110 substrate
110a first side of the substrate
110b second side of the substrate
111 doped well
1111 deep N-type well
1112 high Voltage P-well
1113 high-voltage N-well
1114N type well
1115P type trap
112 backside deep trench insulator
113 through substrate tie line
120 insulating layer
130 functional array layer
131 run-through array tie line
200 second wafer
10 first wafer
11P type substrate
First side of 11a P type substrate
Second side of 11b P type substrate
101 doped well
1011 deep N-well
1012 high voltage P-well
1013 high voltage N-well
1014N type trap
1015P type trap
102 backside deep trench insulator
103 through substrate tie line
12 functional array layer
121 through array bond wires
20 second wafer
A isolation region
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 4, in the present embodiment, by forming an insulating layer in contact with and covering a first end of a through array link line, a large amount of charges generated when a trench penetrating a substrate link line is formed by plasma etching are blocked by the insulating layer and thus cannot be transmitted to the through array link line, thereby preventing the reliability of a peripheral circuit from being affected.
As shown in fig. 1, the present embodiment provides a method for preparing a three-dimensional stacked structure, specifically:
as shown in fig. 2, first, a substrate 110 is provided, wherein the substrate 110 includes a first surface 110a and a second surface 110b corresponding to the first surface 110 a.
Next, an insulating layer 120 is formed on the first surface 110a of the substrate 110, and the insulating layer 120 is patterned, as shown in fig. 3.
As an example, the material of the insulating layer 120 includes one of silicon nitride, silicon oxide, and silicon oxynitride.
Specifically, the insulating layer 120 may be formed by CVD, PVD, or the like, but is not limited thereto, and after patterning the insulating layer 120, the insulating layer 120 may be formed to cover the first ends of the subsequently formed through-array bond wires 131 to block charge transfer.
As an example, the substrate 110 includes a doping well 111, and the step of forming the insulating layer 120 is before the doping well 111 is formed or the step of forming the insulating layer 120 is after the doping well 111 is formed.
Specifically, as shown in fig. 4, in this embodiment, the substrate 110 includes the doped well 111, and the method of forming the doped well 111 may employ ion implantation. Wherein the doped well 111 comprises a deep N-well 1111(DNW), a high voltage P-well 1112(HVPW), a high voltage N-well 1113(HNW), and an N-well 1114 (N)+) And a P-type well 1115 (P)+). Further, the substrate 110 also includes a backside deep trench insulator 112 (BDTI). In forming the insulating layer 120, the substrate 110 may be formed after the doped well 111 and the backside deep trench insulator 112 are formed, but is not limited thereto, and the doped well 111 and the backside deep trench insulator 112 may also be formed after the patterned insulating layer 120 is formed, which may be selected according to the need of the manufacturing process.
Next, a functional array layer 130 is formed on the first surface 110a of the substrate 110 to form the first wafer 100, wherein the functional array layer 130 includes a through array tie line 131(TAS), a first end of the through array tie line 131 is in contact with the insulating layer 120, and the insulating layer 120 covers the first end of the through array tie line 131 to block the transmission of subsequent charges.
Specifically, the functional array layer 130 includes an array core layer and an array interconnection layer (not shown) disposed on the array core layer, such as a three-dimensional memory array, wherein the array interconnection layer is electrically connected to the second end of the through array bonding wire 131 to electrically connect the functional array layer 130 to an external circuit. In this embodiment, only a partial structure of the array core layer is illustrated, such as a stepped gate stack structure, a trench pillar penetrating through the gate stack structure, and the through array tie line 131, but the structure of the functional array layer 130 is not limited thereto, and a conventional process may be used for forming the functional array layer 130, which is not limited herein.
Next, a second wafer 200 is provided, wherein the second wafer 200 includes a peripheral circuit layer (not shown) disposed corresponding to the functional array layer 130.
Specifically, the peripheral circuit layer may include a CMOS transistor layer and a CMOS interconnection layer located on the CMOS transistor layer, and the CMOS interconnection layer may be electrically connected to the array interconnection layer to lead out the circuits of the first wafer 100 and the second wafer 200, and the process for forming the peripheral circuit layer may adopt a conventional process, which is not limited herein.
The first wafer 100 and the second wafer 200 are then bonded to form a bonded wafer, such that the functional array layer 130 is electrically connected to the peripheral circuit layer, and the peripheral circuit layer is electrically connected to the second end of the through array bond wire 131.
After the bonding wafer is formed, plasma etching is performed from the second surface 110b of the substrate 110 to form a trench penetrating through the substrate 110, the bottom of the trench exposes the insulating layer 120, the insulating layer 120 can be used as an etching stop layer, and then, an etching process is continued to remove the insulating layer 120 to expose the first end of the through array tie line 131.
Then, a through-substrate bond wire 113 is formed in the trench, and the through-substrate bond wire 113 is electrically connected to the first end of the through-array bond wire 131, so as to lead out the circuits of the bonded wafer through the through-substrate bond wire 113 and the through-array bond wire 131.
For example, after the first wafer 100 and the second wafer 200 are bonded, before the groove is formed in the substrate 110, a step of thinning the substrate 110 from the second surface 110b of the substrate 110 is further included, so as to reduce an aspect ratio of the groove and reduce process difficulty. Wherein the deep N-well 1111 can be used as a thinning stop layer, the method for thinning the substrate 110 can include, but is not limited to, chemical mechanical polishing.
Referring to fig. 4, the present embodiment provides a three-dimensional stacked structure, which can be prepared by the above method, but is not limited thereto, and the three-dimensional stacked structure includes:
a first wafer 100, the first wafer 100 including a substrate 110, an insulating layer 120 and a functional array layer 130, wherein the substrate 110 includes a first side 110a and a second side 110b corresponding to the first side 110a, the insulating layer 120 is on the first side 110a of the substrate 110, the substrate 110 includes through-substrate tie lines 113, the through-substrate tie lines 113 extend through the substrate 110 and the insulating layer 120, the functional array layer 130 is on the first side 110a of the substrate 110, the functional array layer 130 includes through-array tie lines 131, and first ends 110a of the through-array tie lines 131 are electrically connected to the through-substrate tie lines 113;
a second wafer 200, wherein the second wafer 200 includes a peripheral circuit layer (not shown) disposed corresponding to the functional array layer 130, the peripheral circuit layer is electrically connected to the functional array layer 130, and the peripheral circuit layer is electrically connected to the second end of the through array bonding wire 131 to form a bonded wafer, and the circuits of the bonded wafer are led out through the through substrate bonding wire 113 and the through array bonding wire 131.
As an example, the insulating layer 120 includes one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
As an example, the substrate 110 includes a doped well 111 and a backside deepTrench insulator 112 (BDTI). Wherein the doped well 111 comprises a deep N-well 1111(DNW), a high voltage P-well 1112(HVPW), a high voltage N-well 1113(HNW), and an N-well 1114 (N)+) And a P-type well 1115 (P)+)。
As an example, the deep N-well 1111 is exposed from the second surface 110b of the substrate 110, and the deep N-well 1111 may be used as a thinning stop layer of the substrate 110, so as to reduce the aspect ratio of the trench and reduce the process difficulty by thinning the substrate 110.
As an example, the peripheral circuit layer includes a CMOS transistor layer and a CMOS interconnection layer on the CMOS transistor layer, the functional array layer 130 includes an array core layer and an array interconnection layer on the array core layer, and the CMOS interconnection layer is electrically connected to the array interconnection layer, such as a three-dimensional memory array.
Specifically, the array interconnection layer is electrically connected to the second end of the through array bonding wire 131, so as to lead out the functional array layer 130. In this embodiment, only partial structures of the array core layer, such as a stepped gate stack structure, a channel pillar penetrating the gate stack structure, and the through array tie line 131, are illustrated, but the structure of the functional array layer 130 is not limited thereto. The peripheral circuit layer may be electrically connected to the array interconnection layer through the CMOS interconnection layer, so as to lead out the circuits of the first wafer 100 and the second wafer 200.
Example two
Referring to fig. 5 to 7, in the present embodiment, a deep N-well including an isolation region is formed in a P-type substrate, and a projection of the isolation region on a first surface of the P-type substrate may cover a first end of a through array link line, so that a PN junction and an NP junction may be formed in the P-type substrate above the first end of the through array link line, so that a large amount of charges generated when a trench penetrating the substrate link line is formed by plasma etching are blocked by the PN junction or the NP junction, and thus cannot be transferred to the through array link line, thereby avoiding an influence on reliability of a peripheral circuit.
As shown in fig. 5, the present embodiment provides a method for preparing a three-dimensional stacked structure, specifically:
referring to fig. 6, first, a P-type substrate 11 is provided, where the P-type substrate 11 includes a first surface 11a and a second surface 11b corresponding to the first surface 11 a.
Next, a deep N-well 1011 is formed in the P-type substrate 11, wherein the deep N-well 1011 includes an isolation region A.
Specifically, as shown in fig. 7, the deep N-well 1011 is located in the P-type substrate 11, that is, the deep N-well 1011 includes the isolation region a whose upper and lower surfaces are in contact with the P-type substrate 11, so that the isolation region a and the P-type substrate 11 extend from the second surface 11b of the P-type substrate 11 to the first surface 11a of the P-type substrate 11, and a PN junction and an NP junction are formed, so that when a trench penetrating through the substrate connecting line 103 is formed by subsequent plasma etching, a large amount of charges generated when blocked by the PN junction or the NP junction cannot be transferred to the penetrating array connecting line 121(TAS), thereby avoiding the influence on the reliability of the peripheral circuit.
Illustratively, the P-type substrate 11 further includes a P-type well 1015 (P)+) N type well 1014 (N)+) High voltage P-well 1012(HVPW) and high voltage N-well 1013 (HNW); further, the P-type substrate 11 further includes a backside deep trench insulator 102 (BDTI).
Next, a functional array layer 12 is formed on the first surface 11a of the P-type substrate 11 to form a first wafer 10, wherein the functional array layer 12 includes the through array tie lines 121, a first end of the through array tie lines 121 is in contact with the first surface 11a of the P-type substrate 11, and a projection of the isolation region a on the first surface 11a of the P-type substrate 11 covers the first end of the through array tie lines 121 to block a subsequent charge transmission.
Specifically, the functional array layer 12 includes an array core layer and an array interconnection layer (not shown) on the array core layer, such as a three-dimensional memory array, wherein the array interconnection layer is electrically connected to the second end of the through array tie line 121 to electrically connect the functional array layer 12. In this embodiment, only a partial structure of the array core layer is illustrated, such as a stepped gate stack structure, a trench pillar penetrating through the gate stack structure, and the through array tie line 121, but the structure of the functional array layer 12 is not limited thereto, and a conventional process may be used for forming the functional array layer 12, which is not limited herein.
Next, a second wafer 20 is provided, the second wafer 20 including a peripheral circuit layer (not shown) disposed corresponding to the functional array layer 12.
Specifically, the peripheral circuit layer may include a CMOS transistor layer and a CMOS interconnection layer located on the CMOS transistor layer, and the CMOS interconnection layer may be electrically connected to the array interconnection layer to lead out the circuits of the first wafer 10 and the second wafer 20, and the process for forming the peripheral circuit layer may adopt a conventional process, which is not limited herein.
Then, the first wafer 10 and the second wafer 20 are bonded to form a bonded wafer, such that the functional array layer 12 is electrically connected to the peripheral circuit layer, and the peripheral circuit layer is electrically connected to the second end of the through array bonding wire 121.
After the bonding wafer is formed, plasma etching is performed from the second surface 11b of the P-type substrate 11 to form a trench penetrating through the P-type substrate 11 and the isolation region a, and the first end of the penetrating array tie line 121 is exposed at the bottom of the trench.
Next, the through-substrate bond wires 103 are formed in the trenches, and the through-substrate bond wires 103 are electrically connected to the first ends of the through-array bond wires 121, so that the circuits of the bonded wafer are routed through the through-substrate bond wires 103 and the through-array bond wires 121. The through-substrate bond wires 103 may include a conductive layer and a barrier layer disposed at the periphery of the conductive layer.
Referring to fig. 7, the present embodiment provides a three-dimensional stacked structure, which can be prepared by the above method, but is not limited thereto, and the three-dimensional stacked structure includes:
a first wafer 10, the first wafer 10 including a P-type substrate 11 and a functional array layer 12, wherein the P-type substrate 11 includes a first side 11a and a second side 11b corresponding to the first side 11a, the P-type substrate 11 includes a deep N-well 1011, the deep N-well 1011 includes an isolation region a, the P-type substrate 11 includes a through-substrate tie line 103, the through-substrate tie line 103 penetrates through the P-type substrate 11 and the isolation region a, the functional array layer 12 is located on the first side 11a of the P-type substrate 11, the functional array layer 12 includes a through-array tie line 121, a projection of the isolation region a on the first side 11a of the P-type substrate 11 covers a first end of the through-array tie line 121, and a first end of the through-array tie line 121 is electrically connected to the through-substrate tie line 103;
and a second wafer 20, wherein the second wafer 20 includes a peripheral circuit layer disposed corresponding to the functional array layer 12, the peripheral circuit layer is electrically connected to the functional array layer 12, and the peripheral circuit layer is electrically connected to the second end of the through array bonding wire 121 to form a bonded wafer, and a circuit of the bonded wafer is led out through the through substrate bonding wire 103 and the through array bonding wire 121.
Illustratively, the P-type substrate 11 further includes a P-type well 1015 (P)+) N type well 1014 (N)+) High voltage P-well 1012(HVPW) and high voltage N-well 1013 (HNW); further, the P-type substrate 11 further includes a backside deep trench insulator 102 (BDTI).
As an example, the peripheral circuit layer includes a CMOS transistor layer and a CMOS interconnection layer on the CMOS transistor layer, the functional array layer 12 includes an array core layer and an array interconnection layer on the array core layer, and the CMOS interconnection layer is electrically connected to the array interconnection layer, such as a three-dimensional memory array.
By way of example, the functional array layer 12 includes a stepped gate stack structure and a channel pillar extending through the gate stack structure.
Specifically, the array interconnection layer is electrically connected to the second end of the through array bonding wire 121, so as to lead out the functional array layer 12. In this embodiment, only a partial structure of the array core layer is illustrated, such as the stepped gate stack structure, the channel pillars penetrating the gate stack structure, and the through array tie lines 121, but the structure of the functional array layer 12 is not limited thereto. The peripheral circuit layer may be electrically connected to the array interconnection layer through the CMOS interconnection layer, so as to lead out the circuits of the first wafer 10 and the second wafer 20.
In summary, according to the three-dimensional stacked structure and the fabrication method of the present invention, the deep N-well including the isolation region is formed in the P-type substrate, and the projection of the isolation region on the first surface of the P-type substrate can cover the first end of the through array connecting line, so that a PN junction and an NP junction can be formed in the P-type substrate above the first end of the through array connecting line, and a large amount of charges generated when the trench penetrating the substrate connecting line is formed by plasma etching are blocked by the PN junction or the NP junction, and thus cannot be transmitted to the through array connecting line, thereby avoiding the influence on the reliability of the peripheral circuit. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for preparing a three-dimensional stacked structure is characterized by comprising the following steps:
providing a P-type substrate, wherein the P-type substrate comprises a first surface and a second surface corresponding to the first surface;
forming a deep N-type well in the P-type substrate, wherein the deep N-type well comprises an isolation region;
forming a functional array layer on the first surface of the P-type substrate to form a first wafer, wherein the functional array layer comprises through array bonding wires, first ends of the through array bonding wires are in contact with the first surface of the P-type substrate, and projections of the isolation regions on the first surface of the P-type substrate cover the first ends of the through array bonding wires;
providing a second wafer, wherein the second wafer comprises a peripheral circuit layer which is arranged corresponding to the functional array layer;
bonding the first wafer and the second wafer to form a bonded wafer, so that the functional array layer is electrically connected with the peripheral circuit layer, and the peripheral circuit layer is electrically connected with the second end of the through array connecting line;
performing plasma etching on the second surface of the P-type substrate to form a groove penetrating through the P-type substrate and the isolation region, wherein the first end of the penetrating array connecting line is exposed from the bottom of the groove;
and forming a through substrate bonding wire in the groove, wherein the through substrate bonding wire is electrically connected with the first end of the through array bonding wire so as to lead out the circuit of the bonded wafer through the through substrate bonding wire and the through array bonding wire.
2. The method for producing a three-dimensional stacked structure according to claim 1, wherein: includes the step of forming a P-type well and an N-type well in the P-type substrate.
3. The method for producing a three-dimensional stacked structure according to claim 1, wherein: including the step of forming a backside deep trench insulator in the P-type substrate.
4. The method for producing a three-dimensional stacked structure according to claim 1, wherein: the method comprises the steps of forming a CMOS transistor layer and a CMOS interconnection layer on the CMOS transistor layer in the peripheral circuit layer, and forming an array core layer and an array interconnection layer on the array core layer in the functional array layer, wherein the CMOS interconnection layer is electrically connected with the array interconnection layer.
5. The method for producing a three-dimensional stacked structure according to claim 1, wherein: the formed functional array layer comprises a step-shaped gate stack structure and a channel column penetrating through the gate stack structure.
6. A three-dimensional stacked structure, comprising:
a first wafer, wherein the first wafer comprises a P-type substrate and a functional array layer, the P-type substrate comprises a first surface and a second surface corresponding to the first surface, the P-type substrate comprises a deep N-type well, the deep N-type well comprises an isolation region, the P-type substrate comprises a through substrate tie line, the through substrate tie line penetrates through the P-type substrate and the isolation region, the functional array layer is located on the first surface of the P-type substrate, the functional array layer comprises a through array tie line, a projection of the isolation region on the first surface of the P-type substrate covers a first end of the through array tie line, and the first end of the through array tie line is electrically connected with the through substrate tie line;
and the second wafer comprises a peripheral circuit layer which is arranged corresponding to the functional array layer, the peripheral circuit layer is electrically connected with the second end of the through array connecting line to form a bonded wafer, and the circuit of the bonded wafer is led out through the through substrate connecting line and the through array connecting line.
7. The three-dimensional stacked structure of claim 6, wherein: the P-type substrate further comprises a P-type well and an N-type well.
8. The three-dimensional stacked structure of claim 6, wherein: the P-type substrate also includes a backside deep trench insulator.
9. The three-dimensional stacked structure of claim 6, wherein: the peripheral circuit layer comprises a CMOS transistor layer and a CMOS interconnection layer located on the CMOS transistor layer, the functional array layer comprises an array core layer and an array interconnection layer located on the array core layer, and the CMOS interconnection layer is electrically connected with the array interconnection layer.
10. The three-dimensional stacked structure of claim 6, wherein: the functional array layer comprises a step-shaped gate stack structure and a channel column penetrating through the gate stack structure.
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Cited By (2)
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