CN109473435A - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
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- CN109473435A CN109473435A CN201811392815.3A CN201811392815A CN109473435A CN 109473435 A CN109473435 A CN 109473435A CN 201811392815 A CN201811392815 A CN 201811392815A CN 109473435 A CN109473435 A CN 109473435A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The present invention provides a kind of semiconductor devices, in the semiconductor substrate where memory device, semiconductor substrate can be by being thinned, in this way, the dead ring of Through-substrate can be made with techniques such as fillings by etching, the substrate of substrate therein and surrounding is kept apart, and diffusion layer is formed in the substrate in dead ring, to, the electric resistance structure that resistance value is adjusted by diffusion layer is formd in dead ring, the electric resistance structure is drawn its diffusion layer by two deriving structures, and the connection and use to the electric resistance structure can be thus achieved by deriving structure.The electric resistance structure can be formed in the substrate after being thinned where memory device, dead ring can be made in the substrate in these regions and form independent electric resistance structure, the electric resistance structure adjusts resistance value by diffusion layer, and then electric resistance structure is drawn by the deriving structure of diffusion layer, the effective area of substrate, improves the integrated level of chip where reducing peripheral circuit.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
With the continuous development of semiconductor technology, the integrated level of integrated circuit is constantly improved.In the chip of integrated circuit
In design, it will usually while it being integrated with active device and passive device, passive device such as resistance, capacitor etc. can also occupy chip
Area, especially 3D nand memory chip design in, peripheral circuit by HVMOS, (partly lead by high pressure metal oxide
Body, High Voltage Metal Oxide Semiconductor) device and LVMOS (low pressure metal oxide semiconductor,
Low Voltage Metal Oxide Semiconductor) device composition analog circuit, will use in peripheral circuit a large amount of
Resistance, these resistance can occupy a large amount of chip area, be unfavorable for improving the integrated level of chip.
Summary of the invention
In view of this, resistance is integrated in the purpose of the present invention is to provide a kind of semiconductor devices and its manufacturing method
Substrate where memory device, the area of substrate where reducing peripheral circuit.
To achieve the above object, the present invention has following technical solution:
A kind of semiconductor devices, comprising:
First semiconductor substrate, second surface of first semiconductor substrate with first surface and corresponding thereto, institute
Stating semiconductor substrate includes first area and second area, is formed with memory device on the first surface of the first area；
The dead ring of the semiconductor substrate is penetrated through in the second area；
Diffusion layer in the dead ring in the first surface substrate；
Coating on the first surface of the second area；
The first deriving structure and the second deriving structure of diffusion layer described in the coating.
Optionally, the memory device includes grid layer and the alternately stacked stack layer of insulating layer, passes through the stack layer
Memory cell string and memory cell string on dielectric layer in storage unit interconnection architecture；
The coating includes the first coating and the second coating, and first coating and the stack layer are substantially etc.
Height, second coating are the dielectric layer；
First deriving structure includes the first contact and institute on the diffusion layer of first coating
State the first interconnection architecture in the second coating, in first contact；
Second deriving structure includes the second contact and institute on the diffusion layer of first coating
State the second interconnection architecture in the second coating, in second contact.
Optionally, the memory cell string include on the channel hole of the stack layer and channel hole side wall according to
Tunnel layer, charge storage layer, barrier layer and the channel layer of secondary formation.
Optionally, further include passivation layer on the second surface.
Optionally, the dead ring is round or polygon.
Optionally, the thickness of the semiconductor substrate is less than 10um.
Optionally, further include the second semiconductor substrate, be formed with MOS device and MOS in second semiconductor substrate
The interconnection architecture of device；
The first surface of first semiconductor substrate towards second semiconductor substrate MOS device mutual connection
Structure, and first semiconductor substrate is fixed with second semiconductor substrate；
First deriving structure and the second deriving structure are electrically connected with the interconnection architecture of the MOS device respectively.
Optionally, the MOS device includes low pressure MOS device and high-pressure MOS component.
A kind of manufacturing method of semiconductor devices, comprising:
First semiconductor substrate, second table of first semiconductor substrate with first surface and corresponding thereto are provided
Face, the semiconductor substrate include first area and second area, are formed with memory on the first surface of the first area
Part；It is formed with diffusion layer in the substrate of the first surface of the second area, is formed on the first surface of the second area
Coating is formed with the first deriving structure and the second deriving structure of the diffusion layer in the coating；
Being thinned for first semiconductor substrate is carried out from the second surface；
Form the dead ring for penetrating through the semiconductor substrate, the insulation in the second region from the second surface
The interior zone of ring covers the diffusion layer region that first deriving structure and the second deriving structure are connected.
Optionally, after forming the dead ring, further includes:
Passivation layer is formed on the second surface.
Optionally, the memory device includes grid layer and the alternately stacked stack layer of insulating layer, passes through the stack layer
Memory cell string and memory cell string on dielectric layer in storage unit interconnection architecture；
The coating includes the first coating and the second coating, and first coating and the stack layer are substantially etc.
Height, second coating are the dielectric layer；
First deriving structure includes the first contact and institute on the diffusion layer of first coating
State the first interconnection architecture in the second coating, in first contact；
Second deriving structure includes the second contact and institute on the diffusion layer of first coating
State the second interconnection architecture in the second coating, in second contact.
Optionally, the memory cell string include on the channel hole of the stack layer and channel hole side wall according to
Tunnel layer, charge storage layer, barrier layer and the channel layer of secondary formation.
Optionally, the dead ring is round or polygon.
Optionally, from the second surface carry out first semiconductor substrate be thinned before, further includes:
Second semiconductor substrate is provided, the interconnection of MOS device and MOS device is formed in second semiconductor substrate
Structure；
By the first surface of first semiconductor substrate towards second semiconductor substrate MOS device mutual connection
Structure, and first semiconductor substrate and second semiconductor substrate are fixed, first deriving structure and second is drawn
Structure is electrically connected with the interconnection architecture of the MOS device respectively.
Optionally, the MOS device includes low pressure MOS device and high-pressure MOS component.
Optionally, the dead ring for penetrating through the semiconductor substrate is formed in the second region from the second surface,
Include:
The pattern of dead ring is transferred in mask layer by photoetching process；
Under the masking of the mask layer, the etching of the first semiconductor substrate is carried out from second surface, until described in perforation
First semiconductor substrate；
The filling of insulating materials is carried out, to form dead ring.
Semiconductor devices provided in an embodiment of the present invention and its manufacturing method, where memory device after reduction process
Semiconductor substrate in, dead ring is formed by etching and fill process, dead ring by substrate therein and the substrate of surrounding every
It leaves, and is formed with diffusion layer in the substrate in dead ring, thus, the electricity that resistance value is adjusted by diffusion layer is formd in dead ring
Structure is hindered, which is drawn its diffusion layer by two deriving structures, be can be thus achieved by deriving structure to the electricity
Hinder the connection and use of structure.The electric resistance structure is formed in the substrate where memory device, the substrate will with include periphery
Another substrate of circuit is packaged together, and can have the white space of some non-device around memory device region, can
To form electric resistance structure in the substrate in these regions, which adjusts resistance value by diffusion layer, and then passes through diffusion layer
Deriving structure draws electric resistance structure, in order to the connection and use of the device of peripheral circuit, in this way, where reducing peripheral circuit
The effective area of substrate improves the integrated level of chip.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the structural schematic diagram of semiconductor devices according to embodiments of the present invention；
Fig. 2 shows the structural schematic diagrams of semiconductor devices according to another embodiment of the present invention；
Fig. 3 shows dead ring in semiconductor devices according to an embodiment of the present invention and illustrates from the plan structure of first surface
Figure；
Fig. 4-8 shows the device profile knot during manufacturing method formation semiconductor devices according to an embodiment of the present invention
Structure schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, in the chip of integrated circuit, it is for example electric also to will use a large amount of passive devices
Resistance etc., these devices can also occupy the area of chip, and in the application of memory device, as what is required integrated level constantly mentions
Height reduces the carrying cost of every bit in order to further improve memory capacity, proposes the memory device of stereochemical structure.?
In one application of the memory device of stereochemical structure, 3D nand memory part can be the MOS (metal oxide of peripheral circuit
Semiconductor, Metal Oxide Semiconductor) device formed on different substrates, can then pass through encapsulation technology
The two is linked together, the analog circuit which is made of HVMOS device and LVMOS device, meeting in peripheral circuit
Using a large amount of resistance, these resistance can occupy a large amount of chip area, cause the chip area of peripheral circuit to be difficult to decrease, no
Conducive to the integrated level for improving chip.
Based on this, present applicant proposes a kind of semiconductor devices, refering to what is shown in Fig. 1, including:
First semiconductor substrate 100, first semiconductor substrate 100 have first surface 101 and corresponding thereto the
Two surfaces 102, the semiconductor substrate include first area 1001 and second area 1002, and the first of the first area 1001
Memory device is formed on surface 101；
The dead ring 150 of the semiconductor substrate 100 is penetrated through in the second area 1002；
150 are located at the diffusion layer 104 in 101 substrate 100 of first surface in the dead ring；
Coating 120 on the first surface 101 of the second area 1002；
The first deriving structure 130 and the second deriving structure 140 of diffusion layer 104 described in the coating 120.
In the embodiment of the present application, the MOS device of the peripheral circuit of memory device and memory device is respectively formed at difference
Substrate on, and electric resistance structure is then formed on the substrate where memory device, specifically, dead ring is by the substrate and ring in ring
Outer substrate is kept apart, and is formed with diffusion layer in the substrate in dead ring, passes through diffusion layer in this way, just foring in dead ring
The electric resistance structure of resistance value is adjusted, which is drawn its diffusion layer by two deriving structures, passes through deriving structure
To realize connection and use to the electric resistance structure.The electric resistance structure is formed in the substrate where memory device, in memory
Around part region, especially around 3D nand memory part, there can be the white space of some non-device, utilize these
White space forms electric resistance structure, can't additionally increase the area of chip, while the electric resistance structure is adjusted by diffusion layer and hindered
Value, and then is drawn electric resistance structure by the deriving structure of diffusion layer, in order to the connection and use of the device of peripheral circuit, this
Sample, the effective area of substrate, improves the integrated level of chip where reducing peripheral circuit.
In the embodiment of the present application, memory device can be three-dimensional memory device, that is to say, that in addition to substrate level
Two-dimensional directional, is also distributed with multiple storage units on vertical substrates direction, in the embodiment of the present application, the memory device of the solid
It for 3D nand memory part, is formed on the first surface of substrate 100,3D nand memory part is including at least grid layer and absolutely
The alternately stacked stack layer 110 of edge layer, on the memory cell string 112 and memory cell string 112 of the stack layer 110
Storage unit interconnection architecture 114, the interconnection architecture 114 are formed among dielectric layer 124, can for the extraction of memory cell string
To include the contact, via hole, liner etc. of one or more layers metal layer and connection metal layer.
In 3D nand memory part, stack layer 110 is formed by grid layer and insulating layer are alternately laminated, each layer of grid
Pole layer constitutes a storage unit with memory cell string 112, so that it is single also to form multiple storages on the direction perpendicular to substrate
Member.Wherein, the end of stack layer 110 can be hierarchic structure (not shown go out) so that each layer of grid layer exist it is not upper
The part of layer grid layer covering, so as to be used to form the contact of this layer of grid layer, so as to draw each layer of grid layer
Out.The formation of memory cell string 120 can be formed in the channel hole of stack layer 110, along channel hole side wall into channel hole
The heart, memory cell string 112 successively include store function layer and channel layer, and store function layer plays the role of charge storage, usually
Including tunnel layer, charge storage layer and barrier layer, store function layer may be substantially of L-type, and channel layer is formed in store function
On the side wall of layer and the bottom in channel hole, the filled layer of insulating materials can also be formed between channel layer.It is understood that
Being can also include other necessity portion on the first surface 101 of the semiconductor substrate 100 in specific application
Part, for example, the top of memory cell string 114 conductive pad, in gating tube device of the lower section of memory cell string etc..
In the embodiment of the present application, with reference to shown in Fig. 1 and Fig. 3, dead ring 150 is formed in substrate 100, the substrate 100
It can be the substrate after being thinned, thickness will usually be less than 10um hereinafter, can be by traditional semiconductor technology, example
Such as photoetching, etching and filling technique, to form the dead ring 150 of perforation.
For dead ring 150 by being formed for material that substrate can be isolated into different piece, the material of dead ring 150 for example can be with
For one of dielectric materials such as silica, silicon nitride or silicon oxynitride or a variety of formed.Dead ring 150 is closed annular
Structure, dead ring play the role of being dielectrically separated from, so that the substrate outside the substrate and ring in ring is kept apart, the lining in dead ring
Bottom is used to form electric resistance structure.It can according to need the shape of dead ring 150, the shape namely resistance of dead ring 150 is arranged
The shape of structure, the shape of dead ring 150 can be for example polygon or round, and polygon may include rectangular or other are polygon
Shape, rectangular includes square and rectangle, refering to what is shown in Fig. 3, the shape of dead ring 150 is rectangular in the specific example.
In the application, diffusion layer 104 is provided in the first surface 101 of substrate in dead ring 150, that is to say, that
150 form silicon diffusion resistor structure in dead ring, which is the doped layer in substrate, and diffusion layer 104 can have
There are p-type doping or n-type doping, the Doped ions of n-type doping can be for example N, P, As, S etc., the doping particle example of p-type doping
It such as can be B, Al, Ga or In.It in specific application, can be by controlling the doping particle of diffusion layer 104, doping concentration
And the technological parameters such as doping depth, and the area in dead ring 150 is combined, to obtain the electric resistance structure of required resistance value.
The electric resistance structure is formed on the substrate 100 where memory device, and the blank area of the non-device in memory device
It is formed on domain, for ease of description, in this application, which is denoted as second area 1002, the first of second area 1002
Coating 120 is formed on surface 101, the first deriving structure 130 and second that diffusion layer 104 is formed in coating 120 draws
Diffusion layer 104 is drawn by the first deriving structure 130 and the second deriving structure 140 in structure 140 out.First deriving structure
130 and second two connecting pins of the deriving structure 140 as resistance, in order to the circuit in other substrates, such as peripheral circuit
Use the electric resistance structure.
In the particular embodiment, coating 120 can have different structures, can be the lamination knot of dielectric material
Structure.First deriving structure 130 and the second deriving structure 140 are electrically drawn for diffusion layer 104, may include contact, one layer or
More metal layers and via hole, the liner etc. for connecting metal layer.In the embodiment that memory device is 3D nand memory part,
The coating 120 include the first coating 122 and the second coating 124, the first coating 122 substantially with 3D nand memory
The stack layer 110 of part is contour, and the second coating 124 is the dielectric layer 124 of 1001 storage unit of first area；First deriving structure
130 include the first contact 132 on the diffusion layer 104 of the first coating 122 and second in coating 124, institute
The first interconnection architecture 134 in the first contact 132 is stated, the second deriving structure 140 includes the expansion through the first coating 122
Dissipate the second interconnection architecture 144 in the second contact 142 and the second coating 124 on layer 104, in second contact 142.
First interconnection architecture 134, the second interconnection architecture 144 may include one layer or repeatedly metal layer and connect metal layer via hole,
Liner etc., can be with the knot having the same of memory device interconnection architecture 114 on the memory cell string 112 of first area 1001
Structure, that is, can be formed simultaneously in same technique.
It can also be further provided with passivation layer 160 on the second surface 102 of substrate 100, which plays guarantor
Shield effect, passivation layer 160 can be one or more layers structure, which for example can be silicon oxide layer.
Above semiconductor devices can be the device on the wafer after the completion of wafer manufacture, be also possible to and other wafers
The device in encapsulating structure after completing encapsulation, in the embodiment of encapsulating structure, refering to what is shown in Fig. 2, still further comprising the
Two semiconductor substrates 200 are formed with the interconnection architecture 220 of MOS device 210 and MOS device in second semiconductor substrate 200；
The first surface 101 of first semiconductor substrate 100 towards the second semiconductor substrate 200 MOS device interconnection architecture 220,
First semiconductor substrate 100 and the second semiconductor substrate 200 are fixed, in specific application, can be two through encapsulation technology
Corresponding interconnection architecture is fixed together on substrate, and the first deriving structure 130 and the second deriving structure 140 respectively with it is described
The interconnection architecture 220 of MOS device is electrically connected.
First semiconductor substrate 100 and the second semiconductor substrate 200 are fixed together by encapsulation technology, by electric resistance structure
It is formed in the substrate where memory device, and passes through the first deriving structure 130 and the second deriving structure 140 and the second semiconductor
The interconnection architecture 220 of MOS device on substrate 200 is electrically connected, in this way, without the face for occupying the second semiconductor substrate 200
Product, utilizes the idle region except the memory device of the first semiconductor substrate 100, it can realizes and is used for the second semiconductor substrate
The layout of electric resistance structure needed for circuit in 200, the effective area of substrate where reducing peripheral circuit improve the integrated of chip
Degree.
According to different design needs, different source and drain operating voltages and device can have in the second semiconductor substrate 200
Part type, in the application of 3D nand memory part, 3D nand memory part needs higher driving voltage, peripheral circuit
In generally include high-pressure MOS component and low pressure MOS device namely HVMOS and LVMOS, type of device can for PMOS and/or
NMOS.Wherein, high-pressure MOS component is for the source and drain operating voltage of standard MOS device, such as in the CMOS of 0.18um
In device technology, the source and drain operating voltage of standard MOS device is 1.8V, and be higher than the operating voltage of the standard MOS device, then
For high-pressure MOS component.In the application of 3D NAND, the source and drain operating voltage of high-pressure MOS component can be higher than 20V, typically
It can be 25V.
In the particular embodiment, MOS device includes at least grid, gate lateral wall in second semiconductor substrate 200
Source-drain area in side wall and grid two sides substrate, the interconnection architecture 220 of MOS device metal layer and company including one layer or repeatedly
Via hole, the liner etc. of metal layer are connect, interconnection architecture 220 can be set on source-drain area and/or grid.
The structure of the semiconductor devices of the embodiment of the present application is described in detail above, in order to better understand originally
The technical solution and technical effect of application, are described in detail specific embodiment below with reference to flow chart and attached drawing.
Refering to what is shown in Fig. 4, providing the first semiconductor substrate 100 in step S01, first semiconductor substrate 100 has
First surface 101 and second surface 102 corresponding thereto, the semiconductor substrate 100 include first area 1001 and the secondth area
Domain 1002 is formed with memory device on the first surface 101 of the first area 1001；First table of the second area 1002
It is formed with diffusion layer 104 in the substrate 100 in face 101, is formed with coating on the first surface 102 of the second area 1002
120, the first deriving structure 130 and the second deriving structure 140 of the diffusion layer 104, reference are formed in the coating 120
Shown in Fig. 5.
In the application preferred embodiment, semiconductor substrate 100 can be for Si substrate, Ge substrate, SiGe substrate, SOI (absolutely
Silicon on edge body, Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator) etc..At it
In his embodiment, semiconductor substrate can also be include the substrate of other elements semiconductor or compound semiconductor, such as GaAs,
InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be with other epitaxial structures, such as SGOI (insulator
Upper germanium silicon) etc..In the present embodiment, which can be silicon substrate.
In the embodiment of the present application, be already formed on first substrate 100 above-mentioned memory device, diffusion layer and
First and second deriving structures, the application are not particularly limited to the method for forming these devices and structure, for the ease of reason
Solution, will be described the method for these devices and structure with a specific example below.
It can be after or before forming memory cell string 112 on first area 1001, from the second of second area 1002
Surface 102 forms diffusion layer 104 in substrate 100.Specifically, type needed for being injected by ion implanting to substrate is miscellaneous
Matter then carries out thermal annealing activation doping, so that diffusion layer 104 is formed, with reference to shown in Fig. 5.Specifically, diffusion layer 104 can be with
With p-type doping or n-type doping, the Doped ions of n-type doping can be for example N, P, As, S etc., the doping particle of p-type doping
Such as it can be selected to adulterate particle according to the resistance value of institute's electric resistance structure to be formed and mixed for B, Al, Ga or In etc.
The parameters such as miscellaneous concentration and depth.
In the present embodiment, memory device is three-dimensional nand memory part, in the concrete realization, it is possible, firstly, to the
One region 1001 forms stack layer by alternately laminated sacrificial layer and insulating layer, and sacrificial layer and insulating layer have different quarters
Erosion selectivity, sacrificial layer will be removed and be substituted by grid layer, and sacrificial layer for example can be silicon nitride, and insulation layers such as can be with
For silica, the number of the storage unit of the number of plies of sacrificial layer and insulating layer formation needed for vertical direction is in stack layer Lai really
Fixed, the number of plies of sacrificial layer and insulating layer for example can be 32 layers, 64 layers, 128 layers etc., which determines and store in vertical direction
The number of unit, therefore, the number of plies of stack layer are more, can more improve integrated level.
Then, can be by etching technics, so that the end of stack layer 110 is hierarchic structure, hierarchic structure is for subsequent
The contact on grid layer is formed, the middle section of stack layer is memory block, is used to form memory device.
During forming memory device, firstly, forming channel hole in stack layer, which can be stack layer
In through-hole, lithographic technique can be used, etch stack layer, until exposing 100 first surface 101 of substrate, form channel hole.
It then, can be by selective epitaxial growth (Selective EpitaxialGrowth), first in channel hole bottom growth in situ
Epitaxial structure out, the epitaxial structure are the channel layer for gating tube device.In the substrate under the channel hole, it can be previously formed
Doped region, the active area as gating tube device.Then, memory cell string is formed in channel hole, specifically, present channel hole
Store function layer is formed on side wall, store function layer may include tunnel layer, charge storage layer and barrier layer, specifically can be with
For ONO lamination, ONO (Oxide-Ntride-Oxide) i.e. oxide, nitride and oxide, which can be L
Type exposes the channel layer of gating tube device.Then, depositing trench layer, channel layer can be polysilicon, thus in store function
The channel layer of memory device is formed on the channel layer of layer and gating tube device.Finally, filling channel hole, insulation with insulating materials
Material is, for example, silica.
Later, stack layer 110 can be etched, is formed grid line gap (Gate Line Seam), passes through grid line gap Jiang Dui
Sacrificial layer removal in lamination, meanwhile, the filling of grid material is carried out, grid material for example can be tungsten, sacrifice in original
The region of layer forms grid layer, and fills grid line gap.In this way, foring grid layer and the alternately stacked stack layer of insulating layer
110, the control grid and gating tube device of grid layer in the stack layer as each storage unit of memory cell string 112
Control grid.
Then, above-mentioned device can be covered with dielectric material, in the first surface 101 and stack layer of second area 1002
Hierarchic structure (not shown go out) on all will be covered with the first coating 122, after carrying out flatening process, on second area
The first coating 122 will there is the contour thickness with stack layer substantially.
Later, the etching and filling that the first coating 122 can be carried out, the shape on the diffusion layer 104 of second area 1002
It is connect at grid is formed in the first contact 132 and the second contact 142, and the hierarchic structure of the stack layer in first area 1001
Touching (not shown go out).
Later, continue the second coating 124 of overwrite media material, it can be simultaneously in the first contact of second area 1002
132, depositing for the first interconnection architecture 134, the second interconnection architecture 144 and first area 1001 is respectively formed in the second contact 142
The interconnection architecture 114 of memory device is formed on storage unit string 112, interconnection architecture may include one or more layers metal layer, connect
Connect via hole and the liner etc. of metal layer.
So far, the diffusion layer 104 of memory device and electric resistance structure just is formd in the front of the first semiconductor substrate 100
With the deriving structure of diffusion layer 104.
In step S02, being thinned for first semiconductor substrate 100 is carried out from the second surface 102, with reference to Fig. 6 institute
Show.
When needing for the first semiconductor substrate and another semiconductor substrate to be packaged together, wafer-level packaging can be used
First semiconductor substrate is first packaged by technology with another semiconductor substrate, then, then is carried out from the first semiconductor substrate
100 back side carries out thinned technique.
In the present embodiment, before be thinned, refering to what is shown in Fig. 6, further include: the second semiconductor substrate 200 is provided,
The interconnection architecture 220 of MOS device 210 and MOS device is formed in second semiconductor substrate 200；By the first semiconductor
The first surface 101 of substrate 100 towards the second semiconductor substrate 200 MOS device interconnection architecture 114, and the first half are led
Body substrate 100 and second semiconductor substrate 200 are fixed, the first deriving structure 130 and the second deriving structure 140 respectively with
The interconnection architecture 114 of MOS device is electrically connected.
MOS device is already formed in the second semiconductor substrate 200, MOS device is used to constitute the periphery of memory device
Circuit, according to different design needs, MOS device can have different source and drain operating voltages and type of device, in 3D NAND
In the application of memory device, 3D nand memory part needs higher driving voltage, generally includes high pressure in peripheral circuit
MOS device and low pressure MOS device namely HVMOS and LVMOS, type of device can be PMOS and/or NMOS.
In specific application, MOS device includes gate dielectric layer, grid, gate lateral wall in the second semiconductor substrate 200
Source-drain area in side wall and grid two sides substrate, the interconnection architecture 220 of MOS device metal layer and company including one layer or repeatedly
Via hole, the liner etc. of metal layer are connect, interconnection architecture 220 can be set on source-drain area and/or grid.Wherein, gate dielectric layer 1
It such as can be thermal oxide layer or other suitable dielectric materials, such as silica or high K medium material, high K medium grid material example
Such as hafnium base oxide, HFO2, one of HfSiO, HfSiON, HfTaO, HfTiO etc. or in which several combinations.Grid is for example
Can be polysilicon, amorphous silicon or metal electrode material or their combination, metal electrode material can for TiN, TiAl, Al,
The one or more combinations of TaN, TaC, W.Side wall can have single or multi-layer structure, can be by silicon nitride, silica, nitrogen oxidation
Silicon, silicon carbide, fluoride-doped silica glass, low k dielectric material and combinations thereof and/or other suitable materials are formed.Source and drain
Area has the first doping type, and the first doping type can be N-shaped or p-type.MOS device in second semiconductor substrate 200 can
To be formed using arbitrary method, the application this and be not specially limited.
When the first semiconductor substrate 100 is fixed with second semiconductor substrate 200, encapsulation technology can be used,
Such as the modes such as metal bonding or soldered ball connection, by the first deriving structure 130 and the second deriving structure 140 respectively with MOS device
Interconnection architecture 114 be fixed and be electrically connected.
In this way, just the first semiconductor substrate 100 is electrically connected with the second semiconductor substrate, electric resistance structure is formed
In the substrate where memory device, and pass through the first deriving structure 130 and the second deriving structure 140 and the second semiconductor substrate
The interconnection architecture 220 of MOS device on 200 is electrically connected, in this way, without the area for occupying the second semiconductor substrate 200, benefit
With the idle region except the memory device of the first semiconductor substrate 100, it can realize in the second semiconductor substrate 200
The layout of electric resistance structure needed for circuit, the effective area of substrate, improves the integrated level of chip where reducing peripheral circuit.
Later, refering to what is shown in Fig. 6, the reverse side of the first semiconductor substrate 100 can be carried out it is thinned so that substrate 100 have
There is suitable thickness, convenient for the progress of subsequent technique.Specifically, can be led to the first half by the method for chemical mechanical grinding
The second surface 102 of body substrate 100 carry out it is thinned, until reaching required thickness, normally, be thinned after the first semiconductor
The thickness of substrate 100 is less than 10um.
In step S03, the perforation semiconductor substrate is formed in the second area 1002 from the second surface 102
The interior zone of 100 dead ring 150, the dead ring 150 covers first deriving structure 130 and the second deriving structure
140 104 regions of diffusion layer connected, with reference to shown in Fig. 7.
Since the first semiconductor substrate 100 is by being thinned, thickness is substantially reduced, then can pass through existing semiconductor technology
Come formed perforation semiconductor substrate dead ring, covered specifically, photoetching process can be first passed through and be transferred to the pattern of dead ring
In film layer, then, under the masking of the mask layer, by etching technics, the etching of substrate 100 is first carried out from second surface 102,
Until carving logical substrate 100, the dead ring namely closed annular groove for etching perforation then carry out the filling of insulating materials,
Insulating materials can be for example one of silica, silicon nitride or silicon oxynitride or a variety of, to form dead ring 150.It is logical
The position where control dead ring 150 is crossed, so that interior zone covering the first deriving structure 130 and second of dead ring 150 draws
104 region of diffusion layer that structure 140 is connected out, in this way, just foring electric resistance structure in dead ring 150.
It can according to need the shape of dead ring 150, the shape of dead ring 150 namely the shape of electric resistance structure is arranged,
The shape of dead ring 150 for example can be polygon or round, and polygonal such as can be rectangular or other shapes, rectangular to include
Square and rectangle, refering to what is shown in Fig. 3, the shape of dead ring 150 is rectangular in the specific example.Finally with insulation
The doping situation of diffusion layer 104 determines the resistance value of electric resistance structure in Substrate Area and dead ring 150 in ring 150.
In this way, being just integrated with electric resistance structure in the substrate where memory device, which is formed in the substrate
In dead ring, the electric resistance structure of resistance value is adjusted by diffusion layer, which is drawn its diffusion layer by two deriving structures
Out, two connecting pins of the two deriving structures as resistance, in order to which the circuit in other substrates, such as peripheral circuit use
The electric resistance structure.
Later, refering to what is shown in Fig. 8, passivation layer 160 can also be formed further on second surface 102.It can carry out blunt
Change the deposition of layer, such as silica material, and planarized, to form the passivation layer.
So far, the processing of the semiconductor devices of the embodiment of the present application is just completed.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
Claims (16)
1. a kind of semiconductor devices characterized by comprising
First semiconductor substrate, second surface of first semiconductor substrate with first surface and corresponding thereto, described half
Conductor substrate includes first area and second area, is formed with memory device on the first surface of the first area；
The dead ring of the semiconductor substrate is penetrated through in the second area；
Diffusion layer in the dead ring in the first surface substrate；
Coating on the first surface of the second area；
The first deriving structure and the second deriving structure of diffusion layer described in the coating.
2. semiconductor devices according to claim 1, which is characterized in that the memory device includes grid layer and insulating layer
Alternately stacked stack layer, the storage in the dielectric layer on the memory cell string and memory cell string of the stack layer
Element-interconn ection structure；
The coating includes the first coating and the second coating, and first coating and the stack layer are substantially contour,
Second coating is the dielectric layer；
First deriving structure includes the first contact and described the on the diffusion layer of first coating
The first interconnection architecture in two coatings, in first contact；
Second deriving structure includes the second contact and described the on the diffusion layer of first coating
The second interconnection architecture in two coatings, in second contact.
3. semiconductor devices according to claim 2, the memory cell string includes across the channel hole of the stack layer
And tunnel layer, charge storage layer, barrier layer and the channel layer sequentially formed on the side wall of the channel hole.
4. semiconductor devices according to claim 1, which is characterized in that further include the passivation layer on the second surface.
5. semiconductor devices according to claim 1, which is characterized in that the dead ring is round or polygon.
6. semiconductor devices according to claim 1, which is characterized in that the thickness of the semiconductor substrate is less than 10um.
7. semiconductor devices according to claim 1 to 6, which is characterized in that further include the second semiconductor lining
Bottom is formed with the interconnection architecture of MOS device and MOS device in second semiconductor substrate；
The first surface of first semiconductor substrate towards second semiconductor substrate MOS device interconnection architecture, and
First semiconductor substrate is fixed with second semiconductor substrate；
First deriving structure and the second deriving structure are electrically connected with the interconnection architecture of the MOS device respectively.
8. semiconductor devices according to claim 7, which is characterized in that the MOS device includes low pressure MOS device and height
Press MOS device.
9. a kind of manufacturing method of semiconductor devices characterized by comprising
First semiconductor substrate, second surface of first semiconductor substrate with first surface and corresponding thereto, institute are provided
Stating semiconductor substrate includes first area and second area, is formed with memory device on the first surface of the first area；Institute
It states and is formed with diffusion layer in the substrate of the first surface of second area, covering is formed on the first surface of the second area
Layer, the first deriving structure and the second deriving structure of the diffusion layer are formed in the coating；
Being thinned for first semiconductor substrate is carried out from the second surface；
Form the dead ring for penetrating through the semiconductor substrate in the second region from the second surface, the dead ring
Interior zone covers the diffusion layer region that first deriving structure and the second deriving structure are connected.
10. manufacturing method according to claim 9, which is characterized in that after forming the dead ring, further includes:
Passivation layer is formed on the second surface.
11. manufacturing method according to claim 9, which is characterized in that the memory device includes grid layer and insulating layer
Alternately stacked stack layer, the storage in the dielectric layer on the memory cell string and memory cell string of the stack layer
Element-interconn ection structure；
The coating includes the first coating and the second coating, and first coating and the stack layer are substantially contour,
Second coating is the dielectric layer；
First deriving structure includes the first contact and described the on the diffusion layer of first coating
The first interconnection architecture in two coatings, in first contact；
Second deriving structure includes the second contact and described the on the diffusion layer of first coating
The second interconnection architecture in two coatings, in second contact.
12. manufacturing method according to claim 11, which is characterized in that the memory cell string includes across the stacking
Tunnel layer, charge storage layer, barrier layer and the channel layer sequentially formed on the channel hole of layer and channel hole side wall.
13. manufacturing method according to claim 11, which is characterized in that the dead ring is round or polygon.
14. manufacturing method according to claim 9, which is characterized in that carrying out described the first half from the second surface
Conductor substrate it is thinned before, further includes:
Second semiconductor substrate is provided, the mutual connection of MOS device and MOS device is formed in second semiconductor substrate
Structure；
By the first surface of first semiconductor substrate towards second semiconductor substrate MOS device interconnection architecture,
And first semiconductor substrate and second semiconductor substrate are fixed, first deriving structure and the second deriving structure
It is electrically connected respectively with the interconnection architecture of the MOS device.
15. manufacturing method according to claim 14, which is characterized in that the MOS device includes low pressure MOS device and height
Press MOS device.
16. manufacturing method according to claim 9, which is characterized in that in the second region from the second surface
Form the dead ring for penetrating through the semiconductor substrate, comprising:
The pattern of dead ring is transferred in mask layer by photoetching process；
Under the masking of the mask layer, the etching of the first semiconductor substrate is carried out from second surface, until perforation described first
Semiconductor substrate；
The filling of insulating materials is carried out, to form dead ring.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111128721A (en) * | 2019-12-04 | 2020-05-08 | 长江存储科技有限责任公司 | Memory manufacturing method and memory |
| CN111162002A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Memory manufacturing method and memory |
| CN111180344A (en) * | 2020-01-02 | 2020-05-19 | 长江存储科技有限责任公司 | Three-dimensional stacked structure and preparation method |
| WO2021022402A1 (en) * | 2019-08-02 | 2021-02-11 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
| CN112384978A (en) * | 2020-10-12 | 2021-02-19 | 长江先进存储产业创新中心有限责任公司 | Novel integration scheme for bonding to 3D XPOINT chip by adopting CPU |
| CN112702047A (en) * | 2021-01-04 | 2021-04-23 | 长江存储科技有限责任公司 | Switching device, integrated circuit, and electronic apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826522A (en) * | 2009-03-03 | 2010-09-08 | 三星电子株式会社 | The integrated-circuit resistor spare that comprises a plurality of interconnection resistance layers |
| CN102569205A (en) * | 2010-12-30 | 2012-07-11 | 海力士半导体有限公司 | Non-volatile memory device and method for fabricating the same |
| CN102610495A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Manufacturing method of semiconductor resistor, semiconductor resistor and electronic device |
-
2018
- 2018-11-21 CN CN201811392815.3A patent/CN109473435B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826522A (en) * | 2009-03-03 | 2010-09-08 | 三星电子株式会社 | The integrated-circuit resistor spare that comprises a plurality of interconnection resistance layers |
| CN102569205A (en) * | 2010-12-30 | 2012-07-11 | 海力士半导体有限公司 | Non-volatile memory device and method for fabricating the same |
| CN102610495A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Manufacturing method of semiconductor resistor, semiconductor resistor and electronic device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021022402A1 (en) * | 2019-08-02 | 2021-02-11 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
| US11348936B2 (en) | 2019-08-02 | 2022-05-31 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
| JP2022534613A (en) * | 2019-08-02 | 2022-08-02 | 長江存儲科技有限責任公司 | Three-dimensional memory device and manufacturing method thereof |
| JP7242907B2 (en) | 2019-08-02 | 2023-03-20 | 長江存儲科技有限責任公司 | Three-dimensional memory device and manufacturing method thereof |
| CN111128721A (en) * | 2019-12-04 | 2020-05-08 | 长江存储科技有限责任公司 | Memory manufacturing method and memory |
| CN111162002A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Memory manufacturing method and memory |
| CN111180344A (en) * | 2020-01-02 | 2020-05-19 | 长江存储科技有限责任公司 | Three-dimensional stacked structure and preparation method |
| CN111180344B (en) * | 2020-01-02 | 2021-12-07 | 长江存储科技有限责任公司 | Three-dimensional stacked structure and preparation method |
| CN112384978A (en) * | 2020-10-12 | 2021-02-19 | 长江先进存储产业创新中心有限责任公司 | Novel integration scheme for bonding to 3D XPOINT chip by adopting CPU |
| CN112384978B (en) * | 2020-10-12 | 2023-06-13 | 长江先进存储产业创新中心有限责任公司 | Novel integration scheme for bonding to 3D XPOINT chip by adopting CPU |
| CN112702047A (en) * | 2021-01-04 | 2021-04-23 | 长江存储科技有限责任公司 | Switching device, integrated circuit, and electronic apparatus |
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|---|---|
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