CN109473435B

CN109473435B - Semiconductor device and manufacturing method thereof

Info

Publication number: CN109473435B
Application number: CN201811392815.3A
Authority: CN
Inventors: 刘威; 陈亮; 甘程; 吴昕; 鞠韶复
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-11-21
Filing date: 2018-11-21
Publication date: 2020-09-18
Anticipated expiration: 2038-11-21
Also published as: CN109473435A

Abstract

The invention provides a semiconductor device, in a semiconductor substrate where a memory device is arranged, the semiconductor substrate can be thinned, so that an insulating ring penetrating through the substrate can be manufactured through processes of etching, filling and the like, the substrate in the insulating ring is isolated from the surrounding substrate, a diffusion layer is formed in the substrate in the insulating ring, a resistor structure with the resistance value adjusted by the diffusion layer is formed in the insulating ring, the diffusion layer of the resistor structure is led out through two leading-out structures, and the connection and the use of the resistor structure can be realized through the leading-out structures. The resistor structure can be formed in a thinned substrate where the memory device is located, the insulating rings can be manufactured in the substrate in the areas to form an independent resistor structure, the resistance of the resistor structure is adjusted by the diffusion layer, and then the resistor structure is led out through the leading-out structure of the diffusion layer, so that the effective area of the substrate where the peripheral circuit is located is reduced, and the integration level of a chip is improved.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The present invention relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a semiconductor device and a manufacturing method thereof.

Background

With the continuous development of semiconductor technology, the integration level of integrated circuits is continuously improved. In the chip design of the integrated circuit, an active device and a passive device are usually integrated at the same time, and the passive device such as a resistor, a capacitor, etc. also occupies the area of the chip, especially in the chip design of the 3D NAND memory, the peripheral circuit is an analog circuit composed of an HVMOS (High Voltage Metal Oxide Semiconductor) device and an LVMOS (Low Voltage Metal Oxide Semiconductor) device, and a large number of resistors are used in the peripheral circuit, and these resistors occupy a large amount of chip area, which is not favorable for improving the integration level of the chip.

Disclosure of Invention

In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, in which a resistor is integrated on a substrate where a memory device is located, so as to reduce the area of the substrate where a peripheral circuit is located.

In order to achieve the purpose, the invention has the following technical scheme:

a semiconductor device, comprising:

the semiconductor device includes a first semiconductor substrate having a first surface and a second surface opposite thereto, the semiconductor substrate including a first region and a second region, the first surface of the first region having a memory device formed thereon;

an insulating ring penetrating the semiconductor substrate in the second region;

a diffusion layer within the insulating ring in the first surface substrate;

a cover layer on the first surface of the second region;

a first extraction structure and a second extraction structure of the diffusion layer in the capping layer.

Optionally, the memory device comprises a stack layer formed by alternately stacking a gate layer and an insulating layer, a memory cell string penetrating through the stack layer, and a memory cell interconnection structure in a dielectric layer above the memory cell string;

the covering layers comprise a first covering layer and a second covering layer, the first covering layer is basically equal to the stacked layers in height, and the second covering layer is the dielectric layer;

the first leading-out structure comprises a first contact penetrating through the diffusion layer of the first covering layer and a first interconnection structure in the second covering layer and on the first contact;

the second extraction structure comprises a second contact penetrating through the diffusion layer of the first covering layer and a second interconnection structure in the second covering layer and on the second contact.

Optionally, the memory cell string includes a channel hole penetrating the stacked layers and a tunneling layer, a charge storage layer, a blocking layer, and a channel layer sequentially formed on sidewalls of the channel hole.

Optionally, a passivation layer on the second surface is also included.

Optionally, the insulating ring is circular or polygonal.

Optionally, the thickness of the semiconductor substrate is less than 10 um.

Optionally, the semiconductor device further comprises a second semiconductor substrate, wherein an MOS device and an interconnection structure of the MOS device are formed on the second semiconductor substrate;

the first surface of the first semiconductor substrate faces the interconnection structure of the MOS device of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are fixed;

the first lead-out structure and the second lead-out structure are respectively and electrically connected with the interconnection structure of the MOS device.

Optionally, the MOS devices include low voltage MOS devices and high voltage MOS devices.

A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor substrate, wherein the first semiconductor substrate is provided with a first surface and a second surface opposite to the first surface, the semiconductor substrate comprises a first region and a second region, and a storage device is formed on the first surface of the first region; a diffusion layer is formed in the substrate on the first surface of the second area, a covering layer is formed on the first surface of the second area, and a first leading-out structure and a second leading-out structure of the diffusion layer are formed in the covering layer;

thinning the first semiconductor substrate from the second surface;

and forming an insulating ring penetrating through the semiconductor substrate in the second region from the second surface, wherein an inner region of the insulating ring covers a diffusion layer region to which the first lead-out structure and the second lead-out structure are connected.

Optionally, after the forming the insulating ring, further comprising:

a passivation layer is formed on the second surface.

Optionally, the insulating ring is circular or polygonal.

Optionally, before the thinning of the first semiconductor substrate from the second surface, the method further includes:

providing a second semiconductor substrate, wherein an MOS device and an interconnection structure of the MOS device are formed on the second semiconductor substrate;

and enabling the first surface of the first semiconductor substrate to face the interconnection structure of the MOS device of the second semiconductor substrate, fixing the first semiconductor substrate and the second semiconductor substrate, and respectively electrically connecting the first lead-out structure and the second lead-out structure with the interconnection structure of the MOS device.

Optionally, forming an insulating ring penetrating the semiconductor substrate in the second region from the second surface includes:

transferring the pattern of the insulating ring into the mask layer through a photoetching process;

under the masking of the mask layer, etching the first semiconductor substrate from the second surface until the first semiconductor substrate is penetrated;

filling of an insulating material is performed to form an insulating ring.

According to the semiconductor device and the manufacturing method thereof provided by the embodiment of the invention, the insulating ring is formed in the semiconductor substrate of the memory device after the thinning process through the etching and filling processes, the insulating ring isolates the substrate from the surrounding substrate, and the diffusion layer is formed in the substrate in the insulating ring, so that the resistance structure with the resistance value adjusted by the diffusion layer is formed in the insulating ring, the diffusion layer of the resistance structure is led out through the two leading-out structures, and the connection and the use of the resistance structure can be realized through the leading-out structures. The resistance structure is formed in the substrate where the memory device is located, the substrate is packaged together with another substrate containing a peripheral circuit, blank areas of non-devices can exist around the memory device area, the resistance structure can be formed in the substrate in the areas, the resistance value of the resistance structure is adjusted by the diffusion layer, and then the resistance structure is led out through the leading-out structure of the diffusion layer, so that the connection and the use of the devices of the peripheral circuit are facilitated, the effective area of the substrate where the peripheral circuit is located is reduced, and the integration level of a chip is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 2 shows a schematic structural diagram of a semiconductor device according to another embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a top view structure of an insulating ring from a first surface in a semiconductor device according to an embodiment of the present invention;

fig. 4-8 are schematic diagrams illustrating cross-sectional structures of devices during the formation of a semiconductor device according to a method of manufacturing an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As described in the background art, in the chip of the integrated circuit, a large number of passive devices such as resistors and the like are also used, and these devices occupy the area of the chip, and in the application of the memory device, with the increasing demand for integration, in order to further increase the memory capacity and reduce the memory cost per bit, a three-dimensional memory device is proposed. In an application of the three-dimensional memory device, the 3D NAND memory device may be an analog circuit including an HVMOS device and an LVMOS device, in which the peripheral circuit includes a large number of resistors, and the resistors occupy a large chip area, which makes the chip area of the peripheral circuit difficult to reduce, and is not favorable for improving the integration level of the chip.

Based on this, the present application proposes a semiconductor device, shown with reference to fig. 1, comprising:

a first semiconductor substrate 100, the first semiconductor substrate 100 having a first surface 101 and a second surface 102 opposite thereto, the semiconductor substrate including a first region 1001 and a second region 1002, the first surface 101 of the first region 1001 having a memory device formed thereon;

an insulating ring 150 penetrating the semiconductor substrate 100 in the second region 1002;

a diffusion layer 104 within the insulating ring 150 in the first surface 101 substrate 100;

a cover layer 120 on the first surface 101 of the second region 1002;

a first lead-out structure 130 and a second lead-out structure 140 of the diffusion layer 104 in the capping layer 120.

In the embodiment of the application, the MOS devices of the peripheral circuits of the memory device and the memory device are respectively formed on different substrates, the resistor structure is formed on the substrate on which the memory device is located, specifically, the insulating ring isolates the substrate inside the ring from the substrate outside the ring, and the diffusion layer is formed in the substrate inside the insulating ring, so that the resistor structure with the resistance adjusted by the diffusion layer is formed inside the insulating ring, the diffusion layer of the resistor structure is led out by the two lead-out structures, and the connection and the use of the resistor structure can be realized by the lead-out structures. The resistance structure is formed in the substrate where the memory device is located, blank areas of non-devices can exist around the memory device area, particularly around the 3D NAND memory device, the resistance structure is formed by utilizing the blank areas, the area of a chip cannot be additionally increased, meanwhile, the resistance value of the resistance structure is adjusted by the diffusion layer, and then the resistance structure is led out through the leading-out structure of the diffusion layer, so that the connection and the use of the devices of a peripheral circuit are facilitated, therefore, the effective area of the substrate where the peripheral circuit is located is reduced, and the integration level of the chip is improved.

In the embodiment of the present application, the memory device may be a three-dimensional memory device, that is, besides the two-dimensional direction of the substrate horizontal, a plurality of memory cells are also distributed in the vertical substrate direction, in this embodiment, the three-dimensional memory device is a 3D NAND memory device, and is formed on the first surface of the substrate 100, the 3D NAND memory device at least includes a stacked layer 110 in which gate layers and insulating layers are alternately stacked, a memory cell string 112 passing through the stacked layer 110, and a memory cell interconnection structure 114 on the memory cell string 112, the interconnection structure 114 is formed in the dielectric layer 124, and is used for leading out the memory cell string, and may include one or more metal layers and contacts, vias, pads, and the like connecting the metal layers.

In the 3D NAND memory device, the stack layer 110 is formed by alternately stacking gate layers and insulating layers, and the gate layer of each layer constitutes one memory cell with the memory cell string 112, thereby also forming a plurality of memory cells in a direction perpendicular to the substrate. Among them, the end of the stacked layer 110 may be a stepped structure (not shown), so that there is a portion of the gate layer of each layer that is not covered by the upper gate layer, and thus it can be used to form a contact of the gate layer of the layer, and thus each layer of the gate layer can be led out. The memory cell string 120 may be formed in a channel hole penetrating the stack layer 110, and the memory cell string 112 sequentially includes a storage function layer, which plays a role of charge storage, generally including a tunneling layer, a charge storage layer, and a blocking layer, and a channel layer, which may be substantially L-shaped, along a sidewall of the channel hole to a center of the channel hole, formed on the sidewall of the storage function layer and a bottom of the channel hole, and a filling layer of an insulating material may be formed between the channel layers. It is understood that, in a specific application, other necessary components may be included on the first surface 101 of the semiconductor substrate 100, such as conductive pads at the top of the memory cell string 114, strobe devices below the memory cell string, etc.

In the embodiment of the present application, referring to fig. 1 and 3, the insulating ring 150 is formed in the substrate 100, the substrate 100 may be a thinned substrate, the thickness of which is generally less than 10um or less, and the penetrating insulating ring 150 may be formed by a conventional semiconductor process, such as photolithography, etching, and filling.

The insulating ring 150 is formed of a material capable of isolating the substrate into different portions, and the material of the insulating ring 150 may be, for example, one or more of dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating ring 150 is a closed ring structure, and serves as an insulating isolation to isolate the substrate inside the ring from the substrate outside the ring, and the substrate inside the insulating ring is used to form a resistor structure. The shape of the insulating ring 150, that is, the shape of the resistor structure, may be set according to needs, and the shape of the insulating ring 150 may be, for example, a polygon or a circle, and the polygon may include a square or other polygons, and the square includes a square and a rectangle, and in this specific example, the shape of the insulating ring 150 is a square, as shown in fig. 3.

In the present application, a diffusion layer 104 is disposed In the insulating ring 150 on the first surface 101 of the substrate, that is, a silicon diffused resistor structure is formed In the insulating ring 150, the diffusion layer 104 is a doped layer In the substrate, the diffusion layer 104 may have P-type doping or N-type doping, the N-type doping ions may be, for example, N, P, As, S, etc., and the P-type doping particles may be, for example, B, Al, Ga, In, etc. In a specific application, the resistance structure with a desired resistance value can be obtained by controlling the process parameters of the diffusion layer 104, such as doping particles, doping concentration, doping depth, and the like, and by combining the area in the insulating ring 150.

The resistor structure is formed on the substrate 100 where the memory device is located, and is formed on a blank area of the memory device, which is not a device, for convenience of description, this area is referred to as a second area 1002, a covering layer 120 is formed on the first surface 101 of the second area 1002, a first lead-out structure 130 and a second lead-out structure 140 of the diffusion layer 104 are formed in the covering layer 120, and the diffusion layer 104 is led out through the first lead-out structure 130 and the second lead-out structure 140. The first lead-out structure 130 and the second lead-out structure 140 serve as two connection terminals of a resistor, so that the resistor structure can be used by circuits in other substrates, such as peripheral circuits.

In particular embodiments, the capping layer 120 may have a different structure, and may be a stacked structure of dielectric materials. The first and second lead-out

structures

130 and 140 are used for electrical lead-out of the diffusion layer 104 and may include contacts, one or more metal layers, and vias, pads, etc. connecting the metal layers. In an embodiment where the memory device is a 3D NAND memory device, the capping layer 120 includes a first capping layer 122 and a second capping layer 124, the first capping layer 122 is substantially as high as the stacked layer 110 of the 3D NAND memory device, and the second capping layer 124 is a dielectric layer 124 of the memory cells of the first region 1001; the first lead-out structure 130 comprises a first contact 132 on the diffusion layer 104 and a first interconnect structure 134 in the second cladding layer 124 and on the first contact 132, which extend through the first cladding layer 122, and the second lead-out structure 140 comprises a second contact 142 on the diffusion layer 104 and a second interconnect structure 144 in the second cladding layer 124 and on the second contact 142, which extend through the first cladding layer 122. The first and

second interconnection structures

134 and 144 may include one or more metal layers and vias, pads, etc. connecting the metal layers, and may have the same structure as the memory device interconnection structure 114 on the memory cell string 112 of the first region 1001, that is, may be formed simultaneously in the same process.

A passivation layer 160 may be further disposed on the second surface 102 of the substrate 100, the passivation layer 160 may serve as a protection, the passivation layer 160 may be one or more layers, and the passivation layer 160 may be, for example, a silicon oxide layer.

The above semiconductor device may be a device on a wafer after the wafer is manufactured, or may be a device in a package structure after the package structure is completed with other wafers, in an embodiment of the package structure, as shown in fig. 2, the package structure further includes a second semiconductor substrate 200, and a MOS device 210 and an interconnection structure 220 of the MOS device are formed on the second semiconductor substrate 200; the first surface 101 of the first semiconductor substrate 100 faces the interconnection structure 220 of the MOS device of the second semiconductor substrate 200, and the first semiconductor substrate 100 and the second semiconductor substrate 200 are fixed, in a specific application, corresponding interconnection structures on the two substrates may be fixed together by a packaging technology, and the first lead-out structure 130 and the second lead-out structure 140 are electrically connected to the interconnection structure 220 of the MOS device, respectively.

The first semiconductor substrate 100 and the second semiconductor substrate 200 are fixed together by a packaging technology, the resistor structure is formed in the substrate where the memory device is located, and the resistor structure is electrically connected with the interconnection structure 220 of the MOS device on the second semiconductor substrate 200 through the first lead-out structure 130 and the second lead-out structure 140, so that the layout of the resistor structure required by the circuit in the second semiconductor substrate 200 can be realized by using an idle region outside the memory device of the first semiconductor substrate 100 without occupying the area of the second semiconductor substrate 200, the effective area of the substrate where the peripheral circuit is located is reduced, and the integration level of the chip is improved.

According to different design requirements, the second semiconductor substrate 200 may have different source-drain operating voltages and device types, in the application of the 3D NAND memory device, the 3D NAND memory device requires a higher driving voltage, its peripheral circuits usually include high-voltage MOS devices and low-voltage MOS devices, i.e., HVMOS and LVMOS, and the device types may be PMOS and/or NMOS. The high-voltage MOS device is a high-voltage MOS device, for example, in a 0.18um CMOS device process, the source-drain operating voltage of the standard MOS device is 1.8V, and the source-drain operating voltage of the standard MOS device is higher than the operating voltage of the standard MOS device. In 3D NAND applications, the source-drain operating voltage of the high voltage MOS device may be higher than 20V, and may typically be 25V.

In a specific embodiment, the MOS device at least includes a gate on the second semiconductor substrate 200, a sidewall of the gate sidewall, and a source-drain region in the substrate on both sides of the gate, the interconnection structure 220 of the MOS device includes one or more metal layers and a via hole, a pad, etc. connected to the metal layers, and the interconnection structure 220 may be disposed on the source-drain region and/or the gate.

The structure of the semiconductor device according to the embodiment of the present application is described in detail above, and in order to better understand the technical solution and the technical effects of the present application, specific embodiments will be described in detail below with reference to the flowchart and the drawings.

Referring to fig. 4, in step S01, a first semiconductor substrate 100 is provided, the first semiconductor substrate 100 having a first surface 101 and a second surface 102 opposite thereto, the semiconductor substrate 100 including a first region 1001 and a second region 1002, the first surface 101 of the first region 1001 having a memory device formed thereon; a diffusion layer 104 is formed in the substrate 100 on the first surface 101 of the second region 1002, a capping layer 120 is formed on the first surface 102 of the second region 1002, and a first lead-out structure 130 and a second lead-out structure 140 of the diffusion layer 104 are formed in the capping layer 120, as shown in fig. 5.

In the preferred embodiment of the present application, the semiconductor substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator) or the like. In this embodiment, the semiconductor substrate 100 may be a silicon substrate.

In the embodiments of the present application, the memory device, the diffusion layer, and the first and second lead-out structures described above have been formed on the first substrate 100, and the present application does not particularly limit the method of forming these devices and structures, and for ease of understanding, the method of forming these devices and structures will be described below with a specific example.

The diffusion layer 104 may be formed in the substrate 100 from the second surface 102 of the second region 1002 after or before forming the memory cell string 112 on the first region 1001. Specifically, the diffusion layer 104 may be formed by implanting a desired type of impurity into the substrate by ion implantation, followed by thermal annealing to activate the doping, as shown with reference to fig. 5. Specifically, the diffusion layer 104 may have P-type doping or N-type doping, the N-type doped ions may be, for example, N, P, As, S, etc., the P-type doped particles may be, for example, B, Al, Ga, In, etc., and parameters such As the doped particles, the doping concentration and depth, etc. may be selected according to the resistance of the resistor structure to be formed.

In this embodiment, the memory device is a three-dimensional NAND memory device, and in a specific implementation, first, a stack layer may be formed in the first region 1001 by alternately stacking a sacrificial layer and an insulating layer, the sacrificial layer and the insulating layer have different etching selectivities, the sacrificial layer is to be removed and replaced by a gate layer, the sacrificial layer may be, for example, silicon nitride, the insulating layer may be, for example, silicon oxide, the number of layers of the sacrificial layer and the insulating layer in the stack layer is determined by the number of memory cells to be formed in the vertical direction, and the number of layers of the sacrificial layer and the insulating layer may be, for example, 32, 64, 128 layers, or the like, which determines the number of memory cells in the vertical direction, so that the greater the number of layers in the stack layer increases the integration degree.

Then, the end of the stack layer 110 may be made to be a step structure by an etching process, the step structure is used for forming a contact on a gate layer later, and the central region of the stack layer is a storage region for forming a memory device.

In forming the memory device, first, a channel hole is formed in the stacked layer, the channel hole may be a via hole in the stacked layer, and the channel hole may be formed by etching the stacked layer using an etching technique until the first surface 101 of the substrate 100 is exposed. Then, an epitaxial structure can be grown in situ at the bottom of the channel hole through Selective epitaxial growth (Selective epitaxial growth), wherein the epitaxial structure is a channel layer of the gate tube device. In the substrate under the channel hole, a doped region may be formed in advance as an active region of the gate device. Then, a memory cell string is formed in the channel hole, and specifically, a memory function layer is now formed on the sidewall of the channel hole, the memory function layer may include a tunneling layer, a charge storage layer, and a blocking layer, specifically, an ONO (Oxide-nitride-Oxide) stack, i.e., an Oxide, a nitride, and an Oxide, and the memory function layer may be L-shaped, exposing the channel layer of the gate device. Then, a channel layer, which may be polysilicon, is deposited, thereby forming a channel layer of the memory device on the memory function layer and the channel layer of the gate transistor device. Finally, the trench holes are filled with an insulating material, such as silicon oxide.

Then, the stacked layer 110 may be etched to form a Gate Line gap (Gate Line Seam), the sacrificial layer in the stacked layer is removed through the Gate Line gap, and simultaneously, a Gate material, which may be, for example, metal tungsten, is filled, a Gate layer is formed in the original sacrificial layer region, and the Gate Line gap is filled. In this way, a stack layer 110 in which gate layers as a control gate of each memory cell of the memory cell string 112 and a control gate of a gate transistor device are alternately stacked with insulating layers is formed.

The device may then be covered with a dielectric material, and the first cover layer 122 will cover both the first surface 101 of the second region 1002 and the step structure (not shown) of the stacked layers, and after the planarization process, the first cover layer 122 on the second region will have a thickness substantially equal to the thickness of the stacked layers.

Thereafter, etching and filling of the first capping layer 122 may be performed, forming the first contact 132 and the second contact 142 on the diffusion layer 104 of the second region 1002, and forming a gate contact (not shown) on the stepped structure of the stacked layers of the first region 1001.

Thereafter, continuing to cover the second cover layer 124 of dielectric material, a first interconnect structure 134 and a second interconnect structure 144 may be simultaneously formed on the first contact 132 and the second contact 142 of the second region 1002, respectively, and an interconnect structure 114 of the memory device may be formed on the memory cell string 112 of the first region 1001, and the interconnect structure may include one or more metal layers, vias and pads connecting the metal layers, and the like.

Thus, the diffusion layer 104 of the memory device and the resistive structure and the lead-out structure of the diffusion layer 104 are formed on the front surface of the first semiconductor substrate 100.

In step S02, thinning of the first semiconductor substrate 100 is performed from the second surface 102, as shown with reference to fig. 6.

When the first semiconductor substrate and the other semiconductor substrate need to be packaged together, a wafer level packaging technology may be adopted, and the first semiconductor substrate and the other semiconductor substrate are packaged first, and then a process of thinning the back surface of the first semiconductor substrate 100 is performed.

In this embodiment, before performing thinning, as shown in fig. 6, the method further includes: providing a second semiconductor substrate 200, wherein a MOS device 210 and an interconnection structure 220 of the MOS device are formed on the second semiconductor substrate 200; the first surface 101 of the first semiconductor substrate 100 faces the interconnection structure 114 of the MOS device of the second semiconductor substrate 200, the first semiconductor substrate 100 and the second semiconductor substrate 200 are fixed, and the first lead-out structure 130 and the second lead-out structure 140 are respectively electrically connected with the interconnection structure 114 of the MOS device.

The second semiconductor substrate 200 has formed thereon MOS devices for constituting peripheral circuits of the memory device, the MOS devices may have different source-drain operating voltages and device types according to different design requirements, in the application of the 3D NAND memory device, the 3D NAND memory device requires a higher driving voltage, the peripheral circuits thereof usually include high-voltage MOS devices and low-voltage MOS devices, i.e., HVMOS and LVMOS, and the device types may be PMOS and/or NMOS.

In a specific application, the MOS device includes a gate dielectric layer on the second semiconductor substrate 200, a gate, a sidewall spacer of a gate sidewall, and a source-drain region in the substrate on both sides of the gate, the interconnection structure 220 of the MOS device includes one or more metal layers and a via hole, a pad, etc. connected to the metal layers, and the interconnection structure 220 may be disposed on the source-drain region and/or the gate. The gate dielectric layer 1 may be, for example, a thermal oxide layer or other suitable dielectric material, such as silicon oxide or a high-k dielectric material, a high-k dielectric gate material such as hafnium-based oxide, HFO₂One or a combination of several of HfSiO, HfSiON, HfTaO, HfTiO, etc. The gate electrode can be, for example, polysilicon, amorphous silicon, or a metal electrode material or a combination thereof, and the metal electrode material can be one or more combinations of TiN, TiAl, Al, TaN, TaC, and W. The sidewall spacers may have a single or multi-layer structure and may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials, combinations thereof, and/or other suitable materials. The source and drain regions have a first doping type,the first doping type may be n-type or p-type. The MOS devices on the second semiconductor substrate 200 may be formed by any method, and the present application is not limited thereto.

When the first semiconductor substrate 100 and the second semiconductor substrate 200 are fixed, the first lead-out structure 130 and the second lead-out structure 140 may be respectively fixed and electrically connected to the interconnection structure 114 of the MOS device by using a packaging technique, such as metal bonding or solder ball connection.

Thus, the first semiconductor substrate 100 and the second semiconductor substrate are electrically connected together, the resistor structure is formed in the substrate where the memory device is located, and the resistor structure is electrically connected with the interconnection structure 220 of the MOS device on the second semiconductor substrate 200 through the first lead-out structure 130 and the second lead-out structure 140, so that the layout of the resistor structure required by the circuit in the second semiconductor substrate 200 can be realized by using the idle region outside the memory device of the first semiconductor substrate 100 without occupying the area of the second semiconductor substrate 200, the effective area of the substrate where the peripheral circuit is located is reduced, and the integration level of the chip is improved.

Thereafter, referring to fig. 6, the reverse side of the first semiconductor substrate 100 may be thinned, so that the substrate 100 has a suitable thickness for facilitating the subsequent processes. Specifically, the second surface 102 of the first semiconductor substrate 100 may be thinned by chemical mechanical polishing until a desired thickness is reached, and typically, the thickness of the thinned first semiconductor substrate 100 is less than 10 um.

In step S03, an insulating ring 150 penetrating the semiconductor substrate 100 is formed in the second region 1002 from the second surface 102, and an inner region of the insulating ring 150 covers a region of the diffusion layer 104 to which the first and

second extraction structures

130 and 140 are connected, as shown with reference to fig. 7.

Since the first semiconductor substrate 100 is thinned and the thickness is greatly reduced, an insulating ring penetrating through the semiconductor substrate can be formed by using the existing semiconductor technology, specifically, a pattern of the insulating ring can be transferred into a mask layer by using a photolithography process, then, under the masking of the mask layer, the substrate 100 is etched from the second surface 102 by using an etching process until the substrate 100 is etched through, the penetrating insulating ring, that is, a closed annular groove, is etched, and then, an insulating material is filled, wherein the insulating material can be one or more of silicon oxide, silicon nitride or silicon oxynitride, so that the insulating ring 150 is formed. By controlling the position of the insulating ring 150, the inner region of the insulating ring 150 covers the region of the diffusion layer 104 where the first lead-out structure 130 and the second lead-out structure 140 are connected, so that a resistive structure is formed in the insulating ring 150.

The shape of the insulating ring 150, that is, the shape of the resistor structure, may be set according to needs, and the shape of the insulating ring 150 may be, for example, a polygon or a circle, and the polygon may be, for example, a square or other shapes, and the square includes a square and a rectangle, and in this specific example, the shape of the insulating ring 150 is a square, as shown in fig. 3. Finally, the resistance of the resistor structure is determined by the substrate area in the insulating ring 150 and the doping of the diffusion layer 104 in the insulating ring 150.

In this way, a resistor structure is integrated in the substrate where the memory device is located, the resistor structure is formed in an insulating ring in the substrate, the resistance value of the resistor structure is adjusted by the diffusion layer, the diffusion layer of the resistor structure is led out by two lead-out structures, and the two lead-out structures are used as two connecting ends of the resistor, so that the resistor structure can be conveniently used by circuits in other substrates, such as peripheral circuits.

Thereafter, referring to fig. 8, a passivation layer 160 may be further formed on the second surface 102. A passivation layer, such as a silicon oxide material, may be deposited and planarized to form the passivation layer.

Thus, the processing of the semiconductor device of the embodiment of the present application is completed.

The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims

1. A semiconductor device, comprising:

an insulating ring penetrating through the semiconductor substrate in the second region, wherein the substrate in the insulating ring is used for forming a resistor structure;

a diffusion layer within the insulating ring in the first surface substrate;

a cover layer on the first surface of the second region;

a first extraction structure and a second extraction structure of the diffusion layer in the cover layer;

the semiconductor device comprises a second semiconductor substrate, wherein an MOS device and an interconnection structure of the MOS device are formed on the second semiconductor substrate;

2. The semiconductor device according to claim 1, wherein the memory device comprises a stack layer in which gate layers and insulating layers are alternately stacked, a memory cell string passing through the stack layer, and a memory cell interconnect structure in a dielectric layer over the memory cell string;

3. The semiconductor device of claim 2, the memory cell string comprising a tunneling layer, a charge storage layer, a blocking layer, and a channel layer sequentially formed through a channel hole of the stacked layers and on sidewalls of the channel hole.

4. The semiconductor device according to claim 1, further comprising a passivation layer on the second surface.

5. The semiconductor device according to claim 1, wherein the insulating ring is circular or polygonal.

6. The semiconductor device according to claim 1, wherein a thickness of the semiconductor substrate is less than 10 um.

7. The semiconductor device of claim 6, wherein the MOS devices comprise a low-voltage MOS device and a high-voltage MOS device.

8. A method of manufacturing a semiconductor device, comprising:

the first surface of the first semiconductor substrate faces towards an interconnection structure of an MOS device of the second semiconductor substrate, the first semiconductor substrate and the second semiconductor substrate are fixed, and the first lead-out structure and the second lead-out structure are respectively and electrically connected with the interconnection structure of the MOS device;

thinning the first semiconductor substrate from the second surface;

and forming an insulating ring penetrating through the semiconductor substrate in the second region from the second surface, wherein the substrate in the insulating ring is used for forming a resistance structure, and the inner region of the insulating ring covers the diffusion layer region connected with the first lead-out structure and the second lead-out structure.

9. The method of manufacturing according to claim 8, further comprising, after forming the insulating ring:

a passivation layer is formed on the second surface.

10. The manufacturing method according to claim 8, wherein the memory device comprises a stack layer in which gate layers and insulating layers are alternately stacked, a memory cell string passing through the stack layer, and a memory cell interconnect structure in a dielectric layer over the memory cell string;

11. The method of claim 10, wherein the memory cell string comprises a tunneling layer, a charge storage layer, a blocking layer, and a channel layer sequentially formed through a channel hole of the stacked layers and on sidewalls of the channel hole.

12. The method of manufacturing of claim 10, wherein the insulating ring is circular or polygonal.

13. The method of manufacturing of claim 8, wherein the MOS devices comprise low voltage MOS devices and high voltage MOS devices.

14. The method of manufacturing according to claim 8, wherein forming an insulating ring penetrating the semiconductor substrate in the second region from the second surface comprises:

filling of an insulating material is performed to form an insulating ring.