CN117393535A

CN117393535A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN117393535A
Application number: CN202311210795.4A
Authority: CN
Inventors: 庄学理; 黄享弘; 林新富
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-09-20
Filing date: 2023-09-19
Publication date: 2024-01-12

Abstract

Embodiments of the present invention provide a semiconductor device. The semiconductor device includes: a substrate having a device region and a peripheral region surrounding the device region; a via disposed at the peripheral region and extending at least partially through the substrate; an insulating structure disposed at the peripheral region, the insulating structure extending at least partially through the substrate and surrounding the via; and a doped region disposed at the peripheral region, over or in the substrate, and adjacent to the via, the doped region being between the via and the insulating structure; and one or more interconnects disposed within an interlayer dielectric (ILD) above the substrate and configured to electrically couple the vias to the doped regions. Embodiments of the present invention also provide methods of manufacturing semiconductor devices.

Description

Semiconductor device and method for manufacturing the same

Technical Field

Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same.

Background

As semiconductor devices, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), are scaled down through various technology nodes, many challenges may arise during implementation of components and processes in Complementary Metal Oxide Semiconductor (CMOS) fabrication. The above-mentioned problems are exacerbated as the gate length and spacing between devices are reduced. For example, it is difficult to prevent parasitic capacitance between gate stacks of MOSFETs due to reduced spacing between the gate stacks, thereby affecting device performance.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor device including: a substrate including a device region and a peripheral region surrounding the device region; a via disposed at the peripheral region and extending at least partially through the substrate; an insulating structure disposed at the peripheral region, and extending at least partially through the substrate and surrounding the via; a doped region disposed at the peripheral region, over or in the substrate, and adjacent to the via, wherein the doped region is located between the via and the insulating structure; and one or more interconnects disposed within an interlayer dielectric (ILD) above the substrate and configured to electrically couple the vias to the doped regions.

Further embodiments of the present invention provide a semiconductor device including: a substrate defining a device region and a peripheral region; a through hole provided in the substrate; a first annular structure disposed at one side of the via hole and separating the via hole from the transistor in the device region; the second annular structure is arranged at the other side of the through hole; and a conductive region disposed between the first annular structure and the second annular structure, wherein the conductive region is configured to be electrically coupled to the via.

Still further embodiments of the present invention provide a method of manufacturing a semiconductor device, the method comprising: providing a substrate, wherein the substrate is provided with a first surface and a second surface opposite to the first surface; forming an isolation structure in the substrate at the first surface; forming a first doped region along the first surface, and surrounding the first doped region by the isolation structure; forming an interconnect structure within the dielectric layer on the first surface, the interconnect structure coupled to the first doped region; removing a portion of the substrate from the second surface to form a first trench exposing a portion of the isolation structure, and removing another portion of the substrate from the second surface to form a second trench exposing a portion of the interconnect structure; filling the first trench with a dielectric material and conformally disposing the dielectric material on sidewalls of the second trench; and filling the second trench with a conductive material, wherein the conductive material is surrounded by a dielectric material.

Still other embodiments of the present invention provide semiconductor devices including insulating structures surrounding through vias and methods of forming the same.

Drawings

Aspects of embodiments of the present disclosure can be best understood from the following detailed description when read with the accompanying drawing figures. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Fig. 2 is a schematic top view illustrating portions of the semiconductor device in fig. 1, according to some embodiments of the present disclosure.

Fig. 3 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

Fig. 4-29 are schematic cross-sectional views illustrating sequential operations of the method illustrated in fig. 3, according to some embodiments of the present disclosure.

Fig. 30A, 30B, 31A and 31B are schematic top views showing portions of the semiconductor device in fig. 1 according to various embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, of the different components used to implement the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "under …," "under …," "lower," "above …," "upper" and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, although terms such as "first," "second," and "third" may describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as "first," "second," and "third" when used herein do not imply a sequence or order unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Furthermore, as used herein, the terms "substantially," "about," and "approximately" generally refer to values or ranges that may be considered by one of ordinary skill in the art. Alternatively, the terms "substantially," "about," and "approximately" mean within an acceptable standard error of the average value when considered by one of ordinary skill in the art. Those of ordinary skill in the art will appreciate that the acceptable standard error may vary according to different techniques. Except in the operating/working examples, or where otherwise expressly indicated, all numerical ranges, amounts, values, and percentages disclosed herein (such as those for amounts of material, durations of time, temperatures, operating conditions, ratios of amounts, etc.) should be understood to be modified in all instances by the terms "substantially," about, "or" about. Accordingly, unless indicated to the contrary, the numerical parameters set forth in this disclosure and attached disclosure are approximations that may vary as desired. At a minimum, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint, or between two endpoints. Unless otherwise indicated, all ranges disclosed herein are inclusive of the endpoints.

Fig. 1 is a schematic cross-sectional view of a semiconductor device 10. Fig. 2 is a schematic top view of the semiconductor device 10 in fig. 1. The cross-sectional view of fig. 1 is taken along line A-A' of fig. 2. Referring to fig. 1, a semiconductor device 10 includes a substrate 100, the substrate 100 defining a device region R1 and a peripheral region R2, the peripheral region R2 being adjacent to the device region R1 or surrounding the device region R1. A plurality of isolation structures 102, 104 are disposed in the substrate 100. A plurality of doped regions 120, 122 are disposed in the substrate 100 and separated by isolation structures 102, 104. The doped region 122 is disposed in the device region R1, and the doped region 120 is disposed in the peripheral region R2. In some embodiments, the doped regions 120, 122 may have the same doping type (e.g., P-type) as the substrate 100. In the device region R1 and within the substrate 100, a well 118 (e.g., an N-well) is disposed between the two isolation structures 104. In some embodiments, the well 118 may have a different doping type (e.g., N-type) than the substrate 100. Doped region 122 is disposed in well 118. Transistor T10 is disposed over well 118. Transistor T10 includes a gate structure 110 and a doped region 122. The gate structure 110 includes a gate dielectric layer 112, a gate electrode layer 114, and a gate spacer 116. A gate dielectric layer 112 is disposed on the substrate 100 between the two isolation structures 104. A gate electrode layer 114 is disposed on the gate dielectric layer 112. Gate spacer 116 surrounds gate electrode layer 114 and gate dielectric layer 112.

An interlayer dielectric (ILD) layer 140 is disposed on the substrate 100 and over the transistor T10. A plurality of conductive contacts 131, 132 and an interconnect structure 145 electrically coupled to the conductive contacts 131, 132 are embedded in the ILD layer 140. The interconnect structure 145 includes a plurality of high level conductive features such as conductive lines 145A and conductive vias 145B. One end of the interconnect structure 145 is electrically coupled to the doped region 120, and the other end of the interconnect structure 145 is electrically coupled to the doped region 122 and the transistor T10.

A Through Silicon Via (TSV) structure 170 is disposed in the peripheral region R2. TSV structures 170 extend at least partially through substrate 100 and/or ILD layer 140. In some embodiments, TSV structure 170 is surrounded by first insulating member 166. The TSV structure 170 is isolated from the substrate 100 by a first insulating member 166. In some embodiments, TSV structure 170 directly contacts first insulating member 166. A plurality of second insulating members 162, 164 are disposed in the peripheral region R2. In some embodiments, the second insulating member 162 and the second insulating member 164 extend parallel to each other. In some embodiments, each of the second insulating members 162, 164 is parallel to the first insulating member 166. The second insulating members 162, 164 extend at least partially through the substrate 100 and around the TSV structures 170. The TSV structures 170 are separated from the second insulating members 162, 164. The interconnect structure 145 is disposed over the TSV structure 170 and the second insulating members 162, 164. Interconnect structure 145 is electrically coupled to TSV structure 170 through conductive line 145A. A first passivation layer 152 (e.g., made of silicon oxide) is disposed on a side of the substrate 100 facing away from the interconnect structure 145. A second passivation layer 154 (e.g., made of silicon nitride) is disposed on the first passivation layer 152. Conductive pads 180 are disposed on TSV structures 170 and electrically coupled to TSV structures 170. A bias voltage may be applied to TSV structure 170 via conductive pad 180.

Referring to fig. 2, from a top view of the semiconductor device 10, the second insulating member 164 is disposed at one side of the TSV structure 170, and the second insulating member 162 is disposed at the other side of the TSV structure 170. The second insulating member 164 is closer to the device region R1 than the second insulating member 162. In some embodiments, the second insulating member 164 is a ring-shaped structure surrounding the device region R1, and fig. 2 only shows portions of the second insulating member 164. The second insulating member 164 separates the TSV structure 170 in the peripheral region R2 from the transistor T10 in the device region R1. In some embodiments, the second insulating member 162 is a ring-shaped structure that surrounds the doped region 120 and the TSV structure 170 together with the second insulating member 164, and fig. 2 only shows a portion of the second insulating member 162. The doped region 120 is disposed adjacent to the TSV structure 170 and between the second insulating member 162 and the second insulating member 164. Each of the second insulating members 162 and 164 has a width W1 of between about 0.3 micrometers (μm) and about 5 μm, about 0.8 μm, or other similar values. The TSV structures 170 and the first insulating member 166 together have a width W2 of between about 1 μm and about 10 μm, between about 3 μm and about 4 μm, or other similar values. Doped region 120 has a length L1 of between about 0.1 μm and about 10 μm, about 2 μm, or other similar values.

Without coupling the interconnect structure 145 to the portion of the substrate 100 between the second insulating members, the high voltage applied to the TSV structure 170 may cause dielectric breakdown of the first insulating member 166 (e.g., because the adjacent portion of the substrate 100 is substantially grounded). However, because the interconnect structure 145 couples the TSV structure 170 to the doped region 120, the portion of the substrate 100 located between the second insulating members 162, 164 may be maintained at substantially the same voltage potential as the TSV structure 170. Maintaining the TSV structure 170 and the portion of the substrate 100 located between the second insulating members 162, 164 at substantially the same voltage potential mitigates the electric field between the TSV structure 170 and the substrate 100 and thereby reduces dielectric breakdown between the TSV structure 170 and the substrate 100 during application of high voltages (e.g., voltages greater than or equal to about 200V). Thus, the disclosed structure may be used in high voltage applications. In addition, the second insulating member 164 will mitigate any diffusion of metal (e.g., copper) from the TSV structure 170 to the device region R1.

Fig. 3 is a flow chart of a method 200 of fabricating the semiconductor device 10 of fig. 1. Fig. 4-29 are schematic cross-sectional views illustrating sequential operation of the method 200 shown in fig. 3. The method 200 includes a number of operations (201, 203, 205, 207, 209, 211, 213, 215, 217, 219, 221, 223, and 225) and the description and illustration is not to be considered as limiting the order of the operations.

In operation 201 of fig. 3, a substrate 100 is provided, as shown in fig. 4. The substrate 100 may be a semiconductor substrate, such as a bulk silicon wafer. In some embodiments, the substrate 100 is a semiconductor-on-insulator (SOI) substrate, a multilayer substrate, a gradient substrate, or the like. The substrate 100 may include a semiconductor material such as Si, ge; a compound semiconductor or alloy semiconductor including SiC, siGe, gaAs, gaP, gaAsP, alInAs, alGaAs, gaInAs, inAs, gaInP, inP, inSb or GaInAsP; or a combination thereof. The substrate 100 may be doped or undoped. In some embodiments, substrate 100 comprises P-type monocrystalline silicon. The substrate has a first surface S1 and a second surface S2 opposite to the first surface S1.

In operation 203 of fig. 3, a plurality of isolation structures 102, 104 are formed in the substrate 100, as shown in fig. 5. The isolation structures 102, 104 may be Shallow Trench Isolation (STI) regions located in the substrate 100. In some other embodiments, the isolation structures 102, 104 are formed over the substrate 100. STI regions may have different widths or dimensions. For example, the isolation structure 104 has a size that is larger than the size of the isolation structure 102. Forming the isolation structures 102, 104 includes forming a plurality of trenches on the first surface S1 in the substrate 100 by any acceptable etching operation, such as Reactive Ion Etching (RIE) or dry etching. An insulating material is then deposited to fill the trenches. The insulating material may be silicon oxide, silicon nitride, or a combination thereof. The insulating material may be deposited using Chemical Vapor Deposition (CVD), atmospheric Pressure CVD (APCVD), high density plasma CVD (HDP-CVD), or other suitable methods. Any excess insulating material is removed from the first surface S1 using a planarization operation, such as a Chemical Mechanical Polishing (CMP) operation, such that the top surfaces of the isolation structures 102, 104 are coplanar with the first surface S1 (e.g., coplanar within the tolerances of the CMP operation).

In operation 205 of fig. 3, a plurality of doped regions are formed in the substrate 100, as shown in fig. 6 and 7. Referring to fig. 6, an implantation mask 117 is formed on a portion of the substrate 100 while exposing portions of the substrate 100 between the isolation structures 104. A first ion implantation operation D1 is performed on the exposed substrate 100. The first ion implantation operation D1 may employ a dopant having a first doping type. In some embodiments, the dopant may include an N-type dopant, such As a phosphorus (P) or arsenic (As) atom or ion. The openings of implantation mask 117 allow dopants to penetrate into substrate 100. After a period of time, the first ion implantation operation D1 is stopped depending on the desired depth of the well.

Referring to fig. 7, n-type dopants may be diffused to a predetermined depth in the substrate 100 and form the well 118. The well 118 is formed at the first surface S1 and is located between the isolation structures 104. The implantation mask 117 is then removed. An annealing operation, such as a Rapid Thermal Annealing (RTA) operation, may be used to activate the implanted dopants. In some embodiments, well 118 may comprise an N-well configured to act as a conductive region, and well 118 serves as the body of a P-channel transistor. Although not specifically shown, appropriate doped regions may be formed in the substrate 100. For example, lightly Doped Drain (LDD) regions may be formed in the well 118 after the well 118 is formed. In some other examples, LDD regions may be formed after operation 205.

In operation 207 of fig. 3, a gate structure 110 is formed on the substrate 100, as shown in fig. 8 and 9. Referring to fig. 8, in some embodiments, forming the gate structure 110 includes depositing or thermally growing an oxide layer on the first surface S1 of the substrate 100. CVD or other suitable methods may then be used to form a polysilicon layer over the oxide layer. A photoresist pattern or patterned nitride hard mask is formed on the polysilicon layer. An etching operation such as RIE or dry etching is used to pattern the polysilicon layer and the oxide layer. The photoresist pattern or the pattern of the patterned nitride hard mask is transferred to the polysilicon layer and the oxide layer to form the gate electrode layer 114 and the gate dielectric layer 112, respectively. A gate dielectric layer 112 is formed on the first surface S1 between the isolation structures 104, and a gate electrode layer 114 is formed on the gate dielectric layer 112.

Referring to fig. 9, a gate spacer 116 may be formed so as to surround the gate electrode layer 114 and the gate dielectric layer 112. Forming gate spacers 116 includes conformally forming a dielectric material over substrate 100, isolation structures 102, 104, gate dielectric layer 112, and gate electrode layer 114 using CVD or other suitable method. The dielectric material may be silicon nitride, silicon carbonitride, combinations thereof, and the like. An anisotropic etch is used to remove portions of the dielectric material and leave the dielectric material on the sidewalls of gate dielectric layer 112 and gate electrode layer 114, thereby forming gate spacers 116. Gate dielectric layer 112, gate electrode layer 114, and gate spacers 116 form gate structure 110. The order of formation of the gate structure 110 and the well 118 may not be limited. In some other embodiments, the gate structure 110 is formed prior to forming the well 118.

Although not specifically illustrated, in some other embodiments, the gate structure 110 is formed using a "Replacement Metal Gate (RMG)" technique. For example, a dummy gate structure may be formed on the first surface S1 of the substrate 100. The dummy gate structure includes a dummy gate dielectric layer and a dummy gate electrode layer on the dummy gate dielectric layer. The dummy gate structure may be replaced by a functional gate structure. The functional gate structure may include a high dielectric constant (high-k) dielectric material as its gate dielectric layer and one or more metals as its gate electrode layer. The high-k dielectric material may include HfO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or other suitable dielectric material. The metal may include W, cu, co, al, ni, ta, ti, mo, pd, pt, ru, ir, ag, au, the like, or a combination thereof. A diffusion barrier layer and/or a work function layer may be disposed between the gate dielectric layer and the gate electrode layer. The diffusion barrier layer and work function layer may comprise TiN, taN, WN, the like, or a combination thereof.

Referring to fig. 10, a second ion implantation operation D2 is performed on the exposed substrate 100. The second ion implantation operation D2 may employ a dopant having a second doping type. In some embodiments, the dopant may include a P-type dopant, such as boron (B), indium (In), or gallium (Ga) atoms or ions. During the second ion implantation operation D2, the gate spacers 116 may function as an implantation mask. After a period of time, the second ion implantation operation D2 is stopped, depending on the desired depth of the doped region.

Referring to fig. 11, dopants may be diffused to a predetermined depth in the substrate 100 and a plurality of doped regions 120, 122 are formed. Doped regions 120, 122 are formed at the first surface S1 and between the isolation structures 102, 104. An annealing operation, such as an RTA operation, may be used to activate the implanted dopants. In some embodiments, where the doped regions 120, 122 are P-type and conductive, the doped region 120 may be referred to as P ⁺ The oxide defines the (OD) region, and its function will be described below. Doped region 122 is located within well 118 and at an opposite side of gate structure 110. After forming the doped region 122, the transistor T10 is formed. The transistor T10 includes a gate structure 110 as a gate terminal and a doped region 122 as a source/drain (S/D) terminal. The substrate 100 may define a device region R1 and a peripheral region R2 adjacent to the device region R1. The device region R1 is a region where the transistor T10 or other transistors are disposed. The peripheral region R2 is a region where no transistor is provided. The peripheral region R2 may surround the device region R1.

Although not specifically illustrated, suitable doped regions may be formed in the substrate 100. For example, LDD regions may be formed in the well 118 after forming the gate spacers 116 or before forming the doped regions 120, 122. Due to the presence of the LDD region, the transistor T10 has a smaller electric field in the vicinity of the drain region, and thus the so-called hot carrier effect can be reduced.

In operation 209 of fig. 3, a plurality of conductive contacts 131, 132 are formed over the substrate 100, as shown in fig. 12-14. Referring to fig. 12, an interlayer dielectric (ILD) layer 130 is formed over the substrate 100. ILD layer 130 may be formed using spin coating, CVD, ALD, and/or other suitable methods. ILD layer 130 may be made of silicon oxide, silicon nitride, undoped Silicate Glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), or other suitable materials. In some embodiments, the dielectric material of ILD layer 130 comprises an Extremely Low K (ELK) dielectric material having a dielectric constant between 2.0 and 3.0. ILD layer 130 may cover isolation structures 102, 104, doped regions 120, 122, and transistor T10. In some embodiments, a CMP operation is used to planarize ILD layer 130 without exposing the top surface of transistor T10. In such an embodiment, the top surface of planarized ILD layer 130 is higher than the top surface of transistor T10, as shown in fig. 12.

Referring to fig. 13, a plurality of contact holes Tl, T2 are formed in the ILD layer 130. The contact holes T1, T2 may be formed using any acceptable etching operation, such as RIE or dry etching. The contact holes T1, T2 may penetrate the ILD layer 130. The contact hole T1 may expose the doped region 120, and the contact hole T2 may expose the doped region 122.

Referring to fig. 14, a conductive material, such as W, cu, co, al, ni, ta, ti, mo, pd, pt, ru, ir, ag, au, or the like, or a combination thereof, is deposited in the contact holes T1, T2. Sputtering, electroplating, PVD or other suitable methods may be used to form the conductive material. A CMP operation is used to remove any excess conductive material from the top surface of ILD layer 130 to form conductive contacts 131, 132. The conductive contacts 131, 132 may be formed simultaneously or separately, and the order in which the conductive contacts 131 and 132 are formed is not limited. Conductive contact 131 may be electrically coupled to doped region 120 and conductive contact 132 may be electrically coupled to doped region 122. Although not specifically shown, a diffusion barrier layer (not shown) may be disposed between each conductive contact 131 and ILD layer 130, and between each conductive contact 132 and ILD layer 130. The diffusion barrier layer may be formed from TiN, taN, ta, ti, tiSN, taSN, W, WN or a combination thereof using ALD, PVD or other suitable methods. A diffusion barrier layer may be used to prevent the conductive material of the conductive contacts 131, 132 from diffusing into the ILD layer 130.

In operation 211 of fig. 3, an interconnect structure 145 is formed over the conductive contacts 131, 132, as shown in fig. 15. The interconnect structure 145 includes a plurality of high level conductive features such as conductive lines 145A and conductive vias 145B. More dielectric material may be formed over ILD layer 130 to form ILD layer 140 prior to forming interconnect structure 145. ILD layer 140 may be formed by repeatedly stacking dielectric materials as each layer of conductive lines or conductive vias is formed. Although not illustrated, a series of lithography, etching, deposition, and planarization operations may be used to form the interconnect structure 145. The conductive lines and conductive vias may be formed using a single damascene process or a dual damascene process. The conductive lines and conductive vias may be embedded in one or more dielectric layers. Interconnect structure 145 is surrounded by ILD layer 140. The conductive lines and the conductive vias may be electrically coupled to each other. Interconnect structure 145 may be electrically coupled to conductive contacts 131, 132, doped regions 120, 122, and transistor T10 or more.

In operation 213 of fig. 3, the substrate 100 is flipped as shown in fig. 16. In order to pattern the second surface S2 of the substrate 100 in a subsequent operation, the substrate 100 is flipped such that the second surface S2 faces upward.

In operation 215 of fig. 3, a plurality of passivation layers 152, 154 are formed on the substrate 100, as shown in fig. 17. In some embodiments, the first passivation layer 152 is formed on the second surface S2 of the substrate 100. In some embodiments, the first passivation layer 152 is made of silicon oxide. The first passivation layer 152 may be formed by an HDP-CVD operation. The first passivation layer 152 may have a thickness of between about 0.2 micrometers (μm) and about 2 μm. Forming a silicon oxide surface on the substrate 100 may reduce the severity of narrow trenches that will be formed in subsequent operations.

In some embodiments, a second passivation layer 154 is formed on the first passivation layer 152. The second passivation layer 154 may directly contact the first passivation layer 152. In some embodiments, the second passivation layer 154 is comprised of silicon nitride or silicon oxynitride. The second passivation layer 154 may be formed by a Low Pressure CVD (LPCVD) operation or a Plasma Enhanced CVD (PECVD) operation. The second passivation layer 154 may have a thickness of between about 2 μm and about 6 μm. Forming a silicon nitride or silicon oxynitride surface may act as a barrier to moisture that may be present in subsequent operations.

In operation 217 of fig. 3, a plurality of trenches are formed through the substrate 100, as shown in fig. 18-24. Referring to fig. 18, a photoresist layer 156 is coated on the second passivation layer 154. Photoresist layer 156 is exposed to radiation P1, such as Deep Ultraviolet (DUV) or Extreme Ultraviolet (EUV), through photomask M1. In some embodiments, a photomask M1 is used to define trench features and Through Silicon Via (TSV) features.

Referring to fig. 19, after development, the exposed photoresist layer 156 may form a photoresist pattern 158 including a plurality of openings O1, O2. The openings O1, O2 expose portions of the second passivation layer 154.

Referring to fig. 20, a first etching operation E1 is performed on the second passivation layer 154, the first passivation layer 152, and the substrate 100 using the photoresist pattern 158 as an etching mask. The first etching operation E1 may include RIE or dry etching. In some embodiments, will be based on chlorine (Cl) ₂ ) Is used as an etchant for the substrate 100 with a high etch rate ratio of silicon to silicon oxide. The etchant may pass through the photoresist pattern 158 via the openings O1, O2.

Referring to fig. 21, the first etching operation E1 removes portions of the second passivation layer 154, the first passivation layer 152, and the substrate 100, terminating at the surfaces of the isolation structures 102, 104. A plurality of trenches O10 and O20 are formed through the substrate 100. Trench O10 exposes a portion of isolation structure 104 and trench O20 exposes a portion of isolation structure 102. In some embodiments, the trench O10 has a width W1 of between about 0.3 μm and about 5 μm, about 0.8 μm, or other similar values. In some embodiments, the trench O20 has a width W2 of between about 1 μm and about 10 μm, between about 3 μm and about 4 μm, or other similar values. In some embodiments, width W2 is greater than width W1.

Referring to fig. 22, a second etching operation E2 is performed on the isolation structure 102 and portions of the ILD layer 140 through the trench O20. The second etching operation E2 may include RIE or dry etching. In some embodiments, the composition will be based on trifluoromethane (CHF ₃ ) Is used as an etchant in the second etching operation E2, which has a high etching rate ratio of silicon oxide to silicon.

Referring to fig. 23, a second etching operation E2 removes portions of the isolation structure 102 and ILD layer 140 exposed by the trench O20, terminating at the surface of the conductive line 145A. The trench O20 is enlarged to form a trench O22. Trench O22 penetrates one of isolation structures 102 and exposes a portion of interconnect structure 145. The groove O22 may be parallel to the groove O10.

Referring to fig. 24, after forming the trenches O10, O22, the photoresist pattern 158 is removed using, for example, a plasma ashing operation.

In operation 219 of fig. 3, an insulating layer 160 is deposited in the trenches O10, O22, as shown in fig. 25 and 26. Referring to fig. 25, an insulating layer 160 is formed on the second passivation layer 154 and in the trenches O10, O22. In some embodiments, the insulating layer 160 is composed of silicon oxide and the insulating layer 160 is formed using an Atomic Layer Deposition (ALD) operation. In other embodiments, insulating layer 160 may comprise silicon nitride, silicon carbide, tetraethyl orthosilicate (TEOS), and the like. The ALD operation may be performed for a certain time until the trench O10 is completely filled with the insulating layer 160. Because the width W2 of the trench O22 is greater than the width W1 of the trench O10, the trench O22 is not filled with the insulating layer 160 until the trench O10 is completely filled. A thin film of insulating layer 160 may be conformally deposited on the sidewalls of trench O22. At this point a portion of wire 145A may remain exposed.

Referring to fig. 26, the insulating layer 160 is removed from the top surface of the second passivation layer 154 using a CMP operation. The second insulating member 162 and the second insulating member 164 may be formed on the isolation structures 102 and 104, respectively. The second insulating members 162, 164 may be Deep Trench Isolation (DTI) structures. The first insulating member 166 may be formed to line sidewalls of the trench O22. The first insulating member 166 may contact the wire 145A. The first insulating member 166 may be parallel to the second insulating member 162 or the second insulating member 164.

In operation 221 of fig. 3, a conductive material is deposited in the trench O22 to form a TSV structure 170, as shown in fig. 27. The conductive material may include W, cu, co, al, ni, ta, ti, mo, pd, pt, ru, ir, ag, au, the like, or a combination thereof. Sputtering, electroplating, PVD or other suitable methods may be used to form the conductive material. Any excess conductive material is removed from the top surface of the second passivation layer 154 using a CMP operation, thereby forming TSV structures 170. In some embodiments, TSV structure 170 is surrounded by first insulating member 166. TSV structures 170 may be electrically coupled to interconnect structures 145 by conductive lines 145A. In some embodiments, the interconnect structure 145 over the substrate 100 is configured to electrically couple the TSV structure 170 to the doped region 120.

In operation 223 of fig. 3, conductive pads 180 are formed on TSV structures 170, as shown in fig. 28. Portions of the second passivation layer 154 and the TSV structures 170 can be removed to form openings. Conductive material such as Cu or Al may be deposited in the openings to form the conductive pads 180. A bias voltage may be applied to TSV structure 170 via conductive pad 180.

In operation 225 of fig. 3, the substrate 100 is flipped again, as shown in fig. 29. At this stage, the semiconductor device 10 is completed. In some embodiments, if a wafer on wafer (WoW) bonding operation is subsequently performed on the semiconductor device 10, a carrier wafer 190 is disposed over the interconnect structure 145. Carrier wafer 190 may be formed directly on ILD layer 140.

Fig. 30A, 30B, 31A and 31B are schematic top views showing portions of the semiconductor device 10 in fig. 29 according to various embodiments. Referring to fig. 30A and 30B, in some embodiments, the second insulating members 162, 164 in top view appear as part of a ring-shaped structure. In some embodiments, one TSV structure 170 is disposed between the second insulating member 162 and the second insulating member 164, as shown in fig. 30A. In some other embodiments, a plurality of TSV structures 170 are disposed between the second insulating member 162 and the second insulating member 164, as shown in fig. 30B. In some embodiments, the second insulating member 164 is disposed at one side of the TSV structure 170, and the second insulating member 162 is disposed at the other side of the TSV structure 170. The second insulating member 164 separates the TSV structure 170 in the peripheral region R2 from the transistor T10 in the device region R1. The annular structure of the second insulating members 162, 164 may function as a barrier layer that prevents conductive material (such as Cu) of the TSV structure 170 from diffusing into the silicon of the substrate 100 proximate to the device region R1. In some embodiments, the doped region 120 is disposed adjacent to the at least one TSV structure 170, and the doped region 120 is disposed between the second insulating member 162 and the second insulating member 164. In some embodiments, doped region 120 has a length L1 of between about 0.1 μm and about 10 μm, about 2 μm, or other similar values. In some embodiments, doped region 120 is configured to be supplied with the same potential as the bias voltage applied to TSV structure 170. By such a design, the lateral electric field at the TSV sidewall oxide (i.e., the first insulating member 166 surrounding the TSV structure 170) may be significantly reduced. Since the TSV structure 170 is enclosed in the first insulating member 166, the first insulating member 166 may function as a barrier layer that prevents the conductive material of the TSV structure 170 from diffusing to the silicon of the nearby substrate 100. Thereby, possible current leakage paths to the silicon of the substrate 100 may be prevented. The risk of potential drop at the interface between TSV structure 170 and substrate 100 is reduced. In addition, since the doped region 120 is supplied with the same potential as the bias voltage applied to the TSV structure 170, the TSV sidewall oxide may not be burned out due to the potential equalization. As a result, the tsv sidewall oxide may not break down even when the bias voltage is high, e.g., greater than 200 v.

Referring to fig. 31A, in some other embodiments, the second insulating members 162, 164 are replaced with a single insulating member 168 disposed at the peripheral region R2. The insulating member 168 is similar to the second insulating member 162 or the second insulating member 164, but has a different shape. In a top view, the insulating member 168 has an annular profile surrounding the doped region 120 and the TSV structure 170.

Referring to fig. 31B, in some other embodiments, an insulating member 168 surrounds one doped region 120 and a plurality of TSV structures 170 in a top view. In some embodiments, doped region 120 is configured to be supplied with the same potential as the bias voltage applied to one of TSV structures 170. In some other embodiments, the bias voltage is applied to all TSV structures 170 at the same time, and doped region 120 is configured to be supplied with the same potential as the bias voltage applied to all TSV structures 170.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate including a device region and a peripheral region surrounding the device region. A via is disposed at the peripheral region and extends at least partially through the substrate. An insulating structure is disposed at the peripheral region, and the insulating structure extends at least partially through the substrate and surrounds the via. The doped region is disposed at the peripheral region, above or in the substrate, and adjacent to the via. The doped region is located between the via and the insulating structure. One or more interconnects are disposed within an interlayer dielectric (ILD) above the substrate and configured to electrically couple the vias to the doped regions.

In some embodiments, the insulating structure surrounds the doped region.

In some embodiments, the insulating structure has an annular profile surrounding the via and the doped region from a top view.

In some embodiments, the semiconductor device further comprises a barrier layer between the substrate and the via, wherein the barrier layer surrounds the via.

In some embodiments, the semiconductor device further includes a transistor disposed in the device region, wherein an insulating structure is disposed between the transistor and the via.

In some embodiments, the semiconductor device further comprises: a dielectric layer disposed over the substrate; and an interconnect structure disposed in the dielectric layer and over the via and the device region, wherein one end of the interconnect structure is electrically coupled to the doped region and the other end of the interconnect structure is electrically coupled to the transistor.

In some embodiments, the via is electrically coupled to the interconnect structure.

Yet another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a substrate defining a device region and a peripheral region; a through hole provided in the substrate; a first annular structure disposed at one side of the via hole and separating the via hole from the transistor in the device region; the second annular structure is arranged at the other side of the through hole; and a conductive region disposed between the first annular structure and the second annular structure, wherein the conductive region is configured to be electrically coupled to the via.

In some embodiments, the first annular structure and the second annular structure are trench isolation structures.

In some embodiments, the conductive region between the first annular structure and the second annular structure is proximate to the via.

In some embodiments, the semiconductor device further includes an interconnect structure disposed over the substrate, and the interconnect structure is configured to electrically couple the via to the conductive region.

In some embodiments, the via, the first ring structure, and the second ring structure are disposed at the peripheral region, and the transistor is disposed at the device region.

In some embodiments, the via includes a conductive material surrounded by a dielectric, the dielectric isolating the conductive material from the substrate.

Yet another aspect of the present disclosure provides a method of manufacturing a semiconductor device, the method comprising: providing a substrate, wherein the substrate is provided with a first surface and a second surface opposite to the first surface; forming an isolation structure in the substrate at the first surface; forming a first doped region along the first surface, and surrounding the first doped region by the isolation structure; forming an interconnect structure within the dielectric layer on the first surface, the interconnect structure coupled to the first doped region; removing a portion of the substrate from the second surface to form a first trench exposing a portion of the isolation structure, and removing another portion of the substrate from the second surface to form a second trench exposing a portion of the interconnect structure; filling the first trench with a dielectric material and conformally disposing the dielectric material on sidewalls of the second trench; and filling the second trench with a conductive material, wherein the conductive material is surrounded by a dielectric material.

In some embodiments, the dielectric material is formed by Atomic Layer Deposition (ALD).

In some embodiments, the method further comprises: forming a gate structure along a first surface of a substrate; and forming a second doped region on one side of the gate structure, wherein, after forming the interconnect structure, one end of the interconnect structure is electrically coupled to the first doped region and the other end of the interconnect structure is electrically coupled to the second doped region.

In some embodiments, the method further includes disposing a carrier wafer on the dielectric layer and over the interconnect structure.

In some embodiments, the second trench filled with the conductive material forms a Through Silicon Via (TSV) structure electrically coupled to the interconnect structure.

In some embodiments, the first doped region is configured to be supplied with a first potential voltage that is the same as a second potential voltage applied to the through silicon via structure.

In some embodiments, the first trench filled with a dielectric material forms an insulating member surrounding the through silicon via structure and the first doped region.

One aspect of the present disclosure provides another semiconductor device. The semiconductor device includes a substrate. A via is disposed in the substrate. A first ring structure is disposed at one side of the via and separates the via from the transistor in the device region. The second annular structure is disposed at the other side of the through hole. A conductive region is disposed between the first annular structure and the second annular structure. The conductive region is configured to be electrically coupled to the via.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method comprises the following steps: providing a substrate, wherein the substrate is provided with a first surface and a second surface opposite to the first surface; forming an isolation structure in the substrate at the first surface; forming a doped region along the first surface, the isolation structure surrounding the doped region; forming an interconnect structure within the dielectric layer on the first surface, the interconnect structure coupled to the doped region; removing a portion of the substrate from the second surface to form a first trench exposing a portion of the isolation structure, and removing another portion of the substrate from the second surface to form a second trench exposing a portion of the interconnect structure; filling the first trench with a dielectric material and conformally disposing the dielectric material on sidewalls of the second trench; and filling the second trench with a conductive material, wherein the conductive material is surrounded by a dielectric material.

The foregoing outlines features of a drop-off embodiment so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a substrate including a device region and a peripheral region surrounding the device region;

a via disposed at the peripheral region and extending at least partially through the substrate;

an insulating structure disposed at the peripheral region, and extending at least partially through the substrate and surrounding the via;

a doped region disposed at the peripheral region, over or in the substrate, and adjacent to the via, wherein the doped region is located between the via and the insulating structure; and

one or more interconnects disposed within an interlayer dielectric above the substrate and configured to electrically couple the via to the doped region.

2. The semiconductor device of claim 1, wherein the insulating structure surrounds the doped region.

3. The semiconductor device of claim 1, wherein the insulating structure has an annular profile surrounding the via and the doped region from a top view.

4. The semiconductor device of claim 1, further comprising a barrier layer between the substrate and the via, wherein the barrier layer surrounds the via.

5. The semiconductor device of claim 1, further comprising a transistor disposed in the device region, wherein the insulating structure is disposed between the transistor and the via.

6. The semiconductor device of claim 5, further comprising:

a dielectric layer disposed over the substrate; and

an interconnect structure disposed in the dielectric layer and over the via and the device region, wherein,

one end of the interconnect structure is the doped region and the other end of the interconnect structure is coupled to the transistor.

7. The semiconductor device of claim 6, wherein the via is electrically coupled to the interconnect structure.

8. A semiconductor device, comprising:

a substrate defining a device region and a peripheral region;

a through hole provided in the substrate;

a first annular structure disposed at one side of the via and separating the via from the transistor in the device region;

the second annular structure is arranged at the other side of the through hole; and

a conductive region disposed between the first annular structure and the second annular structure, wherein the conductive region is configured to be electrically coupled to the via.

9. The semiconductor device of claim 8, wherein the first and second ring structures are trench isolation structures.

10. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein the substrate is provided with a first surface and a second surface opposite to the first surface;

forming an isolation structure in the substrate at the first surface;

forming a first doped region along the first surface, the isolation structure surrounding the first doped region;

forming an interconnect structure within the dielectric layer on the first surface, the interconnect structure coupled to the first doped region;

removing a portion of the substrate from the second surface to form a first trench exposing a portion of the isolation structure, and removing another portion of the substrate from the second surface to form a second trench exposing a portion of the interconnect structure;

filling the first trench with a dielectric material and conformally disposing the dielectric material on sidewalls of the second trench; and

the second trench is filled with a conductive material, wherein the conductive material is surrounded by the dielectric material.