CN110660737A - Method for forming integrated circuit structure - Google Patents

Method for forming integrated circuit structure Download PDF

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Publication number
CN110660737A
CN110660737A CN201910298757.6A CN201910298757A CN110660737A CN 110660737 A CN110660737 A CN 110660737A CN 201910298757 A CN201910298757 A CN 201910298757A CN 110660737 A CN110660737 A CN 110660737A
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China
Prior art keywords
integrated circuit
source
fin
well
forming
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CN201910298757.6A
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Chinese (zh)
Inventor
林杰峯
叶震亚
林志勇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/263,656 external-priority patent/US10665673B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110660737A publication Critical patent/CN110660737A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The embodiment of the disclosure provides a forming method of an integrated circuit structure, which comprises the steps of receiving a semiconductor substrate, wherein the semiconductor substrate comprises an integrated circuit unit and a well connecting unit surrounding the integrated circuit unit; forming a plurality of first fin-shaped active regions in the well connection unit and forming a plurality of second fin-shaped active regions in the integrated circuit unit; forming a hard mask in the well connecting unit, wherein the hard mask comprises a plurality of openings, and the openings define a plurality of first source/drain regions on a first fin-shaped active region of the well connecting unit; forming a plurality of gate stacks on a second fin-shaped active region in the integrated circuit unit without forming the gate stacks in the well connecting unit, wherein the gate stacks define a plurality of second source/drain regions on the second fin-shaped active region; epitaxially growing a plurality of first source/drain structures in the first source/drain regions, and using a hard mask to limit epitaxial growth; and forming a plurality of contacts landed on the first source/drain structure in the well connecting unit.

Description

Method for forming integrated circuit structure
Technical Field
Embodiments of the present disclosure relate to integrated circuit structures and methods of forming the same.
Background
An integrated circuit includes a variety of device units, each having a function. A guard ring may surround the cells to provide a consistent operating environment for devices in the integrated circuit cells. The existing grommet structures face a variety of problems and concerns. For example, the guard ring includes a dummy gate and a source/drain structure having the dummy gate to limit the formation of the source/drain. However, the dummy gate is limited by gate design rules such as spacing between gate ends, which increases guard ring size and reduces circuit area. In addition, dummy gates also increase gate density, which also leads to high manufacturing risks such as chemical mechanical polishing dishing or erosion. Therefore, there is a need for an integrated circuit structure and a method of forming the same to solve the above-mentioned problems.
Disclosure of Invention
The method for forming an integrated circuit structure provided by an embodiment of the disclosure includes: receiving a semiconductor substrate including an integrated circuit cell and a well tap cell surrounding the integrated circuit cell; forming a plurality of first fin-shaped active regions in the well connection unit and forming a plurality of second fin-shaped active regions in the integrated circuit unit; forming a hard mask in the well connecting unit, wherein the hard mask comprises a plurality of openings, and the openings define a plurality of first source/drain regions on a first fin-shaped active region of the well connecting unit; forming a plurality of gate stacks on a second fin-shaped active region in the integrated circuit unit without forming the gate stacks in the well connecting unit, wherein the gate stacks define a plurality of second source/drain regions on the second fin-shaped active region; epitaxially growing a plurality of first source/drain structures in the first source/drain regions, and using a hard mask to limit epitaxial growth; and forming a plurality of contacts landed on the first source/drain structure in the well connecting unit.
The method for forming an integrated circuit structure provided by an embodiment of the disclosure includes: receiving a semiconductor substrate including an integrated circuit unit and a well connection unit surrounding the integrated circuit unit; forming a first fin-shaped active region in the well connection unit and forming a second fin-shaped active region in the integrated circuit unit; forming a hard mask in the well connecting unit, wherein the hard mask comprises an opening, and the opening defines a first source/drain region on a first fin-shaped active region of the well connecting unit; forming a gate stack on a second fin-shaped active region in the integrated circuit unit, the gate stack defining a second source/drain region on the second fin-shaped active region; using the hard mask and the gate stack together as an etching mask and performing an etching process to recess the first source/drain region and the second source/drain region; epitaxially growing a first source/drain structure in the first source/drain region and a second source/drain structure in the second source/drain region, and using a hard mask and gate stack to limit the epitaxial growth process; and forming a contact, wherein the contact is landed on the first source/drain structure in the well connecting unit.
An embodiment of the present disclosure provides an integrated circuit structure, including: a semiconductor substrate having an integrated circuit unit and a well connection unit surrounding the integrated circuit unit; a first fin-shaped active region formed in the well connection unit; a second fin-shaped active region formed on the integrated circuit unit; a source/drain structure formed on the first fin-shaped active region; a plurality of gate stacks formed on the second fin-shaped active region; and a contact formed on the source/drain structure, wherein the well connecting unit does not have any gate.
Drawings
FIG. 1 is a top view of an integrated circuit structure, in some embodiments.
Fig. 2A is a partial top view of the integrated circuit structure of fig. 1 in some embodiments.
Fig. 2B is a cross-sectional view of the integrated circuit structure of fig. 2A along dashed line AA' in some embodiments.
Fig. 2C is a cross-sectional view of the integrated circuit structure of fig. 2A along dashed line BB' in some embodiments.
Fig. 2D is a cross-sectional view of the integrated circuit structure of fig. 2A along dashed line BB' in some embodiments.
Figure 3 is a flow diagram of a method of forming an integrated circuit structure, in some embodiments.
Figure 4 is a top view of an integrated circuit structure, in some embodiments.
Fig. 5A is a partial top view of the integrated circuit structure of fig. 4 in some embodiments.
Fig. 5B is a cross-sectional view of the integrated circuit structure of fig. 5A along dashed line AA' in some embodiments.
Fig. 5C is a cross-sectional view of the integrated circuit structure of fig. 5A along dashed line BB' in some embodiments.
Fig. 5D is a cross-sectional view of the integrated circuit structure of fig. 5A along dashed line CC' in some embodiments.
Fig. 5E is a cross-sectional view of the integrated circuit structure of fig. 5A along dashed line DD' in some embodiments.
Fig. 6A, 6B, and 6C are cross-sectional views of gates of integrated circuit structures in some embodiments.
Fig. 7 and 8 are top views of integrated circuits in various embodiments.
Description of reference numerals:
AA ', BB', CC ', DD' dotted line
100. 400 integrated circuit structure
102 integrated circuit unit
104 well connection unit
106. Part 402
202 semiconductor substrate
204 shallow trench isolation structure
206 fin active region
208 gate stack
210 source/drain structure
212 doped well
214 interlayer dielectric layer
216 contact
300 method
302. 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324 steps
502 hard mask
504 edge
602 gate dielectric layer
602A interface layer
602B high-k dielectric material layer
604 grid electrode
604A work function metal layer
604B filled metal
606 Gate spacer
Detailed Description
It is to be understood that the following provides many different embodiments, or examples, for implementing different features of various embodiments. The particular components and arrangements are provided to simplify the present disclosure and not to limit the same. Moreover, the various examples of the present disclosure may be repeated with reference numbers, but such repetition is merely intended to simplify and clarify the description and does not imply that there is a similar correspondence between elements having the same reference numbers in different embodiments and/or arrangements.
Various embodiments of an integrated circuit structure are provided having a plurality of integrated circuit cells surrounded by well-connected cells. For example, the well connecting units surround the integrated circuit units, and the interval of the integrated circuit units is provided with the well connecting units. The integrated circuit unit and the well connection unit share the continuous doping well. The well connecting unit comprises a fin-shaped active region, a source/drain structure and a contact landed on the source/drain structure. The contacts act as pickups and are connected to power lines (e.g., ground lines) that can bias the doped wells to provide reliable, accurate, and consistent device performance for devices in the integrated circuit cell, particularly analog devices. Specifically, the well connecting unit does not have any gate structure, and the source/drain structure is formed by using a hard mask having an opening to define the source/drain region. Source/drain structures are formed in the well connectors by etching and epitaxial growth, and the above process is limited by the hard mask formed in the well connector unit. In some embodiments, the hard mask remains in the final integrated circuit structure. In various embodiments, the integrated circuit cells include analog field effect transistors, digital field effect transistors, static random access memory devices, or other suitable devices.
Fig. 1 is a top view of an integrated circuit structure 100 in various embodiments of the present disclosure. Fig. 2A is a partial top view of an integrated circuit structure 100. Fig. 2B and 2C are cross-sectional views of the integrated circuit structure 100 of fig. 2A along dashed lines AA 'and BB', respectively. In this embodiment, the integrated circuit structure 100 is formed on a fin-shaped active region and includes a fin-shaped field effect transistor. The integrated circuit structure 100 and its method of formation will be described with reference to fig. 1, 2A-2C, and other figures.
In various embodiments, the integrated circuit structure 100 includes a plurality of integrated circuit cells 102 spaced apart from one another by well-connect cells 104. Specifically, well connecting units 104 surround each integrated circuit unit 102, and each integrated circuit unit 102 is separated from other integrated circuit units by well connecting units 104. The integrated circuit cell 102 includes a variety of devices, such as analog finfets, digital finfets, static random access memory devices, other suitable devices, or combinations thereof. The well connect cell 104 is designed to provide a bias voltage to the doped well of the integrated circuit cell 102 to improve circuit performance, such as accuracy. An enlarged view of a portion 106 of the integrated circuit structure 100 is shown in fig. 2A-2C, which will be described in detail below.
As shown in fig. 2A-2C, the integrated circuit structure 100 is formed on a semiconductor substrate 202. The semiconductor substrate 202 comprises silicon. In other embodiments, the semiconductor substrate 202 may include a semiconductor element (e.g., silicon or germanium in a crystalline structure), a semiconductor compound (e.g., silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), or a combination thereof. Possible semiconductor substrates 202 also include silicon-on-insulator substrates. The soi substrate may be fabricated by isolation implantation of oxygen, wafer bonding, and/or other suitable methods.
The integrated circuit structure 100 includes a shallow trench isolation structure 204 formed on a semiconductor substrate 202 and defining a plurality of active regions, such as fin-shaped active regions 206 on the semiconductor substrate 202. The fin-shaped active region 206 is raised above the sti structures 204 to provide multiple surface couplings between the channel and the gate to improve device performance. The shallow trench isolation structure 204 may be formed by a patterning process to form a trench on the semiconductor substrate 202, filling the trench with one or more dielectric materials, and performing a chemical mechanical polishing process. The fin-shaped active region 206 may be formed by epitaxial growth, recessing the sti structures 204, or a combination thereof.
The fin-shaped active regions 206 include fin-shaped active regions extending along a first direction (e.g., X direction) and disposed parallel to each other and located in the integrated circuit unit 102 and the well connecting unit 104. The portion 106 of the integrated circuit structure 100 includes two integrated circuit cells with a region of the well connection unit 104 sandwiched therebetween along the first direction. The area of the well connection unit 104 contacts the edges of the two integrated circuit units 102. In this embodiment, the area of the well connecting unit 104 includes two fin-shaped active regions 206, or alternatively includes three fin-shaped active regions 206 or a single fin-shaped active region 206.
The integrated circuit cell 102 includes a plurality of gate stacks 208 formed on the fin-shaped active region 206. The gate stack 208 has an elongated shape and may be along the second direction (Y direction). The gate stack 208 extends over more than the fin-shaped active region 206 and may extend from one edge of the integrated circuit cell 102 to an edge of the opposite side of the integrated circuit cell 102. Each gate stack 208 includes a gate dielectric layer and a gate overlying the gate dielectric layer. In this embodiment, the gate dielectric layer comprises a high-k dielectric material and the gate comprises a metal or metal alloy.
Integrated circuit cell 102 also includes source/drain structure 210 formed on fin-shaped active region 206. The source/drain structures 210 may be formed by epitaxially growing a semiconductor material, such as silicon, germanium, silicon carbide, or combinations thereof, that is the same as or different from the semiconductor substrate 202. The formation process of the source/drain structure 210 may include etching the source/drain regions to recess them, and epitaxial growth. In the integrated circuit cell 102, the gate stack 208 additionally serves as a barrier to limit etching and epitaxial growth when forming the source/drain structures 210. The gate stacks 208 and the source/drain structures are configured as a plurality of field effect transistors.
Source/drain structures 210 are also formed in the well connecting unit 104. In contrast to the integrated circuit cell 102, the well connection cell 104 does not have any gate stacks. Since the well connecting unit 104 does not have the gate stack, the gate density and the size of the well connecting unit 104 can be reduced, which is beneficial to reducing the chemical mechanical polishing corrosion or dishing effect and increasing the circuit area. In addition, a hard mask is formed on the well connecting unit 104 and has openings defining corresponding source/drain regions. The hard mask may serve as a barrier to limit etching and epitaxial growth processes during formation of the source/drain structures 210 in the well contact 104. The formation process of the hard mask includes deposition, photolithography process, and etching. After the formation of the source/drain structures 210, the hard mask layer may be removed or left in the final structure of the well connecting unit 104, which will be described in further embodiments below. In some embodiments, adjacent source/drain structures 210 are epitaxially grown to merge together to increase contact area and reduce contact resistance, as shown in fig. 2C.
The integrated circuit structure 100 also includes doped wells 212 extending from the integrated circuit cell 102 to the well connection cell 104. The doped well 212 extends continuously from the integrated circuit cell 102 to the well connection cell 104 and also extends to the adjacent integrated circuit cell 102. Specifically, the doped well 212 extends continuously over a plurality of fin-shaped active regions 206, and the fin-shaped active regions 206 have transistor portions under the intervening shallow trench isolation regions 204, as shown in fig. 2C. In this embodiment, the doped wells 212 are disposed such that the integrated circuit cells 102 and the well connecting cells 104 in fig. 2A are formed in the continuous doped well 212. In some embodiments, the doped wells 212 are p-type wells and the field effect transistors in the integrated circuit cells 102 are n-type field effect transistors.
Integrated circuit structure 100 also includes an interlayer dielectric layer 214 formed over fin active region 206 and gate stack 208. The interlayer dielectric 214 is not shown in fig. 2A, so as to illustrate other structures below the interlayer dielectric 214, such as the fin-shaped active region 206 and the gate stack 208. The interlayer dielectric 214 may comprise one or more dielectric materials, such as silicon oxide, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some embodiments, the interlayer dielectric 214 is formed by deposition and chemical mechanical polishing.
The integrated circuit structure 100 also includes various contacts 216 formed on the source drain structure 210. The contact 216 conducts electricity and lands on the source/drain structure 210. In some embodiments, the contact 216 comprises tungsten, nickel, cobalt, ruthenium, copper, other metals or metal alloys, or combinations thereof. The formation process of the contact 216 may include patterning, deposition, and chemical mechanical polishing. In some embodiments, the contact 216 surrounds the source/drain structure 210 to improve contact performance and reduce contact resistance. As shown in fig. 2D. The integrated circuit structure 100 also includes interconnect structures coupled to the contact 216 and the gate stack 208 in the integrated circuit cell 102.
The integrated circuit cell 102 and the well connecting cell 104 share the doping well 212. The contacts 216 in the well connect unit 104 are connected to power lines that may bias the doped wells 212 to provide reliable and consistent device performance of the devices in the integrated circuit unit 102. For example, the contact 216 in the well connecting unit 104 is coupled to ground to bias the doping well 212. By confining the formation (etching and epitaxial growth) of the source/drain structures 210 in the well-tie cells 104 by hard masking rather than dummy gate stacks, the well-tie cells 104 can be brought closer to the integrated circuit cells 102 to increase circuit area and reduce gate density (and thus reduce fabrication risk). This is because the hardmask is a dielectric layer and can be close to the dummy gate stack without being restricted by design rules.
In some embodiments, the field effect transistors in the integrated circuit cells 102 are n-type field effect transistors and the doped wells 212 are p-type doped wells. In some embodiments, the field effect transistors in the integrated circuit cells 102 are p-type field effect transistors, and the doped wells 212 are n-type doped wells. In some embodiments, the integrated circuit structure 100 includes n-type field effect transistors and p-type field effect transistors. n-type field effect transistors are classified as a first set of integrated circuit cells, and p-type field effect transistors are classified as a second set of integrated circuit cells. The first group of integrated circuit cells share a p-type well with a first well connection unit, and the second group of integrated circuit cells share an n-type well with a second well connection unit. The first well connection unit is connected to a first power line (e.g., a first ground line) to bias the p-type well, and the second well connection unit is connected to a second power line (e.g., a high voltage power line) to bias the n-type well.
Figure 3 is a flow diagram of a method 300 of forming an integrated circuit structure (such as the integrated circuit structure 100 described above or the integrated circuit structure 400 described below) in some embodiments. Fig. 4 is a top view of an integrated circuit structure 400. Fig. 5A is a partial top view of an integrated circuit structure 400. Fig. 5B, 5C, 5D, and 5E are cross-sectional views of the integrated circuit structure 400 of fig. 5A along dashed lines AA ', BB', CC ', and DD', respectively. In this embodiment, the integrated circuit structure 400 is formed on a fin-shaped active region and includes a variety of fin-shaped field effect transistors. Similar to the integrated circuit structure 100, the integrated circuit structure 400 also includes a plurality of integrated circuit cells 102 separated by well connection units 104. The description of similar structures will not be repeated. Fig. 5A-5E illustrate only a portion 402 of the integrated circuit structure 400 in some embodiments. The integrated circuit structure 400 and the method 300 will be described in conjunction with fig. 3, 4, 5A-5E, and other figures.
The method 300 begins with step 302 in which an integrated circuit structure 400 is received, the integrated circuit structure having a semiconductor substrate 202, the semiconductor substrate 202 having an area for an integrated circuit cell 102 and an area for a well-connect cell 104. Specifically, the well connection unit 104 surrounds each integrated circuit unit 102. For example, the integrated circuit cells 102 may be arranged in a rectangle, while the well connecting unit 104 includes four regions to surround the integrated circuit cells 102.
The method 300 includes a step 304 to form the shallow trench isolation structure 204. The shallow trench isolation structure 204 may comprise one or more dielectric materials, such as silicon oxide, silicon nitride, fluorinated silicon oxide glass, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some embodiments, the shallow trench isolation structure 204 is formed by etching to form a trench, filling the trench with a dielectric material, and polishing to remove excess dielectric material and planarize the upper surface (e.g., chemical mechanical polishing). One or more etching processes are performed on the semiconductor substrate 202 through the openings of the soft mask or the hard mask. The soft mask may comprise photoresist formed by a photolithography process. The hard mask may be formed by deposition, photolithography, and etching. In various embodiments, the dielectric material is deposited by chemical vapor deposition, high density plasma chemical vapor deposition, sub-pressure chemical vapor deposition, high aspect ratio process, flowable chemical vapor deposition, spin-on process, or a combination thereof.
The method 300 also includes a step 306 of forming the fin-shaped active region 206. Step 306 comprises recessing the sti structures 204 such that the fin-shaped active regions 206 are raised above the sti structures 204. The recessing process may employ one or more etching steps, such as dry etching, wet etching, or a combination thereof, to selectively etch back the sti structures 204. For example, when the shallow trench isolation structure 204 is silicon oxide, the wet etching process may employ hydrofluoric acid as an etchant. The fin-shaped active regions 206 have a shape elongated along the X direction and are spaced apart from each other in the Y direction. In other embodiments, the fin-shaped active region 206 is formed by epitaxial growth, or a combination of recess and epitaxial growth.
The method 300 also includes step 308 to form the doped well 212. The doped well 212 extends continuously from the integrated circuit cell 102 to the well connection cell 104. Furthermore, the doped well 212 is disposed and dimensioned to include the integrated circuit cell 102 and the well connection cell 104 surrounding the integrated circuit cell 102. Specifically, the doped well 212 extends continuously across the plurality of fin-shaped active regions 206, and the fin-shaped active regions 206 have transistor portions under the intermediate shallow trench isolation structures 204, as shown in fig. 5B. The doped well 212 may be formed by an ion implantation process to introduce suitable dopants into the semiconductor substrate 202. In this embodiment, the doped well 212 is a p-type well and the dopant may be boron, while the finfet of the integrated circuit cell 102 in the doped well 212 is an n-type finfet.
The method 300 includes the step of forming the gate stack 208 in the integrated circuit cell 102. The gate stack 208 is formed on the fin-shaped active region 206 in the integrated circuit cell 102, but not in the well connection cell 104. In this embodiment, the gate stack 208 comprises a high-k dielectric material and a metal, which may be formed by a gate post-processing process, such as steps 310-316 described below.
The method 300 includes a step 310 of forming a dummy gate stack (to be replaced with the gate stack 208 in a later stage of fabrication). The dummy gate stack in this stage of fabrication is at the location of gate stack 208 and is not shown in fig. 5A-5E. The dummy gate stack has an elongated shape along the Y-direction. Each dummy gate stack may be located on a plurality of fin-shaped active regions 206. The dummy gate stack may comprise polysilicon and may also comprise a layer of dielectric material (e.g., silicon oxide) sandwiched between the polysilicon and fin-shaped active region 206. The dummy gate stack formation method includes depositing a dummy gate material (e.g., thermal oxidation to form silicon oxide and chemical vapor deposition polysilicon), and patterning the dummy gate material. A gate hard mask may be formed over the dummy gate material and used as an etch mask in forming the dummy gate stack. In some embodiments, the patterning process includes depositing a hard mask, forming a patterned photoresist layer on the hard mask with a photolithography process, using the patterned photoresist layer as an etch mask and etching the hard mask, and using the patterned hard mask as an etch mask and etching the gate material to form the dummy gate stack. After the dummy gate stack is formed, the gate hard mask on the dummy gate stack may be removed, and the removal method may be an etch or a gate replacement process of step 316. The dummy gate stack may also be used to define source/drain regions in the integrated circuit cell 102 and limit the formation of the source/drain structure 210 in the integrated circuit cell 102, such as the dummy gate stack has the function of blocking etching and epitaxial growth when forming the source/drain structure 210.
In step 310, the method of forming a dummy gate stack also includes forming one or more gate spacers on sidewalls of the gate. The gate spacers may be used to offset subsequently formed source/drain structures and may also be used to design or adjust the profile of the source/drain structures. The gate spacers may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The gate spacer may have a plurality of films such as two films (silicon oxide film and silicon nitride film) or three films (silicon oxide film, silicon nitride film, and silicon oxide film). The gate spacers are formed by a process including deposition and anisotropic etching such as dry etching.
The method 300 also includes step 312 of forming a hard mask 502 in the well connecting unit 104 to define source/drain regions and to confine the source/drain structures 210 formed in the well connecting unit 104. As highlighted above, the well connecting unit 104 does not have any gate stacks. Instead, a hard mask 502 is formed to achieve this function. Specifically, a hard mask 502 is formed on fin-shaped active region 206 of well connect cell 104 to limit etching and epitaxial growth when forming source/drain structures 210.
Specifically, in fig. 5A, the integrated circuit cell 102 includes an edge 504 that contacts a region of the well connection cell 104. The region of the well connection unit 104 includes two fin-shaped active regions 206 that are parallel and along the direction of the edge 504. In some embodiments, the area of the well connection unit 104 includes a single fin-shaped active region 206 along the direction of the edge 504, as shown in the top view of fig. 7; or three parallel fin-shaped active regions 206 along the direction of the edge 504, as shown in the top view of fig. 8.
The hard mask 502 includes a portion having an elongated shape along the Y-direction and is aligned with the dummy gate stacks in adjacent integrated circuit cells 102. Each portion of hardmask 502 extends over two fin active regions 206 (as shown in fig. 5A), or three or more fin active regions 206 (as in other embodiments). The gaps between portions of the hard mask 502 may define source/drain regions in the well connecting unit 104. Since the hard mask 502 is a dielectric layer and portions of the hard mask 502 are not gate stacks, the spacing between the dummy gate stack ends and portions of the hard mask 502 is not limited by any design rules. The well connecting unit 104 can be minimized and the gate density of the integrated circuit structure 400 can be reduced.
The hardmask 502 comprises a dielectric material such as an oxide of a semiconductor, a nitride of a semiconductor, an oxynitride of a semiconductor, and/or a carbide of a semiconductor. In one embodiment, the hard mask 502 comprises a silicon oxide film and a silicon nitride film. The hard mask 502 is formed by deposition and patterning processes. In this embodiment, a hard mask 502 is deposited on the semiconductor substrate 202, and the hard mask 502 is patterned by a photolithography and etching process.
The deposition method of the hardmask 502 may be atomic layer deposition, chemical vapor deposition, high density plasma chemical vapor deposition, other suitable deposition processes, or combinations thereof. A patterned photoresist layer is formed on the hard mask by a photolithography process.
A photolithography process is then performed to form a patterned photoresist layer over the hard mask 502. The photoresist layer includes a photosensitive material that produces a property change upon exposure of the photoresist layer to light, such as ultraviolet light, deep ultraviolet light, or extreme ultraviolet light. This property change can be used to selectively remove either exposed portions or unexposed portions of the photoresist layer with a development process. The photolithography process includes spin coating a photoresist layer, soft baking the photoresist layer, aligning the mask, exposing, post-exposure baking, developing the photoresist layer, rinsing, and drying (e.g., hard baking). In other embodiments, maskless lithography, e-beam writing, or ion beam writing may be employed to perform, supplement, or replace the lithography process.
An etching process is then performed on the hard mask 502 through the openings of the patterned photoresist layer to transfer the pattern of the patterned photoresist layer to the hard mask 502. The etching process may comprise wet etching, dry etching, or a combination thereof. The etching process may comprise a plurality of etching steps. For example, the hard mask 502 includes a silicon oxide film and a silicon nitride film. The silicon oxide film may be etched by a dilute hydrofluoric acid solution, and the silicon nitride film may be etched by a phosphoric acid solution. After patterning the hard mask 502 or in other suitable process stages, the patterned photoresist layer may be removed by wet stripping or plasma ashing, etc.
The method 300 continues with forming the source/drain structure 210 using the dummy gate stack in the integrated circuit cell 102 and the hard mask 502 in the well-connect cell 104 to confine the source/drain structure 210 formed in the integrated circuit cell 102 and the source/drain structure 210 formed in the well-connect cell 104, respectively. In this embodiment, the method of forming the source/drain structure includes etching the source/drain region to recess it, and an epitaxial growth process.
The method 300 includes step 314, which performs an etching process to recess the source/drain regions. The etch process may selectively etch fin active region 206. In addition, the dummy gate stack and hard mask 502 act as an etch mask to limit the etching process to the source/drain regions. Specifically, in the integrated circuit cell 102, the dummy gate stack limits the etch process to the source/drain regions. In the well connecting unit 104, the hard mask 502 limits the etching process to the source/drain region. The etching process may include any suitable etching technique, such as dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching). In some embodiments, the etching process includes multiple etching steps with different etch chemistries. Which is designed to etch a substrate to form a trench having a desired recess profile, may be used to improve device performance. In some examples, the semiconductor material of fin active region 206 may be etched using a dry etch process that employs a fluorine-based etch.
Step 316 of method 300 is performed by performing epitaxial growth, optionally by growing a semiconductor material (e.g., silicon or other suitable semiconductor material for stress effects) in the recessed source/drain regions to form source/drain regions 210. Similarly, the dummy gate stack and hard mask 502 also limit epitaxial growth. A dopant species, such as a p-type dopant (e.g., boron or boron difluoride) or an n-type dopant (e.g., phosphorus or arsenic), may be introduced during the epitaxial growth to in-situ dope the source/drain structures 210. If the source/drain structure 210 is not in-situ doped, an implantation process may be performed to introduce a corresponding dopant into the source/drain structure 210. In some embodiments, the source/drain structure 210 for an n-type field effect transistor comprises epitaxially grown silicon carbide or silicon doped with phosphorus. The source/drain structures 210 for p-type field effect transistors comprise epitaxially grown germanium or silicon germanium doped with boron. In some other embodiments, the source/drain structure 210 includes more than one layer of semiconductor material. For example, a silicon germanium layer may be epitaxially grown on the recessed ones of the source/drain regions, followed by an epitaxial growth of a silicon layer on the silicon germanium layer. One or more annealing processes may then be performed to activate the source/drain structure 210. Suitable annealing processes include rapid thermal annealing, laser annealing processes, other suitable annealing techniques, or combinations thereof. In this embodiment, the source/drain structures 210 formed on the two fin-shaped active regions 206 in the well connecting unit 104 merge to increase the contact area and reduce the contact resistance, as shown in fig. 5C.
Step 318 of method 300 forms an interlayer dielectric 214 on semiconductor substrate 202 to cover fin active region 206 and source/drain structure 210. The interlayer dielectric 214 surrounds the dummy gate stack, allowing the dummy gate stack to be removed and replaced with the gate stack 208. The interlayer dielectric 214 serves as an insulating layer that supports and isolates conductive lines (e.g., contacts to be formed). The interlayer dielectric 214 may comprise any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the step of forming the interlayer dielectric 214 includes a deposition process and chemical mechanical polishing to provide a planarized upper surface. In some embodiments, step 318 additionally comprises forming an etch stop layer below the interlayer dielectric layer 214. The etch stop layer is of a different composition than the interlevel dielectric layer 214 to provide etch selectivity and to stop the etch process used to form the contacts.
The method 300 continues with a step 320 in which a gate replacement process is performed to replace the dummy gate stack with the gate stack 208, which has a high-k dielectric material and metal. The gate replacement process includes an etch process to remove the dummy gate stack, a deposition process to deposit gate material (e.g., high-k dielectric material and metal), and chemical mechanical polishing to remove excess gate material and planarize the upper surface. In various embodiments, the gate stack 208 is also described below with reference to fig. 6A-6C, which are cross-sectional views of the gate stack 208.
The gate stack 208 includes a gate dielectric layer 602, a gate 604 over the gate dielectric layer 602, and a gate spacer 606 on sidewalls of the gate 604. In various embodiments, gate dielectric layer 602 may comprise a metal oxide (such as lanthanum oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanate, barium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, barium strontium titanate, or aluminum oxide), a metal nitride, silicon nitride, an oxynitride (such as silicon oxynitride), or other suitable dielectric material. Gate 604 may comprise titanium, silver, aluminum, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, copper, tungsten, or any suitable material. The gate spacers 606 may comprise silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof.
Step 310 of forming the dummy gate stack forms gate spacers 606. A gate dielectric layer 602 may be formed in step 310 and remain as a component of the gate stack 208, as shown in fig. 6A. The gate dielectric layer 602 may comprise two films, such as an interfacial layer 602A and a high-k dielectric material layer 602B, as shown in fig. 6B. In other embodiments, the gate dielectric layer 602 and the gate 604 are formed by the gate replacement process of step 320, as shown in fig. 6C. In this case, the high-k dielectric material layer 602B is deposited by atomic layer deposition, and thus has a U-shape. In other embodiments, the gate 604 may comprise multiple layers, such as a workfunction metal layer 604A and a fill metal 604B, and may additionally comprise other films, such as a capping layer.
In various embodiments, the interfacial layer 602A may comprise silicon oxide, silicon nitride, silicon oxynitride, and/or other suitable materials. The deposition method of the interface layer 602A may be a suitable method such as atomic layer deposition, chemical vapor deposition, ozone oxidation, or the like. The high-k dielectric material layer 602B is deposited on the interfacial layer 602A by a suitable technique such as atomic layer deposition, chemical vapor deposition, metal organic chemical vapor deposition, physical vapor deposition, thermal oxidation, combinations thereof, and/or other suitable techniques.
The workfunction adjusting metal layer 604A comprises a conductive layer of a metal or metal alloy having an appropriate workfunction to increase device performance of a corresponding field effect transistor. The p-type and n-type work function metal layers 604A are different from each other and are referred to as n-type and p-type work function metals, respectively. In some embodiments, the n-type workfunction metal comprises tantalum. In other embodiments, the n-type workfunction metal comprises titanium aluminum, titanium aluminum nitride, tungsten nitride, or a combination thereof. In some embodiments, the p-type workfunction metal comprises titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum, or a combination thereof. In various embodiments, the fill metal 604B comprises aluminum, tungsten, copper, other suitable metals, or combinations thereof. The deposition of the workfunction metal layer 604A and the fill metal 604B may be by any suitable deposition technique, such as physical vapor deposition.
Step 322 of method 300 forms contact 216. Contacts 216 land on the respective source/drain structures 210. In particular, in the well-connected cell 104, the contact 216 lands on the source/drain structure 210 and is also connected to the power line to bias the doped region 212 to provide reliable and one-place device performance of the device in the integrated circuit cell 102. The contacts 216 comprise conductive plugs of conductive material, and the conductive material may be tungsten, aluminum alloy, copper, cobalt, other suitable metal/metal alloy, or combinations thereof. In some embodiments, the contact 216 also includes a barrier layer that lines the contact hole to improve material integrity, such as increasing adhesion and reducing diffusion between materials. The barrier layer may comprise a plurality of films. The barrier layer is formed on the sidewall and the bottom surface of the conductive plug. In some embodiments, the barrier layer comprises titanium and titanium nitride (Ti/TiN), tantalum and tantalum nitride (Ta/TaN), copper silicide, or other suitable materials. In other embodiments, the contact 216 does not have a barrier layer. In some embodiments, the contact 216 lands on the top surface of the source/drain structure 210, as shown in fig. 5C. In other embodiments, the contact 216 surrounds the source/drain structure 210 as shown in fig. 2D, which may also increase contact area and decrease contact resistance.
Step 322 includes patterning the interlayer dielectric 214 to form contact holes, depositing one or more conductive materials to fill the contact holes, and chemical mechanical polishing. The patterning process for forming the contact holes also includes a photolithography process and an etching process. The patterning process may also employ a hard mask for patterning. Deposition may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable deposition methods.
Other fabrication steps may be performed before, during, or after the steps of the method. Some steps may be changed to others. For example, the method 300 includes forming 324 a multi-level interconnect on the integrated circuit structure 400. The multilevel interconnect includes various conductive structures that may couple various device structures (e.g., the gate stack 208 and the source/drain structure 210) to form functional circuitry. Specifically, the multilevel interconnect includes multiple metal layers to provide horizontal electrical lines and vias to provide vertical electrical lines. The multilevel interconnect also includes a plurality of interlevel dielectric layers that isolate the various conductive structures from each other.
In various embodiments, the conductive structures (e.g., metal lines and vias) of the multilevel interconnect comprise aluminum, copper, aluminum/silicon/copper alloy, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof. The multi-level interconnect may be an aluminum interconnect formed by deposition and etching, or a copper interconnect formed by a damascene process.
Other steps may be used to perform some of the steps. For example, the patterning process may be performed as a double patterning or a multiple patterning process. In some embodiments, prior to filling the contact hole with the conductive material, a silicide may be formed on the source/drain structure 210 to reduce contact resistance. The silicide comprises silicon and a metal, such as titanium silicide, tantalum silicide, nickel silicide, or cobalt silicide. The silicide formation process may be referred to as a salicidation process, which includes metal deposition, annealing to react silicon with the metal, and etching to remove unreacted metal.
Various embodiments of an integrated circuit structure are provided having a plurality of integrated circuit cells surrounded by well-connected cells. For example, the well connecting units surround the integrated circuit units, and the interval of the integrated circuit units is provided with the well connecting units. The integrated circuit unit and the well connection unit share the continuous doping well. The well connecting unit comprises a fin-shaped active region, a source/drain structure and a contact landed on the source/drain structure. The contacts act as pickups and are connected to power lines (e.g., ground lines) that can bias the doped wells to provide reliable, accurate, and consistent device performance to devices in the integrated circuit cell, particularly analog devices. Specifically, the well connecting unit does not have any gate structure, and the source/drain structure is formed by using a hard mask having an opening to define the source/drain region. Source/drain structures are formed in the well connectors by etching and epitaxial growth, and the above process is limited by the hard mask formed in the well connector unit. In some embodiments, the hard mask remains in the final integrated circuit structure. In various embodiments, the integrated circuit cells include analog field effect transistors, digital field effect transistors, static random access memory devices, or other suitable devices. By adopting the disclosed integrated circuit structure and the forming method thereof, the grid density and the size of the well connecting unit can be reduced, which are both beneficial to reducing the chemical mechanical polishing corrosion and the dishing effect and increasing the circuit area.
Some embodiments of the present disclosure therefore provide methods of forming integrated circuits. The method includes receiving a semiconductor substrate including an integrated circuit cell, and a well connection cell surrounding the integrated circuit cell; forming a plurality of first fin-shaped active regions in the well connection unit and forming a plurality of second fin-shaped active regions in the integrated circuit unit; forming a hard mask in the well connecting unit, wherein the hard mask comprises a plurality of openings, and the openings define a plurality of first source/drain regions on a first fin-shaped active region of the well connecting unit; forming a plurality of gate stacks on a second fin-shaped active region in the integrated circuit unit without forming the gate stacks in the well connecting unit, wherein the gate stacks define a plurality of second source/drain regions on the second fin-shaped active region; epitaxially growing a plurality of first source/drain structures in the first source/drain regions, and using a hard mask to limit epitaxial growth; and forming a plurality of contacts landed on the first source/drain structure in the well connecting unit.
In some embodiments, the epitaxial growth process further includes epitaxially growing a second source/drain structure on a second source/drain region of a second fin-shaped active region in the integrated circuit unit, and the gate stack limited epitaxial growth process is employed.
In some embodiments, the method further includes using the hard mask and the gate stack together as an etch mask and performing an etch process to recess the first and second source/drain regions.
In some embodiments, the hard mask includes portions that are respectively aligned with the gate stacks.
In some embodiments, the step of forming the first fin-shaped active region in the well connecting unit includes forming two fin-shaped active regions in parallel.
In some embodiments, the well connection unit includes a region along an edge of the integrated circuit unit; and the two active regions extend in the direction of the edge.
In some embodiments, the step of forming the first fin-shaped active region in the well connecting unit further includes forming three fin-shaped active regions in parallel.
In some embodiments, the step of forming the hard mask includes: forming a dielectric material layer on the fin-shaped active region; forming a patterned photoresist layer on the dielectric material layer by a photolithography process; and etching the dielectric material layer using the patterned photoresist layer as an etch mask.
Some other embodiments of the present disclosure provide methods of forming integrated circuit structures. The method includes receiving a semiconductor substrate including an integrated circuit cell and a well connection cell surrounding the integrated circuit cell; forming a first fin-shaped active region in the well connection unit and forming a second fin-shaped active region in the integrated circuit unit; forming a hard mask in the well connecting unit, wherein the hard mask comprises an opening, and the opening defines a first source/drain region on a first fin-shaped active region of the well connecting unit; forming a gate stack over a second fin-shaped active region in the integrated circuit cell, the gate stack defining a second source/drain region over the second fin-shaped active region; using the hard mask and the gate stack together as an etching mask and performing an etching process to recess the first source/drain region and the second source/drain region; epitaxially growing a first source/drain structure in the first source/drain region and a second source/drain structure in the second source/drain region, and using a hard mask and gate stack to limit the epitaxial growth process; and forming a contact, wherein the contact is landed on the first source/drain structure in the well connecting unit.
In some embodiments, an integrated circuit cell includes an edge along a first direction; the well-connected strap includes a region along the first direction and adjacent to an edge of the integrated circuit unit; and the first fin-shaped active region in the region of the well connection unit comprises two fin-shaped active regions which are parallel and along the first direction.
In some embodiments, the first fin-shaped active region in the region of the well connection unit includes three fin-shaped active regions parallel and along the first direction.
In some embodiments, the hard mask includes portions in the region of the well-connected cells, and the portions of the hard mask are respectively aligned with the gate stacks adjacent to the edges of the integrated circuit.
In some embodiments, portions of the hardmask extend over both fin-shaped active regions.
In some embodiments, the method further comprises forming a doped well that extends continuously from the well-connecting cell to the integrated circuit cell.
Some other embodiments of the present disclosure provide integrated circuit structures. The integrated circuit structure includes a semiconductor substrate having an integrated circuit unit and a well connection unit surrounding the integrated circuit unit; a first fin-shaped active region formed in the well connection unit; a second fin-shaped active region formed on the integrated circuit unit; a source/drain structure formed on the first fin-shaped active region; a plurality of gate stacks formed on the second fin-shaped active region; and a contact formed on the source/drain structure. The well connection unit does not have any gate.
In some embodiments, the integrated circuit structure further comprises a doped well extending continuously from the well-connecting cell to the integrated circuit cell, the integrated circuit cell and the well-connecting cell being located in the doped well, wherein the contact is connected to the power line to bias the doped well to provide a reliable and consistent device performance of the integrated circuit cell.
In some embodiments, the integrated circuit cell includes an edge along a first direction; the well connection unit includes a region along the first direction, and the region is adjacent to an edge of the integrated circuit unit; and a first fin-shaped active region in the region of the well connection unit, including two fin-shaped active regions parallel and along a first direction.
In some embodiments, the integrated circuit structure further includes a hard mask over the first fin-shaped active region and adjacent to the source/drain structure.
In some embodiments, the field effect transistor includes a gate stack adjacent to the integrated circuit cell; and the hard mask comprises parts in the region of the well connecting unit, and the parts of the hard mask respectively extend on the two fin-shaped active regions and are aligned with the gate stacks.
In some embodiments, the field effect transistor is an analog n-type field effect transistor; the doped well is a p-type doped well; and the integrated circuit cell has no hard mask.
The features of the above-described embodiments will facilitate understanding of the present disclosure by those skilled in the art. Those skilled in the art should appreciate that they may readily use the disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that such equivalent substitutions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (1)

1. A method of forming an integrated circuit structure, comprising:
receiving a semiconductor substrate including an integrated circuit unit and a well connecting unit surrounding the integrated circuit unit;
forming a plurality of first fin-shaped active regions in the well connecting unit and forming a plurality of second fin-shaped active regions in the integrated circuit unit;
forming a hard mask in the well connecting unit, wherein the hard mask comprises a plurality of openings, and the openings define a plurality of first source/drain regions on the first fin-shaped active regions of the well connecting unit;
forming a plurality of gate stacks on the second fin-shaped active regions in the integrated circuit unit without forming the gate stacks in the well connecting unit, wherein the gate stacks define a plurality of second source/drain regions on the second fin-shaped active regions;
epitaxially growing a plurality of first source/drain structures in the first source/drain regions, and using the hard mask to limit epitaxial growth; and
forming a plurality of contacts, and landing the contacts on the first source/drain structures in the well connecting unit.
CN201910298757.6A 2018-06-28 2019-04-15 Method for forming integrated circuit structure Pending CN110660737A (en)

Applications Claiming Priority (4)

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US201862691209P 2018-06-28 2018-06-28
US62/691,209 2018-06-28
US16/263,656 2019-01-31
US16/263,656 US10665673B2 (en) 2018-06-28 2019-01-31 Integrated circuit structure with non-gated well tap cell

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CN110660737A true CN110660737A (en) 2020-01-07

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