TW202217979A - Semiconductor device - Google Patents

Abstract

A device includes a semiconductor substrate, a source feature and a drain feature over the semiconductor substrate, a stack of semiconductor layers interposed between the source feature and the drain feature, a gate portion, and an inner spacer of a dielectric material. The gate portion is between two vertically adjacent layers of the stack of semiconductor layers and between the source feature and the drain feature. Moreover, the gate portion has a first sidewall surface and a second sidewall surface opposing the first sidewall surface. The inner spacer is on the first sidewall surface and between the gate portion and the drain feature. The second sidewall surface is in direct contact with the source feature.

Description

semiconductor device

Embodiments of the present invention generally relate to integrated circuits and semiconductor devices and methods of forming the same, and more particularly to vertically stacked horizontally oriented multi-channel transistors.

The electronics industry continues to increase demand for smaller and more complex electronic devices that can simultaneously support a larger and more complex number of functions. In order to meet these demands, a continuing trend in the integrated circuit industry is to manufacture integrated circuits with low cost, high performance, and low power consumption. The primary approach to achieving these goals is to reduce IC size (eg, minimum IC structure size), thereby improving throughput and reducing associated costs. However, the shrinking size also increases the complexity of the integrated circuit manufacturing process. Thus, in order to achieve continued progress in integrated circuit devices and their performance, similar advances in integrated circuit manufacturing processes and technologies are required.

For example, nanochip-based devices have been introduced to increase gate-channel coupling, reduce off-state current, and reduce short-channel effects, thereby improving gate control. Nanosheet-based devices consist of multiple suspended channel layers stacked together to form a gate structure. Nanochip-based devices are compatible with existing complementary MOS processes, allowing them to maintain gate control and mitigate short-channel effects while being substantially scaled down. However, conventional nanochip-based devices may face the problem of current crowding, which can degrade device performance such as operating speed. Therefore, although existing nanosheet-based devices are generally suitable for their development purposes, they cannot meet the needs of every aspect.

An exemplary embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a semiconductor substrate; a source structure and a drain structure on the semiconductor substrate; a semiconductor layer stack sandwiched between the source structure and the drain structure; a gate portion; and an inner spacer of a dielectric material. The gate portion is located between two vertically adjacent layers of the semiconductor layer stack, and between the source structure and the drain structure. In addition, the gate portion has opposing first and second sidewall surfaces. An inner spacer is located on the first sidewall surface and between the gate portion and the drain structure. The second sidewall surface directly contacts the source structure.

An exemplary embodiment of the present invention relates to a method of forming a semiconductor device. The method includes receiving a structure. The structure includes a semiconductor substrate; a stack of a first semiconductor layer and a second semiconductor layer; and a dummy gate structure on the stack. The first semiconductor layer and the second semiconductor layer have different material compositions and are staggered with each other in the stack. methods also include

A first portion of the stack on the source layer of the dummy gate structure is removed to form a source trench, thereby exposing first sidewall surfaces of the stack in the source trench. The method further includes removing a first portion of the first semiconductor layer from the exposed first sidewall surface to form a first gap; and epitaxially growing a source structure in the source trench and the first gap. Additionally, the method includes removing a second portion of the stack on the drain side of the dummy gate structure to form a drain trench, thereby exposing a second sidewall surface of the stack in the drain trench. The method further includes removing a second portion of the first semiconductor layer from the exposed second sidewall surface to form a second gap. Next, an inner spacer is formed in the second gap. The method additionally includes epitaxially growing a drain structure in the drain trench. The method additionally includes removing the dummy gate structure to form a gate opening on the stack; removing a third portion of the first semiconductor layer from the gate opening to form an extended gate opening; forming a gate dielectric layer on the extended in the gate opening; and forming the gate on the gate dielectric layer in the extended gate opening.

An exemplary embodiment of the present invention relates to a method of forming a semiconductor device. The method includes receiving a structure. The structure has a semiconductor substrate and a stack of first and second semiconductor layers on the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have different material compositions and are staggered with each other in the stack. The method also includes patterning the stack to form the fin structure; forming a dummy gate structure on the fin structure; etching source trenches in the stack on the first side of the dummy gate structure; laterally etching the first semiconductor layer to form a first gap; forming a source structure in the source trench and the first gap; etching the drain trench in the stack on the second side of the dummy gate structure, and the second side of the gate structure is The first side is opposite; the first semiconductor layer is laterally etched to form the second gap; the inner spacer is formed in the second gap; the drain structure is formed in the drain trench; the dummy gate structure is removed to form the first gate a gate opening; removing the remaining part of the first semiconductor layer to form a second gate opening; and forming a gate structure in the first gate opening and the second gate opening.

The following detailed description may be used in conjunction with the accompanying drawings to facilitate an understanding of various aspects of the invention. Notably, the various structures are for illustrative purposes only and are not drawn to scale, as is the norm in the industry. Indeed, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of illustration.

The following description provides different embodiments or examples for implementing different structures of the invention. In addition, the same reference numerals may be used repeatedly in various embodiments of the present invention for brevity, but elements with the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same corresponding relationship. The following examples of specific components and arrangements are presented to simplify the present disclosure and not to limit the present disclosure. For example, the description of forming the first member on the second member includes an embodiment in which the two are in direct contact, or an embodiment in which other additional members are spaced between the two without direct contact. Furthermore, the structures of the embodiments of the present invention may be formed on, connected to, and/or coupled to another structure, the structures may directly contact another structure, or additional structures may be formed within the structure and the other structure between structures.

In addition, spatially relative terms such as "below," "below," "under," "above," "upper," or similar terms may be used to simplify the description of an element relative to another element in the figures relation. Spatial relative terms can be extended to elements used in other orientations and are not limited to the orientation shown. Elements can also be rotated 90° or other angles, so the directional term is only used to describe the orientation in the illustration. Further, when a value or a range of values is described with "about," "approximately," or similar terms, it includes +/- 10% of the stated value unless specifically stated otherwise. For example, the term "about 5 nm" includes sizes ranging from 4.5 nm to 5.5 nm, 4 nm to 5 nm, or the like.

Embodiments of the present invention generally relate to integrated circuits and semiconductor devices and methods of forming the same, and more particularly to vertically stacked horizontally oriented multi-channel transistors, such as nanowire transistors or nanochip transistors. These kinds of transistors are sometimes referred to as fully wound gate transistors, multi-bridge channel transistors, or some other name. In embodiments of the present invention, these transistors are generally regarded as nanosheet-based transistors or devices. Nanochip-based devices include multiple suspended channel layers stacked one on top of the other and bonded to gate structures. The channel layer of a nanosheet-based device may comprise any suitable shape and/or arrangement. For example, the channel layer can be one of many shapes, such as wires (or nanowires), sheets (or nanosheets), rods (or nanorods), and/or other suitable shapes. In other words, the term "nanosheet-based device" generally refers to a device having a channel layer of nanowires, nanorods, or any other suitable shape. In addition, the channel layer of the nanosheet-based device can be bonded to a single continuous gate structure or multiple gate structures. The channel layer can be connected to a pair of source/drain structures so that charge carriers can flow from the source region through the channel layer to the drain region during operation (eg, when a transistor is turned on). In some embodiments, inner spacers may be formed between the source structure and the gate structure, and between the drain structure and the gate structure. However, this setup inevitably faces the problem of current crowding. Current crowding refers to the inhomogeneous distribution of current density throughout a conductor or semiconductor (such as the channel layer and epitaxial structure of nanosheet-based transistors). This non-uniform phase distribution increases local resistance, ultimately degrading device performance. To sum up, the method provided by the embodiments of the present invention can form asymmetrically disposed source and drain sides to alleviate this effect. Therefore, the performance can be improved. The nanosheet-based device described herein may be a complementary MOS device, a p-type MOS device, or an n-type MOS device. Those of ordinary skill in the art will understand that embodiments of the present invention are beneficial to other example semiconductor devices. For example, the embodiments of the present invention are beneficial to other types of MOSFETs, such as planar MOSFETs, fin-shaped field effect transistors, or other multi-gate field effect transistors.

FIG. 1 is a flowchart of a method 100 of fabricating a nanochip-based device 200 in various embodiments of the present invention. 2A is a top view (in the X-Y plane) of a nanosheet-based device 200 in a fabrication stage according to an embodiment of the present invention. FIGS. 2B , 2C to 18C, and 2D to 18D show the nanosheet-based device 200 in various fabrication stages according to some embodiments of the present invention, respectively along the line BB′, CC′, and a cross-sectional view of D-D' (in the Y-Z plane or the X-Z plane).

As shown in steps 102 to 104 of FIG. 1 and FIGS. 2A to 2D , a semiconductor structure such as device 200 is received. A semiconductor structure such as device 200 includes a substrate 202 of semiconductor. In one embodiment, the semiconductor substrate 202 includes a semiconductor material such as base silicon. Substrate 202 may instead or additionally comprise another semiconductor elemental material (eg, germanium), semiconductor compounds (eg, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide), semiconductor Alloys (eg, germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide), or combinations thereof. The substrate 202 can be changed to a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The fabrication method of the semiconductor-on-insulator substrate may be separated oxygen implantation, wafer bonding, and/or other suitable methods. The substrate 202 may include various doped regions, depending on the design requirements of the device 200 . The doped regions may be p-type doped regions configured for n-type transistors (later referred to as p-type wells), or n-type doped regions configured for p-type transistors (later referred to as n-type wells) ). The n-type doped region can be doped with n-type dopants such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-type dopant region can be doped with p-type dopants such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the substrate 202 includes doped regions formed by a combination of p-type dopants and n-type dopants. For example, various doped regions may be formed directly on and/or in substrate 202 to provide p-well structures, n-well structures, dual-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and/or other suitable doping processes may be performed to form various doped regions.

A semiconductor layer stack 205 is formed on the substrate 202 and includes a staggered stack of semiconductor layers 210 and 215 perpendicularly (eg, along the Z-direction) from the surface of the substrate 202 . In one embodiment, the semiconductor layer 210 and the semiconductor layer 215 are epitaxially grown in a staggered manner. For example, the first layer of the epitaxially grown semiconductor layer 210 is on the substrate 202 , the first layer of the epitaxially grown semiconductor layer 215 is on the first layer of the semiconductor layer 210 , and the second layer of the epitaxially grown semiconductor layer 210 on the first layer of the semiconductor layer 215 , and so on until the semiconductor layer stack 205 has the desired number of semiconductor layers 210 and semiconductor layers 215 . In these embodiments, the semiconductor layer 210 and the semiconductor layer 215 can be regarded as epitaxial layers. In one embodiment, the method for epitaxial growth of the semiconductor layer 210 and the semiconductor layer 215 may be a molecular beam epitaxy process, a chemical vapor deposition process, an organic metal chemical vapor deposition process, other suitable epitaxial growth processes, or the above combination.

In one embodiment, the semiconductor layers 210 each have a substantially uniform thickness, and the semiconductor layers 215 each have a substantially uniform thickness. For example, the thickness of the semiconductor layer 210 may be about 4 nm to about 15 nm. If the above thickness is too small, eg, less than 4 nm, the space after removing the semiconductor layer 210 is insufficient to form the gate layer. If the above thickness is too large, eg, greater than 15 nm, the size of the device may increase unnecessarily and hinder downsizing efforts. For example, the thickness of the semiconductor layer 215 may be about 3 nm to about 15 nm. If the above-mentioned thickness is too small, eg, less than 3 nm, the resistance of the device is large and the performance is degraded. If the above thickness is too large, eg, greater than 15 nm, the gate control of the middle portion of the channel layer may be too weak to ensure consistent performance.

The composition of the semiconductor layer 210 is different from the composition of the semiconductor layer 215 to achieve etching selectivity in the subsequent process. In one embodiment, the semiconductor layer 210 in the etchant has a first etch rate and the semiconductor layer 215 in the same etchant has a second etch rate. The second etch rate is typically less than the first etch rate. The semiconductor layer 210 and the semiconductor layer 215 include different materials, material compositions, composition atom %, composition wt %, thicknesses, and/or characteristics, so as to be used in the etching process (such as forming a suspended channel layer under the channel region of the device 200 ). the etching process) to achieve the desired etching selectivity. For example, the semiconductor layer 210 of one embodiment includes silicon germanium, and the semiconductor layer 215 includes silicon. The composition of semiconductor layer 215 is suitable to provide a channel region for device 200 . Semiconductor layers 210 and 215 of embodiments of the present invention may comprise any combination of semiconductor materials that provide desired etch selectivity, etch rate variance, and/or desired performance characteristics (eg, current-maximizing materials) , which may comprise any of the semiconductor materials described herein.

As described below, semiconductor layer 215 or a portion thereof forms a channel region of device 200 . In one embodiment, the semiconductor layer stack 205 includes four semiconductor layers 210 and four semiconductor layers 215 arranged to form four semiconductor layer pairs on the substrate 202, with each semiconductor layer pair having an individual semiconductor layer 210 and an individual semiconductor layer pair. the semiconductor layer 215. After subsequent processing, this setup may allow device 200 to have four channels. However, the semiconductor layer stack 205 in the embodiment of the present invention includes more or less semiconductor layers, depending on the number of channels required by the device 200 (eg, a nanochip-based transistor) and/or the design requirements of the device 200 . . For example, the semiconductor layer stack 205 may include two to ten semiconductor layers 210 and two to ten semiconductor layers 215 .

The semiconductor layer stack 205 is patterned to form fins 218A and 218B (also referred to as fin structures, fin cells, or the like). Fins 218A and 218B include a portion of a substrate (eg, a portion of substrate 202 ) and a portion of the semiconductor layer stack (eg, a remaining portion of semiconductor layer stack 205 containing semiconductor layers 210 and 215 ). The extending directions of the fins 218A and 218B are substantially parallel to each other along the Y direction, and have a length defined in the Y direction, a width defined in the X direction, and a height defined in the Z direction. In one embodiment, the widths of fins 218A and 218B are about 5 nm to about 80 nm. If the width of the fins is too small, eg, less than 5 nm, the space on the fins to form the device structure is insufficient. If the fin width is too large, eg, greater than 80 nm, the additional advantage provided does not justify the increase in die footprint.

In some embodiments, lithography and/or etching processes are performed to pattern semiconductor layer stack 205, and fins 218A and 218B can be formed. The lithography process may include forming a photoresist layer on the semiconductor layer stack 205 (eg, spin coating), performing a pre-exposure bake process, an exposure process using a mask, a post-exposure bake process, and a development process. During the exposure process, the photoresist layer is exposed to radiation energy such as ultraviolet light, deep ultraviolet light, or extreme ultraviolet light, wherein the photomask can block, penetrate, and/or reflect the radiation to the photoresist layer, depending on the light of the photomask Depending on the pattern and/or mask type (eg, binary mask, phase-shift mask, or EUV mask), an image (corresponding to the mask pattern) is projected onto the photoresist layer. Since the photoresist layer is sensitive to ray energy, the exposed part of the photoresist layer can be chemically changed, and the exposed or unexposed part of the photoresist layer can be dissolved during the development process (depending on the characteristics of the photoresist layer and the development used in the development process). depending on the properties of the solution). After development, the patterned photoresist layer includes a photoresist pattern to correspond to the photomask. The etching process uses the patterned photoresist layer as an etching mask to remove portions of the semiconductor layer stack 205 . In one embodiment, the patterned photoresist layer is formed over the hard mask layer on the semiconductor layer stack 205, the first etching process removes portions of the hard mask layer to form the patterned hard mask layer, and The second etch process uses the patterned hard mask layer as an etch mask to remove portions of the semiconductor layer stack 205 . The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In one embodiment, the etching process is a reactive ion etching process. For example, the patterned photoresist layer may be removed after the etching process (some embodiments may also remove the hard mask layer), and the removal method may be a photoresist strip process or other suitable process. The formation method of the fins 218A and 218B can be changed to a multi-patterning process, such as a double-patterning lithography process (such as a lithography-etch-lithography-etch process, a self-aligned double-patterning process, the spacer is a dielectric Layer self-aligned double patterning process, other double patterning process, or a combination of the above), triple patterning process (such as lithography-etch-lithography-etch-lithography-etch process, self-aligned triple patterning process chemical process, other triple patterning process, or a combination of the above), other multi-patterning process (such as a self-aligned quadruple patterning process), or a combination of the above. In one embodiment, the method of patterning the semiconductor layer stack 205 may implement directional self-assembly techniques. Additionally, the exposure process of some embodiments may implement maskless lithography, e-beam writing, and/or ion beam writing to pattern the photoresist layer.

Isolation structures 230 are formed on or in substrate 202 to isolate various regions, such as various device regions of device 200 . For example, isolation structure 230 surrounds the bottoms of fins 218A and 218B, so isolation structure 230 isolates and separates fins 218A and 218B from each other. In one embodiment, the isolation structure 230 surrounds the substrate portion of the fins 218A and 218B and partially surrounds the semiconductor layer stack portion of the fins 218A and 218B (eg, a portion of the bottommost semiconductor layer 210 ). However, embodiments of the present invention may implement different arrangements of the isolation structure 230 relative to the fins 218A and 218B. The isolation structure 230 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (eg, containing silicon, oxygen, nitrogen, carbon, or other suitable isolation compositions), or a combination thereof. The isolation structures 230 may include different structures, such as shallow trench isolation structures, deep trench isolation structures, and/or localized silicon oxide structures. For example, isolation structures 230 may include shallow trench isolation structures that may define and electrically isolate fins 218A and 218B from other active device regions (eg, fins) and/or passive device regions. The shallow trench isolation structure can be formed by etching trenches in the substrate 202 and/or the semiconductor layer stack 205 (eg, using a dry etching process and/or a wet etching process), such as the above steps of patterning the fins 218A and 218B , and fill the trenches with insulating material (eg, using chemical vapor deposition or spin-on glass processes). A chemical mechanical polishing process and/or an etching process may be performed to remove excess insulating material and/or to planarize the upper surface of the isolation structure 230 . In one embodiment, the STI structure may be formed by depositing an insulating material on the substrate 202 after forming the fins 218A and 218B (in some embodiments, an insulating material layer is filled between the fins 218A and 218B). gaps or trenches), and the insulating material layer is etched back to form the isolation structures 230 . In one embodiment, the shallow trench isolation structure includes a multi-layer structure and fills the trenches, such as a silicon nitride-containing layer on a thermal oxide-containing liner layer. In another example, the shallow trench isolation structure includes a dielectric layer on a doped liner layer (eg, borosilicate glass or phosphosilicate glass). In other examples, the shallow trench isolation structure includes a base dielectric layer on the pad dielectric layer, and the materials of the base dielectric layer and the pad dielectric layer are determined according to design requirements.

As shown in step 106 of FIG. 1 , FIGS. 3C and 3D , and FIGS. 4C and 4D , a gate stack 240 is formed on portions of the fins 218A and 218B and the isolation structure 230 . As in step 122 of FIG. 1 described in detail later, the gate stack 240 will be removed later, and thus can be regarded as a dummy gate stack 240 . In the embodiment shown in FIGS. 3C and 3D , a layer 238 of a suitable dielectric material may be formed over the fins 218A and 218B and the isolation structure 230 . The dielectric material layer 238 includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. High dielectric constant dielectric materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide, and other suitable high dielectric constant materials. Dielectric material, or a combination of the above. In one embodiment, the dielectric material layer 238 includes an interface layer (eg, silicon oxide) sandwiched between the fins 218A and 218B, and a high-k dielectric layer is located on the interface layer.

Next, a suitable dummy gate material layer 235 is formed on the dielectric material layer 238 . For example, the dummy gate material layer 235 may include polysilicon. In one embodiment, the hard mask material layer 232 is formed on the dummy gate material layer 235 . For example, the hard mask material layer 232 may include silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, spin-on glass, low-k films, tetraethoxy Silane oxides, plasma assisted chemical vapor deposition oxides, oxides formed by high aspect ratio processes, other suitable materials, and/or combinations thereof. In addition, various other layers such as capping layers, interface layers, diffusion layers, barrier layers, hardmask layers, or combinations thereof may be formed under, between, or over the various layers described herein.

The formation methods of the dielectric material layer 238, the dummy gate material layer 235, and the hard mask material layer 232 can be deposition process, lithography process, etching process, other suitable processes, or a combination thereof. Deposition process can include chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, organometallic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition , low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, electroplating, other suitable methods, or a combination of the above.

As shown in FIGS. 4C and 4D , lithography patterning and etching processes are then performed to pattern various layers, and a dummy gate stack 240 can be formed. For example, dielectric material layer 238 , dummy gate material layer 235 , and hard mask material layer 232 may each be patterned to form dummy gate stack 240 . The lithography patterning process may include coating photoresist (eg spin coating), soft bake, aligning mask, exposure, post exposure bake, developing photoresist, rinsing, drying (eg hard bake), other suitable lithography process, or a combination of the above. The etching process may include a dry etching process, a wet etching process, other etching methods, or a combination thereof. The lengthwise extension of the dummy gate stack 240 is different from (eg, perpendicular to) the lengthwise direction of the fins 218A and 218B. For example, the extension directions of the dummy gate stacks 240 are substantially parallel to each other along the X direction, the length is defined in the X direction, the width is defined in the Y direction, and the height is defined in the Z direction. Dummy gate stack 240 is located on portions of fins 218A and 218B (eg, covering the top and sidewall surfaces of fins 218A and 218B), and defines source regions 202A, drain regions 202B, and source regions and the channel region 202C between the drain region. The dummy gate stacks 240 are located on the upper surfaces (in the Y-Z plane) of the respective channel regions 202C of the fins 218A and 218B such that the dummy gate stacks 240 are sandwiched between the respective source regions 202A and drain regions 202B between. In one embodiment, the width of the dummy gate stack 240 along the Y direction can define the gate length of the subsequently formed metal clipping structure.

As shown in FIGS. 5C and 5D , gate spacer layers 254 are formed in any suitable process to be adjacent to respective dummy gate stacks 240 (eg, along the sidewalls and/or on top of respective dummy gate stacks 240 ) surface). The gate spacer layer 254 is then processed into gate spacers, as described below. The gate spacer layer 254 includes a dielectric material. The dielectric material may comprise silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, or oxycarbonitride silicon. For example, a dielectric layer containing silicon and nitrogen (eg, silicon nitride) may be deposited over dummy gate stack 240 to form gate spacer layer 254 . In one embodiment, the gate spacer layer 254 may include a multi-layer structure, such as a first dielectric layer containing silicon nitride and a second dielectric layer containing silicon oxide. In one embodiment, sets of spacer layers such as seal spacer layers, offset spacer layers, sacrificial spacer layers, dummy spacer layers, and/or main spacer layers may be formed to stack with dummy gates 240 adjacent. In these embodiments, sets of spacer layers may include materials of different etch rates. For example, a first dielectric layer containing silicon and oxygen (eg, silicon oxide) can be deposited and etched to form a first set of spacers adjacent to dummy gate stack 240, and silicon and nitrogen containing (eg, silicon oxide) can be deposited. silicon nitride) to form a second set of spacers adjacent to the first set of spacers. Additionally, a mask layer 252 may be formed on the gate spacer layer 254 . In some embodiments, the mask layer 252 may be conformally formed. Mask layer 252 may be of any suitable etch mask layer material. In one embodiment, the mask layer 252 may be omitted.

As shown in step 108 of FIG. 1 and FIGS. 6C and 6D , a mask layer 262 is formed on the mask layer 252 to cover at least the drain regions 202B of the fins 218A and 218B. At the same time, the mask 262 may expose the source region 202A. Mask layer 262 may comprise any suitable material and may be formed by any suitable method. For example, mask layer 262 may be a photoresist layer of any suitable photoresist material. In one embodiment, the mask layer 252 may be patterned through the openings of the mask layer 262 . For example, the mask layer 252 in the source region 202A may be removed by etching during the patterning process. The patterned mask layer 252 can then serve as an etch mask for etching the source trenches.

The exposed source regions 202A of fins 218A and 218B (eg, source regions 202A uncovered by etched mask layer 252 ) are at least partially removed to form source trenches 258A (eg, recesses). As described above, the fins 218A and 218B include the semiconductor layer stack portion and the substrate portion. Source trench 258A can be viewed as an opening in semiconductor layer stack 205 and can extend into substrate 202 . For example, the etching process can completely remove the semiconductor layer stack 205 in the source region 202A of the fin 218A and further etch into the substrate 202 such that the lower surface of the source trench 258A extends below the substrate 202 upper surface. For another example, the step of forming source trench 258A removes semiconductor layer stack 205 in source region 202A, but does not etch substrate 202 . In summary, the lower surface of the source trench 258A is defined by the substrate 202 . For another example, the etching process may remove some, but not all, of the semiconductor layer stack 205 such that the source trench 258A in the source region 202A has a bottom defined by the semiconductor layer 210, the semiconductor layer 215, or portions thereof.

The process of forming the source trench causes each of the semiconductor layers 210 to have sidewall surfaces 294A and each of the semiconductor layers 215 to have sidewall surfaces 295A. In one embodiment, sidewall surface 294A is aligned with sidewall surface 295A. The etching process for forming the source trench 258A may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In one embodiment, the etching process is a multi-step etching process. For example, the etch process may be interleaved with an etchant to separate and alternately remove semiconductor layer 210 and semiconductor layer 215 . In one embodiment, the parameters of the etching process are set to selectively etch the semiconductor layer stack 205 and minimize the etching of the dummy gate stack 240 , the gate spacer 254 , and the isolation structure 230 . In addition, the source trench formation process also removes portions of the gate spacer layer 254 . The remaining portion of the gate spacer layer 254 is converted into the gate spacer 254 for the dummy gate stack 240 .

As shown in step 110 of FIG. 1 and FIGS. 7C and 7D , the end portions of the semiconductor layers 210 between the end portions of the semiconductor layers 215 are removed using a suitable removal process to form gaps 253A between the vertically adjacent semiconductor layers 215 . between the end parts. For example, a lateral etch process may be performed to selectively etch the semiconductor layer 210 exposed in the source trench 258A along the Y direction with minimal or no etching of the semiconductor layer 215 . In summary, the gap 253A is formed between the semiconductor layers 215 and between the semiconductor layer 215 and the substrate 202 . In one embodiment, the etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. Gaps 253A and source trenches 258A may together form extended source trenches 264A. The etched semiconductor layers 210 each have sidewall surfaces 296A exposed in the gaps 253A. As described above, since the semiconductor layer 215 has better etch resistance to the etching process, the semiconductor layer 215 is minimally etched or not etched. The etched semiconductor layers 215 thus each have the same sidewall surfaces 295A, as before the lateral etching process. Sidewall surface 296A and sidewall surface 295A are offset and misaligned from each other. In addition, the respective upper surface 297A and lower surface 298A of the semiconductor layer 215 are exposed in the extended source trench 264A. These portions of the surface depend, at least in part, on the subsequently formed epitaxial layer profile.

As shown in step 112 of FIG. 1 and FIGS. 8C and 8D, epitaxial source structures 260A are formed in the extended source trenches 264A. For example, semiconductor material may be epitaxially grown from the exposed portion of the substrate 202 and the exposed portion of the semiconductor layer 215 to form the epitaxial source structure 260A in the source region 202A. In one embodiment, the epitaxial source structure 260A includes a plurality of layers. For example, the epitaxial source structure 260A may include an epitaxial source layer 261A overlying the exposed substrate 202 and over the top, bottom, and sidewall surfaces of the exposed portions of the semiconductor layer 215 . The epitaxial source layer 261A at least partially fills the extended source trench 264A. The epitaxial source layer 261A directly contacts the sidewall surface 295A of the semiconductor layer 215 and directly contacts the sidewall surface 296A of the semiconductor layer 210 . As described above, sidewall surfaces 295A and 296A are offset and misaligned from each other. In addition, the epitaxial source layer 261A more directly contacts the upper surface and the lower surface of each semiconductor layer 215 (eg, the upper surface 297A and the lower surface 298A). These interfaces, such as upper surface 297A and lower surface 298A, can serve as additional paths for charge movement in operation and alleviate current crowding problems, as detailed below.

In summary, the interface between the epitaxial source layer 261A and the semiconductor layer stack 205 includes a plurality of vertical (or near-vertical) features (eg, sidewall surfaces 295A and 296A) that are offset and misaligned from each other. The above-mentioned interface also includes a plurality of horizontal (or approximately horizontal) components (eg, the upper surface 297A and the lower surface 298A), the extending direction of which is substantially perpendicular to the sidewall surfaces 295A and 296A. In other words, the interface between the epitaxial source layer 261A and the semiconductor layer stack 205 has one or more portions whose outline is similar to the shape of the letter S. Although the S component in the drawings is in a vertical or horizontal orientation, it can be changed to any orientation.

In one embodiment, the epitaxial source structure 260A may further include an epitaxial source layer 262A grown from the epitaxial source layer 261A. For example, the epitaxial source layer 262A is connected to the two side surfaces of the epitaxial source layer 261A so as to fill the remaining space of the extended source trench 264A. In one embodiment, the upper surface of the epitaxial source layer 262A extends along the upper surface of the epitaxial source layer 261A. Since the epitaxial source layer 262A and the epitaxial source layer 261A share a common interface, the epitaxial source layer 262A may also have two opposite surfaces, each of which has a portion conforming to the shape of the letter "S". In one embodiment, the upper surfaces of the epitaxial source layer 261A and the epitaxial source layer 262A extend higher than the upper surface of the semiconductor layer stack 205 . However, the upper surfaces of the epitaxial source layer 261A and the epitaxial source layer 262A may extend higher or lower than the upper surface of the semiconductor layer stack 205, depending on design requirements.

In one embodiment, the entire profile of the epitaxial source layer 261A may have a uniform or substantially uniform thickness. In summary, the shape of the layer conforms to the surface. Taking FIG. 8C as an example, the epitaxial source layer 261A includes two opposite portions 263a and 263b, each of which extends upward from the substrate 202, and the outlines of the layers each conform to the shape of the letter "S". In some embodiments, the thickness of the epitaxial source layer 261A may be about 2 nm to about 6 nm. If the thickness is too small, eg, less than 2 nm, the protective effect of the epitaxial source layer 261A on the inner layer (eg, the epitaxial source layer 262A described below) may be insufficient. This aspect ratio will be detailed below. On the other hand, the large thickness used for epitaxial source layer 261A necessarily reduces the thickness or volume of epitaxial source layer 262A formed in the same extended source trench 264A. If the thickness is too large, eg, greater than 6 nm, the volume of the epitaxial source layer 262A may be too small. In some embodiments, the epitaxial source layer 262A can serve as a major charge carrier supplier, and has more charge carriers than the epitaxial source layer 261A, or has a carrier mobility greater than that in the source layer 261A child mobility. To sum up, the unnecessarily large thickness of the epitaxial source layer 261A ultimately results in the number or mobility of charge carriers, thereby reducing device performance (eg, operating speed).

In some embodiments, the epitaxial source layer 261A and the semiconductor layer 210 are disposed to achieve etching selectivity during subsequent etching processes. In summary, it may comprise different materials or different material compositions. For example, the semiconductor layer 210 of the embodiment may include silicon germanium, and the epitaxial source layer 261A may include silicon. In some embodiments, epitaxial source layers 261A and 262A form part of a p-type transistor. The presence of the epitaxial source layer 261A dominated by silicon can ensure that the integrity of the epitaxial source structure 260A will not be damaged in the subsequent process. Specifically, the epitaxial source layer 261A is directly formed on or adjacent to the semiconductor layer 210 (eg, only separated by a barrier layer), as described in detail below. In other words, no inner spacer is formed between the semiconductor layer 210 and the epitaxial source layer 261A. To sum up, in the absence of the etching selectivity, the etching process for removing the semiconductor layer 210 (such as the following wire release process, such as step 124 in FIG. 1 ) will unintentionally damage the epitaxy Integrity of the source layer 261A. When the epitaxial source layer 262A includes similar materials, the etching process may further damage the epitaxial source layer 262A.

On the contrary, the etch selectivity between the semiconductor layer 210 and the epitaxial source layer 261A can ensure that these subsequent processes do not etch or minimize the etching of the epitaxial source layer 261A. Furthermore, these etch selectivities allow for more diverse material choices for epitaxial source layer 262A (or other inner epitaxial layers). The thickness (or volume) of the epitaxial source layer 262A is greater than the thickness (or volume) of the epitaxial source layer 261A. The doping amount or dopant mobility of the epitaxial source layer 262A may also be higher than the doping amount or dopant mobility of the epitaxial source layer 261A. In other words, the function of the epitaxial source structure 260A is mainly provided by the epitaxial source layer 262A. In conclusion, the broad material selectivity used for epitaxial source layer 262A facilitates device design and improves device performance (eg, operating speed). For example, silicon germanium is not only a common material for the semiconductor layer 210, but also a common epitaxial source material for p-type transistors because of its high hole mobility. The arrangement described here enables the epitaxial source layer 262A to use SiGe without the risk of damage during the subsequent process of etching SiGe to form the suspended channel layer. Without the above-mentioned etching selectivity, the epitaxial source layer 262A is not selected to have a silicon germanium composition similar to that of the semiconductor layer 210 . This limitation is eliminated because the epitaxial source layer 261A separates the two SiGe layers from each other. Therefore, the etching selectivity between SiGe and Si can ensure that the etching process stops at the interface between the semiconductor layer 210 and the epitaxial source layer 261A, and does not reach the epitaxial source layer 262A.

In this embodiment, epitaxial source layer 261A includes silicon, and epitaxial source layer 262A includes silicon germanium. In other words, there is etching selectivity between the epitaxial source layer 261A and the epitaxial source layer 262A. However, in other embodiments, the epitaxial source layer 261A and the epitaxial source layer 262A may include the same or similar materials, and may not have etch selectivity therebetween. For example, the semiconductor layer 210 of some embodiments may include silicon, while the epitaxial source layer 261A and the epitaxial source layer 262A may include silicon germanium.

In some embodiments, epitaxial source layers 261A and 262A may form part of an n-type transistor. Similar to the p-type transistor, the etch selectivity between the epitaxial source layer 261A and the semiconductor layer 210 can ensure the integrity of the epitaxial source layer. In some embodiments, the semiconductor layer 210 includes silicon germanium. In these embodiments, both the epitaxial source layer 261A and the epitaxial source layer 262A can include silicon as the epitaxial material. In some other embodiments, the semiconductor layer 210 may comprise silicon. Since silicon is a common epitaxial material for n-type devices, it is sometimes advantageous to provide a silicon-containing epitaxial source layer 262A (eg, the primary charge carrier provider). In these embodiments, the epitaxial source layer 261A may include different materials (eg, silicon germanium) to provide an etch stop mechanism, thereby avoiding damage to the epitaxial source layers 261A and 262A when the semiconductor layer 210 is etched. In other words, there is etching selectivity between the epitaxial source layer 261A and the semiconductor layer 210 , and etching selectivity between the epitaxial source layer 261A and the epitaxial source layer 262A.

The epitaxial source structure 260A (including the epitaxial source layer 261A and the epitaxial source layer 262A) can be deposited using any suitable epitaxial process, such as chemical vapor deposition techniques (eg, vapor epitaxy and/or high vacuum chemical vapor deposition), molecular beam epitaxy, other suitable epitaxial growth processes, or a combination of the above. The epitaxy process may employ gaseous and/or liquid precursors, which may interact with the composition of the substrate 202 and/or the semiconductor layer stack 205 (especially the semiconductor layer 215). In addition, the epitaxial source structure 260A can be doped with p-type dopants or n-type dopants, depending on the type of the transistor and the above selection criteria. For example, in the embodiment described in which the semiconductor layer 210 comprises silicon germanium, the epitaxial source layer 261A for the p-type transistor may be doped with boron, gallium, other p-type dopants, or a combination of the foregoing (such as boron Silicone epitaxial source layer or silicon gallium epitaxial source layer). Meanwhile, the epitaxial source layer 262A may include silicon germanium or germanium, which may be doped with boron, gallium, other p-type dopants, or a combination of the above (eg, silicon germanium boride epitaxial source layer, silicon germanium gallium epitaxial source layer, germanium boride epitaxial source layer, or germanium gallium epitaxial source layer). For another example in which the semiconductor layer 210 contains silicon germanium, the epitaxial source layer 261A and the epitaxial source layer 262A used in the n-type transistor can both contain silicon, and can be doped with carbon, phosphorus, arsenic, and other n-type transistors. Dopants, or a combination of the above, to form an epitaxial source layer of silicon carbide, an epitaxial source layer of silicon phosphide, an epitaxial source layer of silicon arsenide, or an epitaxial source layer of silicon carbon phosphide .

The epitaxial source layers 261A and 262A may contain the same or different dopant concentrations. In one embodiment, the epitaxial source structure 260A (including the epitaxial source layer 261A, the epitaxial source layer 262A, or both) contains materials or dopants that can reach desired levels in the individual channel regions of the device. Tensile stress or compressive stress. In one embodiment, impurities are added to the source material of the epitaxial process during deposition to dope the epitaxial source structure 260A (eg, in-situ doping). In one embodiment, the ion implantation process after the deposition process can dope the epitaxial source structure 260A. In one embodiment, an annealing process (eg, rapid thermal annealing and/or laser annealing) may be performed to activate the dopants in the epitaxial source structure 260A.

As shown in step 114 of FIG. 1 and FIGS. 9C and 9D , a mask layer 252 ′ is formed on the epitaxial source structure 260A, so that the mask layer 252 ′ covers the upper surfaces and gate electrodes of the epitaxial source layers 261A and 262A The upper surface and sidewall surface of the spacer 254 and the upper surface of the hard mask material layer 232 . The mask layer 252' can protect the epitaxial source structure 260A in the subsequent etching process. The method of forming the mask 252' may be any suitable method. In one embodiment, a suitable method is used to remove the remaining portion of the mask layer 252 (see FIG. 8C ), and a redeposition process is used to form the mask layer 252 ′ to cover the exposed upper surface.

A mask layer 266 (eg, a photoresist layer) is formed at least on the source region 202A of the device, eg, on the mask layer 252'. Mask layer 266 is patterned to provide openings to expose drain region 202B. An etching process is then used to form the patterned mask layer 252, and then drain trenches 258B are formed in the drain region 202B. This etching process is similar to the etching process described above in relation to step 108 of FIG. 1 and FIGS. 6C and 6D. To sum up, the drain trench 258B in one embodiment exposes the sidewall surfaces of the semiconductor layers 210 and 215 and extends into the substrate 202 in the drain region 202B.

As shown in step 116 of FIG. 1 and FIGS. 10C and 10D , a lateral etching process removes portions of semiconductor layer 210 to form gaps 253B between end portions of vertically adjacent semiconductor layers 215 . This process is similar to the lateral etching process described above in relation to step 110 of FIG. 1 and FIGS. 7C and 7D. Furthermore, gap 253B is similar to gap 253A described above.

As shown in step 118 of FIG. 1 and FIGS. 11C and 11D, a deposition process is then used to form a layer of spacer material 268 on the exposed surface. For example, spacer material layer 268 is formed on mask layer 252' in source region 202A, on mask layer 252, hard mask material layer 232, and exposed substrate 202, and on the drain on semiconductor layers 210 and 215 in region 202B. Specifically, the spacer material layer 268 is filled between the end portions of the vertically adjacent semiconductor layers 215, and the gap 253B (see FIG. 10C ) between the semiconductor layer 215 and the substrate 202, so that the spacer material layer 268 is in direct contact Sidewall surfaces of the semiconductor layer 210 and upper and lower surfaces of end portions of the semiconductor layer 215 . In one embodiment, the deposition process adopts chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, organometallic chemical vapor deposition, remote plasma chemical vapor deposition, plasma Assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, electroplating, other suitable methods, or a combination thereof. Spacer material layer 268 may partially (some embodiments may fully) fill drain trench 258B. Although the spacer material layer 268 shown in FIG. 11C has a U-shaped profile, it may instead have any suitable profile.

For example, the dielectric material included in the spacer material layer 268 may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or carbon) silicon oxynitride). In one embodiment, the dielectric material includes the low-k dielectric materials described herein. In one embodiment, dopants such as p-type dopants, n-type dopants, or a combination thereof are introduced into the dielectric material such that the spacer material layer 268 comprises the doped dielectric material.

As shown in step 118 of FIG. 1 and FIGS. 12C and 12D , an etch-back process may be employed to remove portions of spacer material layer 268 to form inner spacers 255 . In one embodiment, the semiconductor layer 215 , the dummy gate stack 240 , and the gate spacer 254 may be etched back with minimal or no etching of the spacer material layer 268 . In one embodiment, the spacer material layer 268 is completely removed outside the gap 253B to expose the upper surfaces of the hard mask material layer 232 and the gate spacer layer 254 , the upper surface of the thinned mask layer 252 and the sidewall surfaces, and sidewall surfaces of the semiconductor layer 215 . In addition, the exposed sidewall surfaces of the inner spacers 255 are aligned with the sidewall surfaces of the semiconductor layer 215 to form continuous and substantially flat sidewall surfaces. In one embodiment, the material of the spacer material layer (and the inner spacer 255 ) is different from the material of the semiconductor layer 215 and the gate spacer 254 , so as to achieve the required etch selectivity during the etch-back process. In one embodiment, the inner base spacer 255 can protect the epitaxial drain structure 260B ( FIG. 13C ) during the subsequent channel release process, and can also be used to reduce parasitic capacitance. The thickness of the inner spacer 255 along the Z direction greatly depends on the thickness of the semiconductor layer 210 . In summary, the thickness of the inner spacer 255 may be about 3 nm to about 15 nm. Also, the width of the inner spacer 255 along the Y direction may be about 2 nm to about 10 nm. If the width is too small, eg, less than 2 nm, the inner spacer 255 is insufficient to protect the epitaxial drain structure 260B in the subsequent etching process, and the effect of reducing the parasitic capacitance of the inner spacer 255 may be reduced. If the width is too large, eg, greater than 10 nm, the additional benefit is not worth the extra die pins it requires.

As shown in step 120 of FIG. 1 and FIGS. 13C and 13D, epitaxial drain structures 260B are formed in drain trenches 258B. The method for forming the epitaxial drain structure 260B is generally similar to the method for forming the epitaxial source structure 260A described above, as shown in step 112 of FIG. 1 and FIGS. 8C and 8D . The epitaxial drain structure 260B is different from the epitaxial source structure 260A, and a portion of the epitaxial drain structure 260B does not interface with the semiconductor layer 210 . On the contrary, the inner spacer 255 is sandwiched between the semiconductor layer 210 and the sidewall surface of the epitaxial drain structure 260B. In one embodiment, the epitaxial drain structures 260B each comprise multiple layers. Taking FIG. 13C as an example, the epitaxial drain structure 260B includes an epitaxial drain layer 261B and an epitaxial drain layer 262B. The epitaxial drain layer 261B directly interfaces with the inner spacer 255 and the semiconductor layer 215 . The epitaxial drain layer 262B is located between and above the two side components of the epitaxial drain layer 261B. As described above, the sidewall surfaces of the semiconductor layer 215 and the inner spacer 255 are aligned with each other to form continuous and substantially flat sidewall surfaces. To sum up, the epitaxial drain layer 261B has a continuous and substantially flat sidewall surface, such as a continuous and flat interface with the semiconductor layer 215 and the inner spacer 255 . In one embodiment, the epitaxial drain layer 261B is a compliant layer. In other words, the outline of the epitaxial drain layer 261B has a uniform thickness. To sum up, the epitaxial drain layer 262B can also have substantially flat sidewall surfaces. In addition, the epitaxial drain layer 262B has a hexagonal profile in the X-Z plane, as shown in FIG. 13D.

In one embodiment, the upper surfaces of the epitaxial drain layer 261B and the epitaxial drain layer 262B extend along the upper surface of the semiconductor layer stack 205 . However, the upper surfaces of the epitaxial drain layer 261B and the epitaxial drain layer 262B may be higher or lower than the upper surface of the semiconductor layer stack 205, depending on design requirements. The material of the epitaxial drain layer 261B may be similar to the material of the epitaxial source layer 261A or the epitaxial source layer 262A. The material contained in the epitaxial drain layer may also be similar to the epitaxial source layer 261A or the epitaxial source layer 262A. In other words, similar to the epitaxial source layers 261A and 262A, the material used for the epitaxial drain layer 261B or 262B is not limited. This is because the protection scheme of protecting the epitaxial source structure can be satisfied by using the inner spacer 255 . To sum up, the choice of materials for the epitaxial drain layer is wide. In some embodiments, epitaxial drain layers 261B and 262B may comprise the same or similar materials. The method for depositing the epitaxial drain layers 261B and 262B may be similar to the method for depositing the epitaxial source structure 260A described above.

In addition, the epitaxial drain structure 260B (including the epitaxial drain layer 261B and the epitaxial drain layer 262B) can be doped with n-type or p-type dopants. For example, the epitaxial drain layers 261B and 262B for n-type transistors may comprise silicon, and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination of the above (such as silicon carbide epitaxial drains) layer, a silicon phosphide epitaxial drain layer, a silicon arsenide epitaxial drain layer, or a silicon carbon phosphide epitaxial drain layer). In another example, the epitaxial drain layers 261B and 262B for p-type transistors may include silicon germanium, and may be doped with boron, gallium, other p-type dopants, or a combination of the above (eg, silicon germanium boride epitaxy) drain layer or silicon germanium gallium epitaxial drain layer). The epitaxial drain layers 261B and 262B may contain the same or different dopant concentrations. In some embodiments, the epitaxial drain structure 260B ester includes a layer of epitaxial material. In one embodiment, the epitaxial source structure 260A includes materials or dopants that can reach the desired tensile or compressive stress in the individual channel regions of the device. After the epitaxial drain structure 260B is formed, the mask layers 252 and 252' may be removed by any suitable method to expose the upper surfaces of the epitaxial source structure 260A and the epitaxial drain structure 260B and the sidewalls of the gate spacer 254 .

As shown in step 122 of FIG. 1 and FIGS. 14C and 14D, a contact etch stop layer 270 is formed on the sidewall surface of the gate gap 254 and the isolation structure 230, and covers the epitaxial source structure 260A and the epitaxial drain structure 260B surface. In one embodiment, the contact etch stop layer 270 directly contacts the top and side surfaces of the epitaxial source layer 262A and the epitaxial drain layer 262B. Contact etch stop layer 270 may comprise any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or combinations thereof. In one embodiment, the thickness of the contact etch stop layer is about 1 nm to about 10 nm. If the thickness is too small, eg, less than 1 nm, the reliability of the protective effect of the contact etching stop layer during the etching process may be deteriorated. If the thickness is too large, eg, greater than 10 nm, it may occupy the space used to form the contact structure, resulting in increased contact resistance.

Next, an interlayer dielectric layer 272 is formed on the contact etch stop layer, and the deposition process can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, metal organic chemical vapor deposition, Remote plasma chemical vapor deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, electroplating, other suitable methods, or a combination thereof. An interlayer dielectric layer 272 is deposited between adjacent gate structures 250 . In one embodiment, the formation method of the interlayer dielectric layer 272 is a flowable chemical vapor deposition process, which may include depositing a flowable material (eg, a liquid compound) on the device 200 with suitable techniques such as thermal annealing and /or UV treatment to convert flowable materials into solid materials. For example, the interlayer dielectric layer 272 includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, oxides of tetraethoxysilane, phosphosilicate glass, borophosphosilicate glass, low dielectric A dielectric material with an electrical constant, other suitable dielectric materials, or a combination of the above. Exemplary low-k dielectric materials include fluorosilicate glass, silicon oxycarbide, Black Diamond® (available from Applied Materials, Santa Clara, CA, USA), xerogels, aerosols, amorphous carbon fluoride , with p-xylene, benzocyclobutene, SiLK (available from Dow Chemical in Midland, Michigan, USA), polyimide, other low dielectric constant dielectric materials, or a combination of the above. In one embodiment, the interlayer dielectric layer 272 is a dielectric layer containing a low-k dielectric material (generally referred to as a low-k dielectric layer). The interlayer dielectric layer 272 includes a multilayer structure of various dielectric materials. The interlayer dielectric layer 272 may be part of a multilayer interconnect structure on the substrate 202 . In one embodiment, the contact etch stop layer 270 and the interlayer dielectric layer 272 include different materials from each other. For example, when the interlayer dielectric layer 272 includes a low-k dielectric material, the contact etch stop layer includes silicon and nitrogen such as silicon nitride or silicon oxynitride. After depositing the interlayer dielectric layer 272 and the contact etch stop layer, a chemical mechanical polishing process or other planarization process may be performed to expose the upper surface of the dummy gate stack 240 . In one embodiment, the planarization process removes the hard mask layer of the dummy gate stack 240 to expose the underlying dummy gate material layer 235 .

As shown in step 122 of FIG. 1 and FIGS. 15C and 15D , the dummy gate stack 240 is removed from the gate structure 250 to form gate openings 275 on the semiconductor layer stack 205 of the fins 218A and 218B and exposed Semiconductor layer stack 205 . In one embodiment, the etching process can completely remove the dummy gate stack 240 to expose the semiconductor layer 215 and the semiconductor layer 210 in the gate opening 275 . The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In one embodiment, the etching process is a multi-step etching process. For example, the etch process may be interleaved with an etchant to separately remove various layers of the dummy gate stack 240, such as the dummy gate layer, the dummy gate dielectric layer, and the hard mask layer. In one embodiment, an etch process is provided to selectively etch the dummy gate stack 240 while minimizing or not etching other structures of the device 200 such as the interlayer dielectric layer 272, gate spacers 254, isolation structures 230, semiconductors layer 215 , and semiconductor layer 210 . In one embodiment, the lithography process described herein may be performed to form a patterned mask layer that may cover the interlayer dielectric layer 272 and the gate spacer 254 . Then, the patterned mask layer is used as an etching mask, and an etching process is performed.

As shown in step 124 of FIG. 1 and FIGS. 16C and 16D , the semiconductor layer 210 of the semiconductor layer stack 205 exposed by the gate opening 275 is selectively removed to form a suspended semiconductor layer 215 in the channel region 202C. For example, the remaining portion of the semiconductor layer 210 is completely removed. In one embodiment, the etch process may selectively etch the semiconductor layer 210 and minimally etch the semiconductor layer 215 , and in some embodiments minimally or not etch the gate spacer 254 and the inner spacer 255 . As described above, the inner spacer 255 can mask the epitaxial drain layers 261B and 262B on the drain side from the contact etch process and from being degraded by the etch chemicals. However, as described above, similar inner spacers are not formed on the source side to protect the epitaxial structure. In summary, the epitaxial source layer 261A on the source side is exposed to the etch chemistry. To avoid damaging the source structure, it is advantageous to maintain good etch selectivity between the epitaxial source layer 261A and the semiconductor layer 210 . In some embodiments, the material composition of the epitaxial source layer 261A is similar to the composition of the semiconductor layer 215 , but not similar to the composition of the semiconductor layer 210 . In conclusion, the etching process can minimize or not etch the epitaxial source layer 261A. Even without the protection of the inner spacer on the source side, this arrangement allows more material choices for the inner layers of the epitaxial source structure 260A, such as the epitaxial source layer 262A. For example, the material composition of the epitaxial source layer 262A of some embodiments may be the same as or similar to the material composition of the semiconductor layer 210 . For example, both the epitaxial source layer 262A and the semiconductor layer 210 may include silicon germanium. In summary, the etch selectivity between these two layers in the wire release process is minimized or has no etch selectivity. In the absence of the epitaxial source layer 261A, the target of the etching chemical in the line release process is the epitaxial source layer 262A (whose material composition is the same as that of the semiconductor layer 210). The epitaxial source layer 261A here surrounds the epitaxial source layer 262A and has a dissimilar material (eg, silicon) to protect the epitaxial source layer 262A from damage during these etching processes.

The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. Various etch parameters can be adjusted to selectively etch the semiconductor layer 210, such as etchant composition, etch temperature, etch solution concentration, etch time, etch pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable etchants parameter, or a combination of the above. For example, the etchant used in the etching process can be selected to etch the material of the semiconductor layer 210 (eg, silicon germanium in the described embodiment) at a higher rate, and etch the material of the semiconductor layer 215 and the epitaxial source at a lower rate The material of layer 261A (eg, silicon in the described embodiment), ie, the etchant, has high etch selectivity to the material of semiconductor layer 210 . In one embodiment, a dry etching process (eg, a reactive ion etching process) uses a fluorine-containing gas such as sulfur hexafluoride to selectively etch the semiconductor layer 210 . In one embodiment, the ratio of fluorine-containing gas to oxygen-containing gas (eg, oxygen), etching temperature, and/or RF power can be adjusted to selectively etch SiGe. In one embodiment, the wet etching process uses an etching solution containing ammonium hydroxide rainwater to selectively etch the semiconductor layer 210 . In one embodiment, the semiconductor layer 210 can be selectively etched by a chemical vapor etching process using hydrogen chloride. In one embodiment, portions of the semiconductor layer 215 are also minimally or not etched.

Thus, the semiconductor layer 215 suspended in the gate opening 275 is exposed. In one embodiment, four suspended semiconductor layers 215 are vertically stacked and exposed in the channel region 202C, which can provide four channels between individual epitaxial source/drain structures for current flow when operating the transistor. pass. The suspended semiconductor layer 215 can thus be regarded as a channel layer. Channel layers such as semiconductor layer 215 may be vertically spaced apart from each other by gaps 277 and from substrate 202 by gaps 277 . The gaps 277 may each have a vertical space along the Z direction. The vertical space largely depends on the thickness of the semiconductor layer 210 and is substantially equal to the thickness (or height) of the inner spacer 255 along the Z direction. In one embodiment, the vertical space may be about 3 nm to about 15 nm. The process shown in Figure 16C can be viewed as a channel (or wire) release process. In one embodiment, after removing the semiconductor layer 210, an etching process may be performed to adjust the profile of the channel layer, such as the semiconductor layer 215, to achieve a desired size and/or a desired shape. In this way, the thickness of the channel layer such as the semiconductor layer 215 can be reduced.

As shown in step 126 of FIG. 1 and FIGS. 17C and 17D, a gate dielectric layer 282 is formed on the device, wherein the gate dielectric layer 282 partially fills the gate opening 275 and wraps (surrounds) a channel layer such as a semiconductor Layer 215. Gate dielectric layer 282 partially fills gaps 277 between vertically adjacent channel layers such as semiconductor layer 215 and between channel layers such as semiconductor layer 215 and substrate 202 (see FIG. 16C ). In one embodiment, the gate dielectric layer 282 may also be on the gate spacer 254 . For example, the gate dielectric layer 282 may include a high dielectric constant dielectric material, such as hafnium oxide, hafnium silicon oxide, hafnium silicate, hafnium silicon oxynitride, hafnium lanthanum oxide, hafnium tantalum oxide, hafnium titanium oxide, Hafnium zirconium oxide, hafnium aluminum oxide, zirconium oxide, zirconium dioxide, zirconium oxide silicon, aluminum oxide, aluminum oxide silicon, aluminum oxide, titanium oxide, titanium dioxide, lanthanum oxide, lanthanum oxide silicon, tantalum trioxide, tantalum pentoxide , yttrium oxide, strontium titanate, barium zirconium oxide, barium titanate, barium strontium titanate, silicon nitride, hafnium oxide-aluminum oxide, other suitable high dielectric constant dielectric materials, or a combination of the above. A high dielectric constant dielectric material is generally regarded as a dielectric material with a dielectric constant greater than that of silicon oxide (about 3.9). In one embodiment, the thickness of the high-k gate dielectric layer 282 may be about 1 nm to about 5 nm. The high-k gate dielectric layer 282 can be formed by any of the processes described herein, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, oxide-based deposition processes, and other suitable processes , or a combination of the above. In one embodiment, the interface layer 280 is located between the gate dielectric layer 282 and a channel layer such as the semiconductor layer 215 . The interface layer 280 may comprise any suitable material, such as silicon oxide, silicon oxynitride, hafnium silicon oxide, or a combination thereof. In one embodiment, the thickness of the interface layer 280 is about 0.5 nm to about 3 nm. If gate dielectric layer 282 (and interface layer 280, if present) is too thin, it may not function reliably as intended. If the gate dielectric layer 282 (and the interface layer 280, if present) is too thick, it will take up unnecessary space and increase the resistance (which could otherwise be used to form the gate).

In some embodiments, gate dielectric layer 282 is formed over the sidewalls of epitaxial source layer 261A in source region 202A (eg, in direct contact with the sidewalls). At the same time, a gate dielectric layer 282 is formed over the sidewalls of the inner spacer 255 in the drain region 202B.

The gate layer 284 is formed on the gate dielectric layer 282 . For example, an atomic layer deposition process can conformally deposit gate layer 284 on gate dielectric layer 282 such that gate layer 284 completely fills gate opening 275 (including the remainder of gap 277). For example, gate layer 284 is along the sidewalls, top, and bottom of channel layers such as semiconductor layer 215 . The thickness of gate layer 284 is set to fill the remainder of gap 277 between vertically adjacent channel layers such as semiconductor layer 215 and between channel layers such as semiconductor layer 215 and substrate 202 . In one embodiment, the gate layer 284 may include a work function layer. For example, p-type work function layers can be formed in n-type doped regions for p-type devices, and n-type work function layers can be formed in p-type doped regions for n-type devices. The work function layer may be conformably formed on and between the high-k gate dielectric layer 282, and may have a thickness of about 1 nm to 10 nm. The p-type work function layer includes any suitable p-type work function material, such as titanium nitride, tantalum nitride, tantalum silicon nitride, ruthenium, molybdenum, aluminum, tungsten nitride, tungsten carbonitride, zirconium silicide, molybdenum silicide silicide, tantalum silicide, nickel silicide, other p-type work function materials, or a combination of the above. The n-type work function layer includes any suitable n-type work function material, such as titanium, aluminum, silver, manganese, zirconium, titanium aluminum, titanium aluminum carbide, titanium aluminum silicon carbide, tantalum carbide, tantalum carbonitride, tantalum silicon nitride , tantalum aluminum, tantalum aluminum carbide, tantalum aluminum silicon carbide, titanium aluminum nitride, other n-type work function materials, or a combination of the above. In one embodiment, the gate layer 284 may include a metal filling layer (or a base layer) formed on the device 200, especially formed on the p-type work function layer and the n-type work function layer. For example, a chemical vapor deposition process or a physical vapor deposition process deposits a metal fill layer on the work function layer such that the metal fill layer fills any remaining portion of gate opening 275 (including any remaining portion of gap 277). The metal fill layer includes suitable conductive materials such as aluminum, tungsten, and/or copper. The metal fill layer may additionally or collectively comprise other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. The metal filling layer and/or the work function layer can be formed by any suitable deposition process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, high density plasma chemical vapor deposition, organometallic chemical vapor deposition Deposition, Remote Plasma Chemical Vapor Deposition, Plasma Assisted Chemical Vapor Deposition, Low Pressure Chemical Vapor Deposition, Atomic Layer Chemical Vapor Deposition, Atmospheric Pressure Chemical Vapor Deposition, Spin Coating, Electroplating, Other Deposition Processes, or combination of the above. A planarization process can be performed to remove excess gate material. For example, the chemical mechanical polishing process is performed until the upper surface of the interlayer dielectric layer 272 is exposed, so that the upper surface of the dummy gate stack 240 after the chemical mechanical polishing process and the upper surface of the interlayer dielectric layer 272 are substantially coplanar .

As shown in step 128 of FIG. 1 and FIGS. 18C and 18D, fabrication may continue to complete the device. For example, openings may be formed in the interlayer dielectric layer 272 to expose the upper surfaces of the epitaxial source structures 260A and the epitaxial drain structures 260B. Contact structures can then be formed in the openings to interface with the exposed upper surfaces of the epitaxial source structures 260A and the epitaxial drain structures 260B. The contact structure 292 may comprise a conductive material such as metal. Metals include aluminum, aluminum alloys (eg, aluminum, silicon, alloys with copper), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or a combination thereof. In one embodiment, the device is processed (eg, annealed) to form silicide structures 290 between contact structures 292 and epitaxial source structures 260A and between contact structures 292 and epitaxial drain structures 260B. Additionally, one or more interlayer dielectric layers (similar to the interlayer dielectric layer 272 and/or the contact etch stop layer) may be formed on the substrate 202 (especially on the interlayer dielectric layer 272 and the gate structure 250).

Additional process steps may be included before or after any of the process steps of FIG. 1 . Furthermore, the sequence of steps in FIG. 1 may be changed without departing from the spirit of the embodiments of the present invention. For example, the embodiments described above may form the epitaxial source structure before forming the epitaxial drain structure, but instead the epitaxial drain structure may be formed before forming the epitaxial source structure. These adjustments also belong to the embodiments of the present invention.

It can be seen from the above description that the device provided by the embodiment of the present invention has multiple unique characteristics. For example, a device may include an inner spacer layer in the drain region, but not include an inner spacer layer in the source region. For example, the gate portion of the device may interface with epitaxial material in the source region and dielectric material in the drain region. For example, a device may include two epitaxial source layers in the source region, each having different epitaxial materials from each other; and two epitaxial drain layers in the drain region, each having the same epitaxial material Epitaxial material. For example, a device may include two epitaxial source layers in the source region, but only one epitaxial drain layer in the drain region. For example, a device may include p-type transistors and n-type transistors. The p-type transistor may include a first epitaxial source layer, and a second epitaxial source layer formed on and between the first epitaxial source layer. The first epitaxial source layer and the second epitaxial source layer may contain different materials. The p-type transistor may further include a first epitaxial drain layer and a second epitaxial drain layer. The first epitaxial drain layer and the second epitaxial drain layer may have the same material. The n-type transistor may include a third epitaxial source layer and a fourth epitaxial source layer. The third epitaxial source layer and the fourth epitaxial source layer may include the same material. The n-type transistor may further include a third epitaxial drain layer and a fourth epitaxial drain layer. The third epitaxial drain layer and the fourth epitaxial drain layer may have the same material.

Embodiments of the present invention provide advantages to semiconductor processes and semiconductor devices, but are not limited thereto. 18C and 18D as examples, the channel layer such as the semiconductor layer 215 in the source region 202A not only directly contacts the vertical interface such as the sidewall surface 295A of the epitaxial source structure 260A, but also contacts the horizontal plane such as the upper surface 297A and the lower surface 298A. In summary, as current such as charge carriers move toward the contact structure 292 through a narrow channel layer such as the semiconductor layer 215, the current can diffuse to the epitaxial source layer 261A once the charge carriers cross the imaginary surface (eg through upper surface 297A and lower surface 298A). Compared to embodiments in which inner spacers are formed above and below the upper and lower surfaces 297A and 298A, the carrier charges need only travel a shorter distance to disperse the charges. In other words, the degree of current crowding can be alleviated. In summary, the operating speed of the device can be increased. In addition, the methods provided herein can preserve inner spacers in the drain region 202B to reduce parasitic capacitance. Different embodiments may have different advantages. It is not necessary for any embodiment to have all advantages.

An exemplary embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a semiconductor substrate; a source structure and a drain structure on the semiconductor substrate; a semiconductor layer stack sandwiched between the source structure and the drain structure; a gate portion; and an inner spacer of a dielectric material. The gate portion is located between two vertically adjacent layers of the semiconductor layer stack, and between the source structure and the drain structure. In addition, the gate portion has opposing first and second sidewall surfaces. An inner spacer is located on the first sidewall surface and between the gate portion and the drain structure. The second sidewall surface directly contacts the source structure.

In some embodiments, the source structure includes a first source layer and a second source layer on the first source layer. The first source layer has a first source material, the second source layer has a second source material, and the second source material is different from the first source material. In some embodiments, the drain structure includes a first drain layer and a second drain layer on the first drain layer. The first drain layer has a first drain material, the second drain layer has a second drain material, and the second drain material is substantially the same as the first drain material. In some embodiments, the first drain layer directly contacts the inner spacer. In some embodiments, one layer of the semiconductor layer stack includes an upper surface and a side surface, the first portion of the first source layer extends along and is formed on the upper surface of the one layer of the semiconductor layer stack, and the first source layer The second portion of the semiconductor layer extends along and is formed on a side surface of one layer of the semiconductor layer stack. In some embodiments, the gate portion includes a gate dielectric layer, and the first source layer physically interfaces with the gate dielectric layer. In some embodiments, the drain structure directly contacts the inner spacer. In some embodiments, the dielectric material is the first dielectric material. The gate portion includes a second dielectric material on the first sidewall surface and the second sidewall surface. Additionally, the source structure interfaces with the second dielectric material on the second sidewall surface, and the drain structure interfaces with the inner spacer on the first sidewall surface. In some embodiments, one layer of the semiconductor layer stack includes a first portion to interface with the source structure, a second portion to interface with the drain structure, and a third portion between the first and second portions and over the gate portion . The lower surface of the first portion interfaces with the epitaxial material, and the lower surface of the second portion interfaces with the spacer material. In some embodiments, the semiconductor stack is a first semiconductor layer stack, and the semiconductor device further includes a second semiconductor layer stack and a third semiconductor layer stack. The source structure is located between the first semiconductor layer stack and the second semiconductor layer stack, and the drain structure is located between the first semiconductor layer stack and the third semiconductor layer stack. One layer of the second semiconductor layer stack includes at least three sides of the end portion directly interfacing with the source structure. One side of the end portion included in one layer of the third semiconductor layer stack directly interfaces with the drain structure, and the other side of the end portion included in one layer of the third semiconductor layer stack directly interfaces with the inner spacer.

An exemplary embodiment of the present invention relates to a method of forming a semiconductor device. The method includes receiving a structure. The structure includes a semiconductor substrate; a stack of a first semiconductor layer and a second semiconductor layer; and a dummy gate structure on the stack. The first semiconductor layer and the second semiconductor layer have different material compositions and are staggered with each other in the stack. The method also includes removing a first portion of the stack on the source layer of the dummy gate structure to form a source trench, thereby exposing first sidewall surfaces of the stack in the source trench. The method further includes removing a first portion of the first semiconductor layer from the exposed first sidewall surface to form a first gap; and epitaxially growing a source structure in the source trench and the first gap. Additionally, the method includes removing a second portion of the stack on the drain side of the dummy gate structure to form a drain trench, thereby exposing a second sidewall surface of the stack in the drain trench. The method further includes removing a second portion of the first semiconductor layer from the exposed second sidewall surface to form a second gap. Next, an inner spacer is formed in the second gap. The method additionally includes epitaxially growing a drain structure in the drain trench. The method additionally includes removing the dummy gate structure to form a gate opening on the stack; removing a third portion of the first semiconductor layer from the gate opening to form an extended gate opening; forming a gate dielectric layer on the extended in the gate opening; and forming the gate on the gate dielectric layer in the extended gate opening.

In some embodiments, the step of removing the first portion of the first semiconductor layer includes forming a first side surface of the first semiconductor layer, and the step of epitaxially growing the source structure includes growing on the first side surface. In some embodiments, the step of epitaxially growing the drain structure includes growing the drain structure to cover sidewall surfaces of the inner spacer. In some embodiments, the step of epitaxially growing the source structure includes: growing a first source layer of a first source material in the source trench and the first gap; and growing a second source of a second source material The electrode layer is on the first source electrode layer. The second source material is different from the first source material. In some embodiments, the step of epitaxially growing the drain structure includes: growing a first drain layer of a first drain material in the drain trench; and growing a second drain layer of a second drain material on the on a drain layer. The second drain material is substantially the same as the first drain material. In some embodiments, the step of forming the gate dielectric layer includes forming the gate dielectric layer on the sidewall surfaces of the source structure and the sidewall surfaces of the inner spacers. In some embodiments, the step of epitaxially growing the source structure includes epitaxially growing between vertically adjacent second semiconductor layers.

An exemplary embodiment of the present invention relates to a method of forming a semiconductor device. The method includes receiving a structure. The structure has a semiconductor substrate and a stack of first and second semiconductor layers on the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have different material compositions and are staggered with each other in the stack. The method also includes patterning the stack to form the fin structure; forming a dummy gate structure on the fin structure; etching source trenches in the stack on the first side of the dummy gate structure; laterally etching the first semiconductor layer to form a first gap; forming a source structure in the source trench and the first gap; etching the drain trench in the stack on the second side of the dummy gate structure, and the second side of the gate structure is The first side is opposite; the first semiconductor layer is laterally etched to form the second gap; the inner spacer is formed in the second gap; the drain structure is formed in the drain trench; the dummy gate structure is removed to form the first gate a gate opening; removing the remaining part of the first semiconductor layer to form a second gate opening; and forming a gate structure in the first gate opening and the second gate opening.

In some embodiments, the step of forming the source structure includes epitaxially growing the source structure on the sidewall surface of the etched first semiconductor layer. In addition, the step of forming the drain structure includes epitaxially growing the drain structure to cover the sidewall surface of the inner spacer. In some embodiments, the step of forming the source structure includes forming a first source layer and forming a second source layer on the first source layer. In addition, the step of forming the drain structure includes forming a first drain layer and forming a second drain layer on the first drain layer. Surface profiles of the first source layer and the first drain layer are different.

The features of the above-described embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and/or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent replacements do not depart from the spirit and scope of the present invention, and can be changed, replaced, or altered without departing from the spirit and scope of the present invention.

B-B', C-C', D-D': section line 100: Method 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128: Steps 200: Device 202: Substrate 202A: Source region 202B: Drain region 202C: Passage Area 205: Semiconductor layer stacking 210, 215: Semiconductor layers 218A, 218B: Fins 230: Isolation Structure 232: Hard mask material layer 235: Dummy gate material layer 238: Dielectric Material Layer 240: Gate stack 250: Gate structure 252, 252', 262, 266: mask layer 253A, 253B, 277: Clearance 254: gate spacer, gate spacer layer 255: Medial Spacer 258A: Source trench 258B: drain trench 260A: Epitaxial source structure 260B: Epitaxial drain structure 261A, 262A: Epitaxial source layer 261B, 262B: Epitaxial drain layer 263a, 263b: Parts 264A: Extended source trench 268: Spacer Material Layer 270: Contact etch stop layer 272: Interlayer dielectric layer 275: gate opening 280: Interface Layer 282: gate dielectric layer 284: gate layer 290: Silicide Structure 292: Contact Structure 294A, 295A, 296A: Sidewall Surfaces 297A: Upper surface 298A: Lower surface

FIG. 1 is a flowchart of a method for fabricating a nanosheet-based device in various embodiments of the present invention. Figures 2A, 2B, 2C, 2D, 3C, 3D, 4C, 4D, 5C, 5D, 6C, 6D, 7C, 7D, 8C, 8D, 9C, 9D, 10C, 10D, 11C, 11D, 12C, 12D, 13C , 13D, 14C, 14D, 15C, 15D, 16C, 16D, 17C, 17D, 18C, and 18D are various embodiments of the present invention, and some or all of the nanosheet-based devices are used in various fabrication stages (eg, as shown in Fig. 1 method related) part of the schema.

202: Substrate

202A: Source region

202B: Drain region

202C: Passage Area

215: Semiconductor layer

255: Medial Spacer

260A: Epitaxial source structure

260B: Epitaxial drain structure

261A, 262A: Epitaxial source layer

261B, 262B: Epitaxial drain layer

280: Interface Layer

282: gate dielectric layer

284: gate layer

290: Silicide Structure

292: Contact Structure

Claims (1)

A semiconductor device, comprising: a semiconductor substrate; a source structure and a drain structure on the semiconductor substrate; a semiconductor layer stack sandwiched between the source structure and the drain structure; a gate portion located between two vertically adjacent layers of the semiconductor layer stack and between the source structure and the drain structure, the gate portion having a first sidewall surface opposite to a second sidewall surface; and an inner spacer located on the first sidewall surface and between the gate portion and the drain structure, and the inner spacer is a dielectric material, Wherein the second sidewall surface directly contacts the source structure.

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