CN108122845B - Contact structure manufacturing method and semiconductor device - Google Patents

Contact structure manufacturing method and semiconductor device Download PDF

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Publication number
CN108122845B
CN108122845B CN201710402860.1A CN201710402860A CN108122845B CN 108122845 B CN108122845 B CN 108122845B CN 201710402860 A CN201710402860 A CN 201710402860A CN 108122845 B CN108122845 B CN 108122845B
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gate
layer
drain
contact
transistor
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CN108122845A (en
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徐宛萱
王怡琇
陈彦兆
张展玮
汪于仕
吕信谚
邱意为
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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Abstract

A method for manufacturing a contact structure includes forming a first transistor and a second transistor on a substrate, wherein the first transistor and the second transistor share a source/drain region, the source/drain region is formed between a first gate of the first transistor and a second gate of the second transistor, a first opening is formed in an interlayer dielectric layer, an etch stop layer is deposited in the first opening between the first gate and the second gate, a dielectric layer is deposited on the etch stop layer on a top surface of the interlayer dielectric layer, a first etching process is performed on the dielectric layer until the etch stop layer is exposed, and a second etching process is performed on the etch stop layer until the exposed portion of the etch stop layer and a portion of the dielectric layer are removed.

Description

Contact structure manufacturing method and semiconductor device
Technical Field
Embodiments of the present invention relate to a contact structure and a method for fabricating the same, and more particularly, to a contact structure having an enlarged drain contact and a method for fabricating the same.
Background
The semiconductor industry has experienced rapid growth due to the continued improvement in the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density comes in large part from the continual reduction in minimum feature size, which allows more devices to be integrated in a given area. However, smaller feature sizes may result in an undesirable increase in contact resistance. With the demand for miniaturization, higher speed, larger bandwidth, lower power consumption, delay, etc., the demand for reducing contact resistance is increasing.
Disclosure of Invention
According to an embodiment, a method of fabricating a contact structure includes: forming a first transistor and a second transistor on the substrate, wherein the first transistor and the second transistor share a source/drain region, and the source/drain region is formed between a first gate of the first transistor and a second gate of the second transistor; forming a first opening in the interlayer dielectric layer and between the first gate and the second gate; depositing an etch stop layer in the first opening and on a top surface of the inter-level dielectric layer; depositing a dielectric layer on the etch stop layer; depositing a photoresist layer on the dielectric layer; patterning the photoresist layer to form a second opening in the photoresist layer, wherein an outermost edge of the second opening is aligned with an outermost edge of the first opening; performing a first etching process on the dielectric layer until the etching stop layer is exposed; performing a second etching process on the etching stop layer until the exposed part of the etching stop layer and the part of the dielectric layer are removed to form a third opening, wherein the maximum width of the third opening is greater than that of the second opening; and filling the third opening with a conductive material.
According to an embodiment, a method of fabricating a contact structure includes: forming a first transistor and a second transistor on a substrate, wherein: the first transistor comprises a first source electrode, a first grid electrode and a drain electrode; and the second transistor comprises a second source electrode, a second grid electrode and a drain electrode. The method further includes forming a first protective layer and a second protective layer along the sidewall spacers of the first transistor and the second transistor, respectively, wherein the first protective layer and the second protective layer are between the first gate and the second gate and on the drain; forming a lower drain contact in the interlayer dielectric layer and between the first gate and the second gate; forming a first opening in the interlayer dielectric layer and on the lower drain contact; depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer; depositing a dielectric layer on the etch stop layer; performing a first etching process on the dielectric layer until the etching stop layer is exposed; performing a second etching process on the etching stop layer until the exposed part of the etching stop layer and part of the dielectric layer are removed to form a second opening, wherein the width of the upper part of the second opening is larger than that of the upper part of the first opening; and filling the second opening with a conductive material.
According to an embodiment, a contact structure apparatus includes: a first source and a common drain on opposite sides of the first gate; a second source and a common drain on opposite sides of the second gate, wherein: the first grid and the second grid are positioned in the interlayer dielectric layer on the substrate; and the first gate and the second gate are surrounded by the first gate spacer and the second gate spacer, respectively. The device further includes a first protective layer formed along sidewalls of the first gate spacer, wherein the first protective layer is on the common drain and a top surface of the first protective layer has a first slope; a second protective layer formed along a sidewall of the second gate spacer, wherein the second protective layer is on the common drain and a top surface of the second protective layer has a second slope; and a first drain contact formed between the first gate and the second gate, wherein a width of an upper portion of the first drain contact is greater than a width of a lower portion of the first drain contact.
Drawings
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the present invention.
FIG. 1 is a cross-sectional view of a semiconductor device according to various embodiments of the present invention;
fig. 2 to 10 are intermediate steps of manufacturing the semiconductor device shown in fig. 1 according to various embodiments of the present invention;
FIG. 11 is a flow chart depicting a method of forming the semiconductor device shown in FIG. 1, in accordance with various embodiments of the present invention; and
fig. 12 is a cross-sectional view depicting a FinFET semiconductor device having an enlarged drain/source contact, in accordance with various embodiments of the present invention.
Wherein the reference numerals are as follows:
100-semiconductor device
101 to first transistor
102 to second transistor
104 to substrate
106 first isolation region
108 to second isolation region
112-first source
114-drain electrode
116 to second source electrode
120-interlayer dielectric layer
121-first gate dielectric layer
122 to second gate dielectric layer
123 to first grid
124 to the second grid
125-first gate spacer
126-second gate spacer
127 first protective layer
128. 130-drain contact
129 to the second protective layer
202. 602, 702-opening
302 etch stop layer
402 dielectric layer
502 photoresist layer
1102. 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120-step
1200-FinFET device
Detailed Description
While various embodiments or examples are disclosed below to practice various features of the provided subject matter, embodiments of specific elements and arrangements thereof are described below to illustrate the invention. These examples are, of course, intended to be illustrative only and should not be construed as limiting the scope of the invention. For example, references in the specification to a first feature being formed over a second feature include embodiments in which the first and second features are in direct contact, and embodiments in which there are additional features between the first and second features, i.e., the first and second features are not in direct contact. Moreover, where specific reference numerals or designations are used in various embodiments, these are merely used to identify the invention in a simplified and clear manner, and are not intended to necessarily represent a particular relationship between the various embodiments and/or structures discussed.
Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to describe one element or feature's relationship to another element or feature(s) of the illustrations and may encompass different orientations of the device in use or operation and orientations of the device in the figures and the like. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.
The invention will be described in the following with embodiments of a drain contact structure having an enlarged top critical dimension and a method of forming the same. However, embodiments of the present invention may also be applied to a variety of semiconductor structures. For example, the process may be applied to form a source contact structure. In addition, the embodiments of the present invention are applicable not only to planar transistor devices but also fin field effect transistor (FinFET) devices. Various embodiments will be described hereinafter with reference to the accompanying drawings.
Fig. 1 is a cross-sectional view of a semiconductor device according to various embodiments of the present invention. The semiconductor device 100 includes two transistors sharing a common drain formed on a substrate 104 and at least partially between a first isolation region 106 and a second isolation region 108. The first transistor 101 comprises a first gate 123 and its gate dielectric layer 121, a drain 114 and its contacts 128 and 130, and a first source 112 and its contacts (not shown). The second transistor 102 includes a second gate 124 and gate dielectric layer 122, a drain 114 and its contacts 128 and 130, and a second source 116 and its contacts (not shown).
It should be noted that the common drain shown in fig. 1 is for illustration only, and is not limiting to the various embodiments of the present invention. One of ordinary skill in the art would recognize that there are numerous variations, alternatives, and modifications. For example, the semiconductor device 100 may include two transistors that share a common source.
As shown in fig. 1, a first gate spacer 125 is formed next to the first gate 123. As shown in the cross-sectional view of fig. 1, the first gate spacer 125 includes two portions. The first portion is formed at one side of the first gate electrode 123. The second portion is formed on the opposite side of the first gate electrode 123. A first portion of the first gate spacer 125 separates the first source 112 and the first gate 123. A second portion of the first gate spacer 125 separates the drain 114 and the first gate 123.
A second gate spacer 126 is formed adjacent to the second gate 124. Similarly, a second gate spacer 126 separates the second source 116 and the second gate 124.
Gates 123 and 124 are formed in the ild layer 120. An etch stop layer 302 is formed on the ild layer 120. A dielectric layer 402 is formed over the etch stop layer 302. Drain contacts 128 and 130 are formed between the first gate 123 and the second gate 124.
A drain contact 128 is embedded in the interlayer dielectric 120 between the first gate 123 and the second gate 124. The bottom surface of the drain contact 128 contacts the drain 114. It should be noted that a silicide region (not shown) may be formed between the drain 114 and the drain contact 128 to improve the contact resistance of the drain 114. Throughout the specification, the drain contact 128 may be referred to as a lower drain contact 128.
In some embodiments, the lower drain contact 128 is an inverted trapezoid, as shown in fig. 1. The shape of the lower drain contact 128 shown in fig. 1 is merely exemplary, and those skilled in the art will appreciate that the lower drain contact 128 may comprise other shapes, such as, but not limited to, rectangular, square, trapezoidal, and the like.
As shown in fig. 1, drain contact 130 is stacked on drain contact 128. Throughout the specification, the drain contact 130 may be referred to as an upper drain contact 130. The lower portion of the upper drain contact 130 is an inverted trapezoid and is located between the first gate 123 and the second gate 124. The upper portion of the drain contact 130 is rectangular and extends through the dielectric layer 402 and the etch stop layer 302.
As shown in fig. 1, the width of the bottom of the upper drain contact 130 is approximately equal to the width of the top of the lower drain contact 128. The middle portion of the upper drain contact 130 is adjacent to the first gate spacer 125 and the second gate spacer 126. To protect the sidewalls of the gate spacers and the gates 123 and 124, a first protection layer 127 is formed between the drain contact and the first gate spacer 125. A second protective layer 129 is formed between the drain contact and the second gate spacer 126.
It should be noted that although fig. 1 depicts two protective layers 127 and 129 separated on a cross-section of the semiconductor device 100, those skilled in the art will appreciate that various changes, substitutions, and alterations are possible. For example, in some embodiments, protective layers 127 and 129 may be part of a continuous protective layer.
As shown in fig. 1, the top surface of the first protection layer 127 has a slope extending downward from the edge of the top surface of the first gate spacer 125. Similarly, the top surface of the second protection layer 129 has a slope extending downward from the edge of the top surface of the second gate spacer 126. The slope of the protective layers 127 and 129 helps increase the size of the trench where the upper drain contact 130 is formed, thereby improving the metal gap fill of the drain contact. As shown in fig. 1, the width of the trench increases from W2 to W1. W2 is the minimum distance between the first protective layer 127 and the second protective layer 129. W1 is the width of the upper portion of the upper drain contact 130. In some embodiments, the ratio of W1 to W2 is between about 1.1 to about 1.3.
One advantageous feature of having an enlarged trench as shown in fig. 1 is that the enlarged trench helps to reduce contact resistance, thereby improving the performance of the semiconductor device 100. For example, the resistance-capacitance (RC) delay of the semiconductor device 100 may be improved by the enlarged drain contact 130 shown in fig. 1. A detailed process of forming the protective layers of the upper drain contacts 130 and 127 and 129 will be described later with reference to fig. 2 to 10.
Fig. 2 through 10 illustrate intermediate steps in the fabrication of the semiconductor device shown in fig. 1, according to various embodiments of the present invention. It should be noted that the fabrication steps and semiconductor structures shown in fig. 1 are merely exemplary. Those skilled in the art will appreciate that various changes, substitutions, and alterations are possible.
Fig. 2 is a cross-sectional view of a semiconductor device after a lower drain contact is formed on the semiconductor device, according to various embodiments of the present invention. The semiconductor device 100 is formed on a substrate 104. Specifically, a drain 114 and sources 112 and 116 are formed in the substrate 104 and between the isolation regions 106 and 108. Gate electrodes 123 and 124 are formed in the interlayer dielectric layer 120. A lower drain contact 128 is formed between gates 123 and 124.
The substrate 104 may be formed from silicon, although it may also be formed from other group III, group IV, and/or group V elements, such as silicon, germanium, gallium, arsenic, combinations thereof, and the like. The substrate 104 may also be a silicon-on-insulator (SOI). The SOI substrate may include a layer of semiconductor material (e.g., silicon, germanium, etc.) formed over an insulating layer (e.g., buried oxygen, etc.) formed in a silicon substrate. In addition, other substrates such as multi-layered substrates, gradient substrates, hybrid orientation substrates, and/or the like may also be used.
The substrate 104 may further include various circuits such as transistors (e.g., transistor 101 and transistor 102). For simplicity, only two transistors sharing a drain are presented to illustrate the innovative aspects of the various embodiments.
The circuitry formed on the substrate 104 may be any circuitry suitable for a particular application. According to one embodiment, the circuit may include various n-type metal oxide semiconductor (NMOS) and/or p-type metal oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, light emitting diodes, fuses, and the like. The circuits may be interconnected to perform at least one function. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, and the like.
According to one embodiment, the substrate 104 may be a p-type substrate doped with a p-type dopant such as boron, indium, or the like. P-type epitaxial layers (not shown) may be grown from the p-type substrate 104 according to design requirements and different applications. Source 112, 116 and drain 114 may be formed in the p-type epitaxial layer. The p-type epitaxial layer may be epitaxially grown by using a suitable semiconductor process, such as Chemical Vapor Deposition (CVD), ultra-high vacuum chemical vapor deposition (UHV-CVD), and the like.
As shown in fig. 2, the first source electrode 112 and the drain electrode 114 are formed on opposite sides of the first gate electrode 123. A second source 116 and a drain 114 are formed on opposite sides of the second gate 124. In an embodiment where the substrate 104 is an n-type substrate, the source and drain regions may be formed by implanting appropriate p-type dopants, such as boron, gallium, indium, and/or the like. Furthermore, in an embodiment where the substrate 104 is a p-type substrate, the source and drain regions may be formed by implanting appropriate n-type dopants, such as phosphorus, arsenic, and/or the like.
The isolation regions 106 and 108 may be Shallow Trench Isolation (STI) regions, which may be formed by etching the substrate 104 to form multiple trenches and filling the trenches with dielectric materials known in the art to form the isolation regions 106 and 108. For example, the isolation regions 106 and 108 may be filled with a dielectric material such as an oxide material, a high-density plasma (HDP) oxide, and/or the like. A planarization process, such as a Chemical Mechanical Polishing (CMP) process, may be applied to the top surface so that excess dielectric material may be removed.
The gate dielectric layers 121 and 122 may be formed of a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, oxide, nitrogen-containing oxide, combinations thereof, and/or the like. Gate dielectric layers 121 and 122 have a relative dielectric constant greater than about 4. Examples of other such materials include aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, combinations thereof, and the like. In an embodiment in which the gate dielectric layers 121 and 122 include oxide layers, the gate dielectric layers 121 and 122 may be formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process using Tetraethoxysilane (TEOS) and oxygen as precursors. According to one embodiment, the thickness of gate dielectric layers 121 and 122 may range from about
Figure BDA0001310148830000072
To about
Figure BDA0001310148830000071
The gates 123 and 124 may comprise a conductive material such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped polysilicon, other conductive materials, combinations thereof, and/or the like. In one embodiment in which the gates 123 and 124 are formed of polysilicon, the gate electrodes 123 and 124 may be formed by depositing doped or undoped polysilicon by low-pressure chemical vapor deposition (LPCVD). Throughout the specification, the gate electrodes 123 and 124 may also be referred to as a first gate electrode 123 and a second gate electrode 124, respectively.
Gate spacers 125 and 126 may be formed by blanket depositing at least one spacer layer (not shown) over gates 123 and 124 and substrate 104 and etching the spacer layer. Gate spacers 125 and 126 may comprise a suitable dielectric material such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxynitride, oxide, and/or the like. The gate spacers 125 and 126 may be formed by conventional techniques such as CVD, PECVD, sputtering, and/or the like.
A first protective layer 127 and a second protective layer 129 are formed along sidewalls of the first gate spacers 125 and sidewalls of the second gate spacers 126, respectively. In some embodiments, the first protection layer 127 and the second protection layer 129 may serve as Contact Etch Stop Layers (CESL). The CESL layer may comprise commonly used dielectric materials such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, combinations thereof, and multilayers thereof. In some embodiments, in addition to stopping the etch process, the CESL layer may also apply stress to the channel region of the individual transistors.
In some embodiments, the first protective layer 127 and the second protective layer 129 are part of a continuous protective layer. The dielectric layer is deposited and etched by an Atomic Layer Deposition (ALD) process to form the continuous passivation layer as shown in fig. 2. A pre-heat treatment process is applied to the semiconductor apparatus 100 before the ALD process is performed on the semiconductor apparatus 100. The preheat process increases the temperature of the ALD process to a higher temperature. In some embodiments, the temperature of the ALD process is between about 550 ℃ to about 600 ℃ after the preheat process is applied to the semiconductor device 100.
As shown in fig. 2, an interlayer dielectric layer 120 is formed on the substrate 104. The interlayer dielectric layer 120 may be formed, for example, from a low dielectric constant (low-k) dielectric material, such as silicon oxide. The interlayer dielectric layer 120 may be formed by any suitable method known in the art, such as spin-on coating, CVD, PECVD, and the like. Furthermore, those skilled in the art will recognize that although FIG. 2 illustrates only a single ILD layer, the ILD layer 120 may include multiple ILDs.
In some embodiments, the interlayer dielectric layer 120 may include a lower portion and an upper portion. The lower and upper portions of the interlayer dielectric layer 120 are formed by two separate manufacturing steps. After the lower portion is formed, a lower drain contact 128 is formed in the lower portion of the interlayer dielectric layer 120 and between the first gate 123 and the second gate 124. The lower drain contact 128 is used to provide an electrical connection between the drain 114 and an interconnect structure (not shown) formed on the interlayer dielectric layer 120.
A photoresist material may be deposited and patterned on the lower portion of the interlayer dielectric layer 120 photoresist using photolithography techniques to form the lower drain contact 128. Depending on the location and shape of the lower drain contact 128, a portion of the photoresist is exposed. An etching process, such as an anisotropic dry etch process, may be used to create an opening in the lower portion of the ild layer 120. A conductive liner (not shown) may be deposited prior to filling the contact openings. In some embodiments, the conductive liner is conformal and may include a single layer of Ta, TaN, WN, WSi, TiN, Ru, and combinations thereof. The conductive liner layer may act as a barrier layer to prevent diffusion of conductive materials, such as copper, into the underlying substrate 104. The conductive liner may be deposited using a suitable deposition process, such as CVD, PVD, ALD, and/or the like.
The openings are then filled with a conductive material. The conductive material may be deposited using a suitable deposition process such as CVD, PVD, ALD, and the like. A conductive material is deposited on the conductive liner to fill the contact opening. The conductive material may be copper, tungsten, aluminum, silver, titanium nitride, tantalum, combinations thereof, and/or the like.
It should be noted that the polycide regions may be formed on the top surface of the drain and source regions. Silicide regions may be formed on the respective source/drain regions by a self-aligned silicide process. As is known in the art, in salicide processes for forming silicide regions, a metal layer is formed by first depositing a thin metal layer, such as cobalt, nickel, titanium, etc., on the device. The device is then annealed to form silicide regions between the deposited metal and the exposed silicon regions thereunder.
Fig. 2 further illustrates the formation of an opening 202 in the upper portion of the ild layer 120. The opening 202 may be formed by applying and developing a suitable photoresist layer (not shown) and removing a portion of the upper portion of the ild layer 120 until the top surface of the lower drain contact 128 is exposed.
It should be noted that the gates 123 and 124 shown in fig. 2 may be formed by a gate-last semiconductor fabrication process. More specifically, a dielectric layer (e.g., silicon oxide) and a dummy gate layer (e.g., polysilicon) are deposited over substrate 104. Two gate stack structures are formed by etching the dielectric layer and the dummy gate layer. A dielectric material, such as silicon nitride, is deposited and etched to form gate spacers 125 and 126. An interlevel dielectric layer (e.g., dielectric layer 120) is then deposited over substrate 104. The dummy gate layer and the dielectric layer are removed by a suitable etch process to form two gate trenches. As shown in fig. 2, the gate trenches are filled with a high-k dielectric material to form gate dielectric layers 121 and 122, and with a gate material to form gates 123 and 124.
Fig. 3 is a cross-sectional view illustrating the semiconductor device shown in fig. 2 after an etch stop layer 302 is formed thereon according to various embodiments of the present invention. An etch stop layer 302 may be deposited in the opening 202 and on the top surface of the ild layer 120. Can be made of aluminum oxynitride (AlON), aluminum oxide (Al)2O3) Aluminum nitride (AlN), hafnium oxide (HfO)x) Zirconium oxide (ZrO)x) And combinations and/or the like thereof form the etch stop layer 302.
A suitable manufacturing technique may be used and,such as CVD, to form the etch stop layer 302, although any acceptable process may be used to form it
Figure BDA0001310148830000091
To about
Figure BDA0001310148830000092
A thickness of etch stop layer 302. According to one embodiment, the thickness of the etch stop layer 302 is approximately equal to
Figure BDA0001310148830000093
In some embodiments, the material of etch stop layer 302 comprises a different material than the material overlying etch stop layer 302. The difference in materials causes the etch stop layer 302 to etch at a slower rate than the material that covers it. The etch stop layer 302 provides a clear indication of when to end the etch process, thereby protecting the material under the etch stop layer 302.
Fig. 4 is a cross-sectional view of the semiconductor device shown in fig. 3 after a dielectric layer 402 is formed on the etch stop layer 302 according to various embodiments of the present invention. A dielectric layer 402 is formed on the etch stop layer 302. The dielectric layer 402 may be formed from a dielectric material, such as an oxide or silicon nitride, although other suitable dielectric materials, such as high dielectric constant dielectric materials, may also be used. The dielectric layer 402 may be formed using a PECVD process, although any other suitable process may be used.
Fig. 5 is a cross-sectional view of the semiconductor device shown in fig. 4 after forming a mask layer 502 over the dielectric layer 402, according to various embodiments of the present invention. A mask layer 502 is deposited over the dielectric layer 402. In some embodiments, the mask layer 502 may be formed from a photoresist material. Throughout this description, the mask layer 502 may also be referred to as a photoresist layer 502.
The photoresist layer 502 may be formed by a suitable technique, such as spin coating or the like. The photoresist material may be SU-8 (a registered trademark of shell chemical) photosensitive epoxy (photo-sensitive epoxy), a film-like polymer material, and/or the like. It should be noted that those skilled in the art will recognize that although only one photoresist layer is illustrated in fig. 5, photoresist layer 502 may comprise multiple photoresist layers.
Fig. 6 is a cross-sectional view of the semiconductor device shown in fig. 5 after forming an opening 602 in the mask layer 502, according to various embodiments of the present invention. Selected areas of the photoresist layer 502 are exposed after considering the location and dimensions of the upper drain contact 130 shown in fig. 1. A developer is applied to the photoresist layer 502 to form an opening 602 in the photoresist layer 502.
In some embodiments, the outermost edge of the opening 602 is substantially aligned with the outermost edge of the opening 202 depicted in fig. 2. The width of the opening 602 is defined as W3, as shown in fig. 6.
After patterning the photoresist layer 502, two regions of photoresist material may be formed on top of the dielectric layer 402, as shown in FIG. 6. The remaining photoresist regions help to prevent the dielectric layer 402 under the photoresist layer 502 from being etched away by the etching process described below in fig. 7.
Fig. 7 is a cross-sectional view of the semiconductor device shown in fig. 6 after an etching process according to various embodiments of the invention. An etching process such as dry etching is performed on the semiconductor device 100. The result is that the exposed portions of the dielectric layer 402 are removed according to the pattern shown in fig. 6. The etching of the dielectric layer 402 is more precisely controlled with the aid of the etch stop layer 302. As shown in fig. 7, the etching process creates an opening 702 above the lower drain contact 128.
One advantageous feature of having the etch stop layer 302 is that the high selectivity of the etch stop layer 302 helps to avoid over-etch (over-etch) problems, thereby protecting the top surface of the lower drain contact 128 from damage when applying an etch process to the dielectric layer 402.
Fig. 8 is a cross-sectional view of the semiconductor device shown in fig. 7 after removing the remaining photoresist layer from the semiconductor device, in accordance with various embodiments of the present invention. The remaining photoresist layer shown in fig. 7 may be removed by a suitable photoresist stripping technique such as chemical solvent cleaning (chemical solvent cleaning), plasma ashing (plasma ashing), dry stripping (dry stripping), and/or the like. Photoresist stripping techniques are well known and therefore their details are not discussed in detail herein to avoid repetition.
Fig. 9 is a cross-sectional view of the semiconductor device shown in fig. 8 after an etch process is performed on the etch stop layer 302, in accordance with various embodiments of the present invention. The exposed etch stop layer 302 (shown in fig. 8) may be removed by using a suitable etching process, such as a wet etch, a dry etch, and/or the like.
In some embodiments, the exposed etch stop layer 302 is removed by a wet etch process, wherein a cleaning fluid is applied to the etch stop layer 302. In some embodiments, the cleaning solution is a hydrofluoric acid (HF) -based cleaning solution, an ammonia (NH) -based cleaning solution, or a combination thereof4OH), a hydroxylamine based (hydroxylamine), any combination thereof, and the like.
The semiconductor device 100 may be heated prior to the process of applying a cleaning fluid to the etch stop layer 302. In one embodiment, the semiconductor device 100 is heated to about 40 ℃. The time to remove the exposed etch stop layer 302 is about 30 seconds. In an alternative embodiment, the semiconductor device 100 is heated to about 60 ℃. The time to remove the exposed etch stop layer 302 is about 10 seconds.
To have an enlarged opening, the etch process is controlled to remove portions of the protective layers 127, 129 and the dielectric layer 402. Specifically, after the etching process is completed, the first edge 902 of the dielectric layer 402 is vertically aligned with the outermost edge of the first gate spacer 125, as indicated by the dashed line a-a'. Similarly, as shown by dashed line B-B', a second edge 904 of the dielectric layer 402 is vertically aligned with the outermost edge of the second gate spacer 126. In an alternative embodiment, the first edge 902 of the dielectric layer 402 is substantially aligned with the first gate spacer 125. A second edge 904 of the dielectric layer 402 is substantially aligned with the second gate spacer 126.
In addition, the top surface of the first protection layer 127 has a first slope extending downward from the edge of the top surface of the first gate spacer 125, and the top surface of the second protection layer 129 has a second slope extending downward from the edge of the top surface of the second gate spacer 126. As shown in fig. 9, the rate of change of the top surface of the first protective layer 127 is substantially equal to the rate of change of the top surface of the second protective layer 129.
It should be noted that the protective layers 127 and 129 are formed by a high temperature deposition process. As described above and in fig. 2, the protective layers 127 and 129 are formed by the ALD process and a pre-heat treatment to increase the temperature of the ALD process to about 550 ℃ to about 600 ℃. Conversely, the dielectric layer 402 is formed by a CVD process with a process temperature of about 500 ℃. When applying a wet etch process to the capping layer and the dielectric layer 402, different deposition processes result in different etch rates. This etch rate difference helps to form different surfaces on the protective layer and the dielectric layer 402.
After the etching process is completed, an opening 901 is formed in the lower drain contact 128. The opening 901 includes two portions. The first portion of the opening 901 is rectangular. The first portion is located in the dielectric layer 402. The second portion of the opening 901 is an inverted trapezoid. As shown in fig. 9, a second portion of the opening 901 is located in the ild layer 120. The width of the first portion defining the opening 901 is W4. Throughout the description, W4 may be referred to as the maximum width of opening 901.
As shown in fig. 9, a portion of the dielectric layer 402 is removed during the etching process. The sidewalls of dielectric layer 402 are aligned with the sidewalls of gate spacers 125 and 126, respectively. As such, W4 is greater than W3, as shown in fig. 9. In some embodiments, the ratio of W4 to W3 is between about 1.1 to about 1.3.
Fig. 10 is a cross-sectional view of the semiconductor device shown in fig. 9 after filling the opening of the semiconductor device with a metal material according to various embodiments of the present invention. A metal material comprising tungsten, titanium, aluminum, copper, combinations thereof, and/or the like is filled in the opening 901 (as shown in fig. 9). Thus, an upper drain contact 130 is formed on the lower drain contact 128.
As shown in fig. 10, the upper drain contact 130 includes an upper portion and a lower portion. The upper portion of the upper drain contact 130 is rectangular. The lower portion of the upper drain contact 130 is an inverted trapezoid. In addition, the lower portion of the upper drain contact 130 contacts the first slope of the first protective layer 127 and the second slope of the second protective layer 129. The first edge of the upper portion of the upper drain contact 130 is vertically aligned with the outermost edge of the first gate spacer 125. The second edge of the upper portion of the upper drain contact 130 is vertically aligned with the outermost edge of the second gate spacer 126.
Fig. 11 is a flow chart depicting a method of forming the semiconductor device shown in fig. 1, in accordance with various embodiments of the present invention. This flowchart is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize that many variations, alternatives, and modifications are possible. For example, various steps shown in fig. 11 may be added, removed, replaced, rearranged, and repeated.
In step 1102, a semiconductor device including two transistors having a common drain is provided. A lower drain contact has been formed in the interlayer dielectric between the two gates of the two transistors. Openings are formed in the interlayer dielectric layer and over the lower drain contact.
At step 1104, an etch stop layer is deposited in the opening and on the top surface of the interlayer dielectric layer. The etching stop layer is made of aluminum oxynitride (AlON) and aluminum oxide (Al)2O3) Aluminum nitride (AlN), hafnium oxide (HfO)x) Zirconium oxide (ZrO)x) And/or combinations thereof, and the like.
At step 1106, a dielectric layer is formed over the etch stop layer. The dielectric layer is formed from silicon nitride. A dielectric layer is in the opening and on the interlayer dielectric layer.
At step 1108, a photoresist layer is deposited over the dielectric layer. At step 1110, the photoresist layer is exposed according to a predetermined pattern. In step 1112, an opening is formed in the photoresist layer by applying a developer to the photoresist layer.
At step 1114, an etch process is performed on the dielectric layer until the etch stop layer is exposed. In step 1116, the remaining photoresist layer is removed by a suitable photoresist removal process.
At step 1118, the exposed etch stop layer is removed by a suitable etch process. In the process of removing the etch stop layer, the upper portion of the protective layer and a portion of the dielectric layer are removed. Specifically, the etch process is controlled such that a first edge of the dielectric layer is vertically aligned with the sidewall spacers of the first transistor; a second edge of the dielectric layer is vertically aligned with the sidewall spacer of the second transistor; the top surface of the first protective layer has a slope extending downward from an edge of the top surface of the first gate spacer of the first transistor; the top surface of the second protective layer has a slope extending downward from an edge of the top surface of the second gate spacer of the second transistor.
In step 1120, a conductive material is filled in the opening by an electroplating process to form an upper drain contact. An upper drain contact is positioned above and in contact with the lower drain contact.
Fig. 12 is a cross-sectional view depicting a FinFET semiconductor device having an enlarged drain/source contact, in accordance with various embodiments of the present invention. The drain contact process shown in fig. 2-11 applies not only to planar transistor devices, but also to FinFET devices. FinFET device 1200 includes two transistors that share a common drain. The two transistors are formed on a substrate 104. The first transistor 101 includes a first gate 123 and its gate dielectric layer 121, a drain 114 and its contacts 128 and 130, and a first source 112 and its contacts (not shown). The second transistor 102 includes a second gate 124 and its gate dielectric layer 122, a drain 114 and its contacts 128 and 130, and a second source 116 and its contacts (not shown).
The source/ drain regions 112, 114, and 116 may be formed by etching portions of the fin lines and growing the source/ drain regions 112, 114, and 116 by a suitable epitaxial growth process. As shown in fig. 12, the top surfaces of source/ drain regions 112, 114, and 116 are higher than the bottom surfaces of gates 123 and 124.
The shape of the upper drain contact 130 in fig. 12 is similar to that shown in fig. 1 and will not be discussed in detail herein to avoid unnecessary repetition. One advantageous feature of having an enlarged drain contact 130 as shown in fig. 12 is that the enlarged drain contact helps to reduce contact resistance, thereby improving the performance of the FinFET semiconductor device 1200.
According to an embodiment, a method of fabricating a contact structure includes: forming a first transistor and a second transistor on a substrate, wherein the first transistor and the second transistor share a source/drain region formed between a first gate of the first transistor and a second gate of the second transistor; forming an opening in an interlayer dielectric layer between the first gate and the second gate; depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer; depositing a dielectric layer on the etch stop layer; depositing a photoresist layer on the dielectric layer; patterning the photoresist layer to form a second opening in the photoresist layer, wherein an outermost edge of the second opening is aligned with an outermost edge of the first opening; performing a first etching process on the dielectric layer until the etching stop layer is exposed; performing a second etching process on the etching stop layer until an exposed portion of the etching stop layer and portions of the dielectric layer are removed to form a third opening, wherein a maximum width of the third opening is greater than a maximum width of the second opening; and filling the third opening with a conductive material.
According to an embodiment, a method of fabricating a contact structure includes: forming a first transistor and a second transistor on a substrate, wherein: the first transistor comprises a first source electrode, a first grid electrode and a drain electrode; and the second transistor comprises a second source, a second grid and the drain.
The method further includes forming a first protective layer and a second protective layer along the sidewall spacers of the first transistor and the second transistor, respectively, wherein the first protective layer and the second protective layer are between the first gate and the second gate and on the drain; forming a lower drain electrode in contact with an interlayer dielectric layer and between the first grid electrode and the second grid electrode; forming a first opening in the interlayer dielectric layer and on the lower drain contact; depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer; depositing a dielectric layer on the etch stop layer; performing a first etching process on the dielectric layer until the etching stop layer is exposed; performing a second etching process on the etching stop layer until an exposed portion of the etching stop layer and a portion of the dielectric layer are removed to form a second opening, wherein a width of an upper portion of the second opening is greater than a width of an upper portion of the first opening; and filling the second opening with a conductive material.
According to an embodiment, a contact structure apparatus includes: a first source and a common drain on opposite sides of a first gate; a second source and the common drain on opposite sides of a second gate, wherein: the first grid and the second grid are positioned in an interlayer dielectric layer on a substrate; and the first gate and the second gate are surrounded by a first gate spacer and a second gate spacer, respectively.
The apparatus further includes a first passivation layer formed along a sidewall of the first gate spacer, wherein the first passivation layer is on the common drain and a top surface of the first passivation layer has a first slope; a second passivation layer formed along a sidewall of the second gate spacer, wherein the second passivation layer is on the common drain and has a second slope on a top surface thereof; and a first drain contact formed between the first gate and the second gate, wherein an upper portion of the first drain contact has a width greater than a lower portion of the first drain contact. A method of fabricating a contact structure according to some embodiments of the present invention further comprises: before the step of forming the first opening in the interlayer dielectric layer, a lower drain is formed in the interlayer dielectric layer and between the first gate and the second gate.
The method for manufacturing a contact structure according to an embodiment of the present invention further includes: before the step of forming the first opening in the interlayer dielectric layer, a lower drain is formed in the interlayer dielectric layer and between the first gate and the second gate.
The method for manufacturing a contact structure according to an embodiment of the present invention further includes: filling the third opening with the conductive material to form an upper drain contact, wherein a bottom surface of the upper drain contact is in contact with a top surface of the lower drain contact.
The method for manufacturing a contact structure according to an embodiment of the present invention further includes: forming a first passivation layer along a sidewall spacer of the first transistor prior to the step of forming the first opening in the interlayer dielectric layer; and forming a second passivation layer along a sidewall spacer of the second transistor.
A method for fabricating a contact structure according to an embodiment of the present invention, wherein: after the step of performing the second etching process on the etch stop layer, a first edge of the first passivation layer is vertically aligned with an outermost edge of the sidewall spacer of the first transistor; and a second edge of the dielectric layer is vertically aligned to an outermost edge of the sidewall spacer of the second transistor.
A method for fabricating a contact structure according to an embodiment of the present invention, wherein: after the step of performing the second etching process on the etch stop layer, a top surface of the first passivation layer has a first slope extending downward from an edge of a top surface of the sidewall spacer of the first transistor; and a top surface of the second passivation layer has a second slope extending downward from an edge of a top surface of the sidewall spacer of the second transistor.
A method for fabricating a contact structure according to an embodiment of the present invention, wherein: the etch stop layer is formed of aluminum oxynitride.
A method for fabricating a contact structure according to an embodiment of the present invention, wherein: the dielectric layer is formed of silicon nitride.
The method for manufacturing a contact structure according to an embodiment of the present invention further includes: filling the third opening with the conductive material to form an upper drain contact, wherein the upper drain contact comprises a first portion of an inverted trapezoid and a second portion of a rectangle.
A method for fabricating a contact structure according to an embodiment of the present invention, wherein: the first portion of the upper drain contact is in the interlayer dielectric layer and between the first gate and the second gate; and the second portion of the upper drain contact is in the dielectric layer.
The method for manufacturing a contact structure according to another embodiment of the present invention further includes: depositing a photoresist layer on the dielectric layer before the first etching process is performed on the dielectric layer; and patterning the photoresist layer to form a third opening in the photoresist layer, wherein an outermost edge of the third opening is substantially aligned with an outermost edge of the first opening.
The method for manufacturing a contact structure according to another embodiment of the present invention further includes: after performing the second etch process on the etch stop layer, removing the portion of the dielectric layer such that: a first edge of the dielectric layer is aligned with an outermost edge of the sidewall spacer of the first transistor; and a second edge of the dielectric layer is aligned with an outermost edge of the sidewall spacer of the second transistor.
The method for manufacturing a contact structure according to another embodiment of the present invention further includes: after the step of performing the second etching process on the etching stop layer, removing a portion of the first protective layer and the second protective layer such that: a top surface of the first passivation layer has a first slope extending downward from an edge of a top surface of the sidewall spacer of the first transistor; and a top surface of the second passivation layer has a second slope extending downward from an edge of a top surface of the sidewall spacer of the second transistor.
The method for manufacturing a contact structure according to another embodiment of the present invention further includes: filling the second opening with a conductive material to form an upper drain contact, wherein: the first protective layer is contacted between the upper drain electrode and the first grid electrode; the second protective layer is contacted between the upper drain electrode and the second grid electrode; and an upper portion of the upper drain contact has a width greater than a width of a lower portion of the upper drain contact.
The contact structure apparatus according to still another embodiment of the present invention, further comprising: a second drain contact formed between the common drain and the first drain contact, wherein the second drain contact has an inverted trapezoidal shape.
The contact structure apparatus according to still another embodiment of the present invention, wherein: a rate of change of the top surface of the first passivation layer is substantially the same as a rate of change of the top surface of the second passivation layer.
The contact structure apparatus according to still another embodiment of the present invention, wherein: the upper portion of the first drain contact has a rectangular shape; and the lower portion of the first drain contact has an inverted trapezoid shape, and wherein: the lower part of the first drain contact is in contact with the first slope and the second slope; a first edge of the upper portion of the first drain contact is vertically aligned with an outermost edge of the first gate spacer; and a second edge of the upper portion of the second drain contact is vertically aligned with an outermost edge of the second gate spacer.
The contact structure apparatus according to still another embodiment of the present invention, wherein: a ratio of a width of the upper portion of the first drain contact to a minimum width between the first protective layer and the second protective layer is between about 1.1 and about 1.3.
The foregoing outlines features of many embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art may readily devise many other varied processes and structures that are equally effective to achieve the same objectives and/or achieve the same advantages of the embodiments of the invention. It should also be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention and that such equivalents are not to be construed as beyond the spirit and scope of the invention.

Claims (33)

1. A method of fabricating a contact structure, comprising:
forming a first transistor and a second transistor on a substrate, wherein the first transistor and the second transistor share a source/drain region formed between a first gate of the first transistor and a second gate of the second transistor;
forming a first passivation layer along a sidewall spacer of the first transistor;
forming a second passivation layer along a sidewall spacer of the second transistor;
forming a first opening in an interlayer dielectric layer between the first gate and the second gate;
depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer;
depositing a dielectric layer on the etch stop layer;
depositing a photoresist layer on the dielectric layer;
patterning the photoresist layer to form a second opening in the photoresist layer, wherein an outermost edge of the second opening is aligned with an outermost edge of the first opening;
performing a first etching process on the dielectric layer until the etching stop layer is exposed;
performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer are removed to form a third opening, wherein a maximum width of the third opening is greater than a maximum width of the second opening, a first edge of the first protective layer is vertically aligned with an outermost edge of the sidewall spacer of the first transistor, and a second edge of the dielectric layer is vertically aligned with an outermost edge of the sidewall spacer of the second transistor; and
filling the third opening with a conductive material.
2. The method of manufacturing a contact structure of claim 1, further comprising: before the step of forming the first opening in the interlayer dielectric layer, a lower drain is formed in the interlayer dielectric layer and between the first gate and the second gate.
3. The method of manufacturing a contact structure of claim 2, further comprising: filling the third opening with the conductive material to form an upper drain contact, wherein a bottom surface of the upper drain contact is in contact with a top surface of the lower drain contact.
4. The method of manufacturing a contact structure according to claim 1, wherein:
after the step of performing the second etching process on the etch stop layer, a top surface of the first passivation layer has a first slope extending downward from an edge of a top surface of the sidewall spacer of the first transistor; and
a top surface of the second passivation layer has a second slope extending downward from an edge of a top surface of the sidewall spacer of the second transistor.
5. The method of manufacturing a contact structure according to claim 1, wherein:
the etch stop layer is formed of aluminum oxynitride.
6. The method of manufacturing a contact structure according to claim 1, wherein:
the dielectric layer is formed of silicon nitride.
7. The method of manufacturing a contact structure of claim 1, further comprising:
filling the third opening with the conductive material to form an upper drain contact, wherein the upper drain contact comprises a first portion of an inverted trapezoid and a second portion of a rectangle.
8. The method of manufacturing a contact structure according to claim 7, wherein:
the first portion of the upper drain contact is in the interlayer dielectric layer and between the first gate and the second gate; and
the second portion of the upper drain contact is in the dielectric layer.
9. A method of fabricating a contact structure, comprising:
forming a first transistor and a second transistor on a substrate, wherein:
the first transistor comprises a first source electrode, a first grid electrode and a drain electrode; and
the second transistor comprises a second source electrode, a second grid electrode and the drain electrode;
forming a first protective layer and a second protective layer along the sidewall spacers of the first transistor and the second transistor, respectively, wherein the first protective layer and the second protective layer are between the first gate and the second gate and on the drain;
forming a lower drain electrode in contact with an interlayer dielectric layer and between the first grid electrode and the second grid electrode;
forming a first opening in the interlayer dielectric layer and on the lower drain contact;
depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer;
depositing a dielectric layer on the etch stop layer;
performing a first etching process on the dielectric layer until the etching stop layer is exposed;
performing a second etch process on the etch stop layer until an exposed portion of the etch stop layer and a portion of the dielectric layer are removed to form a second opening, wherein a width of an upper portion of the second opening is greater than a width of an upper portion of the first opening, and the second etch process removes the portion of the dielectric layer such that a first edge of the dielectric layer is vertically aligned with an outermost edge of the sidewall spacer of the first transistor and a second edge of the dielectric layer is vertically aligned with an outermost edge of the sidewall spacer of the second transistor; and
the second opening is filled with a conductive material.
10. The method of manufacturing a contact structure of claim 9, further comprising:
depositing a photoresist layer on the dielectric layer before the first etching process is performed on the dielectric layer; and
the photoresist layer is patterned to form a third opening in the photoresist layer, wherein an outermost edge of the third opening is substantially aligned with an outermost edge of the first opening.
11. The method of manufacturing a contact structure of claim 9, further comprising:
after the step of performing the second etching process on the etching stop layer, removing a portion of the first protective layer and the second protective layer such that:
a top surface of the first passivation layer has a first slope extending downward from an edge of a top surface of the sidewall spacer of the first transistor; and
a top surface of the second passivation layer has a second slope extending downward from an edge of a top surface of the sidewall spacer of the second transistor.
12. The method of manufacturing a contact structure of claim 9, further comprising:
filling the second opening with a conductive material to form an upper drain contact, wherein:
the first protective layer is contacted between the upper drain electrode and the first grid electrode;
the second protective layer is contacted between the upper drain electrode and the second grid electrode; and
an upper portion of the upper drain contact has a width greater than a width of a lower portion of the upper drain contact.
13. A semiconductor device, comprising:
a first source and a common drain on both sides of a first gate;
a second source and the common drain on both sides of a second gate, wherein:
the first grid and the second grid are positioned in an interlayer dielectric layer on a substrate; and
the first gate and the second gate are surrounded by a first gate spacer and a second gate spacer, respectively;
a first passivation layer formed along a sidewall of the first gate spacer, wherein the first passivation layer is on the common drain and a top surface of the first passivation layer has a first slope;
a second passivation layer formed along a sidewall of the second gate spacer, wherein the second passivation layer is on the common drain and has a second slope on a top surface thereof; and
a first drain contact formed between the first gate and the second gate, wherein an upper portion of the first drain contact has a width greater than a width of a lower portion of the first drain contact,
the upper portion of the first drain contact has a rectangular shape;
the lower portion of the first drain contact has an inverted trapezoidal shape, and wherein:
the lower part of the first drain contact is in contact with the first slope and the second slope;
a first edge of the upper portion of the first drain contact is vertically aligned with an outermost edge of the first gate spacer; and
a second edge of the upper portion of a second drain contact is vertically aligned with an outermost edge of the second gate spacer.
14. The semiconductor device of claim 13, wherein said second drain contact is formed between said common drain and said first drain contact, wherein said second drain contact has an inverted trapezoidal shape.
15. The semiconductor device of claim 13, wherein:
a rate of change of the top surface of the first passivation layer is the same as a rate of change of the top surface of the second passivation layer.
16. The semiconductor device of claim 13, wherein:
the ratio of the width of the upper portion of the first drain contact to the minimum distance between the first protective layer and the second protective layer is between 1.1 and 1.3.
17. A method of fabricating a contact structure, comprising:
forming a first transistor and a second transistor on a substrate, wherein the first transistor and the second transistor share a common drain formed between a first gate of the first transistor and a second gate of the second transistor;
forming a first passivation layer along a sidewall spacer of the first transistor;
forming a second passivation layer along a sidewall spacer of the second transistor;
forming a first trench between the first gate and the second gate, wherein the first trench is above a contact of the common drain;
depositing an etch stop layer in the first trench;
depositing a dielectric layer over the etch stop layer;
patterning a photoresist layer over the dielectric layer to form a second trench in the photoresist layer;
performing a first etching process on the dielectric layer until the etching stop layer is exposed;
forming a third trench over the contact of the common drain by performing a second etch process on the etch stop layer until a top surface of the contact of the common drain is exposed, a first edge of the first protective layer being vertically aligned with an outermost edge of the sidewall spacer of the first transistor, a second edge of the dielectric layer being vertically aligned with an outermost edge of the sidewall spacer of the second transistor; and
filling the third trench with a conductive material.
18. The method of manufacturing a contact structure of claim 17, wherein:
an outermost edge of the second trench is aligned with an outermost edge of the first trench.
19. The method of manufacturing a contact structure of claim 17, further comprising:
the contact of the common drain extends from the common drain to a top surface of the dielectric layer after filling the third trench with the conductive material.
20. The method of claim 19, wherein said second etch process is performed on said etch stop layer until after said top surface of said contact of said common drain is exposed:
a top surface of the first passivation layer has a first slope; and
a top surface of the second passivation layer has a second slope.
21. The method of manufacturing a contact structure of claim 20, wherein:
an upper portion of the contact of the common drain has a rectangular shape; and
a lower portion of the contact of the common drain has an inverted trapezoid shape, and the lower portion of the contact of the common drain is in contact with the first slope and the second slope.
22. A semiconductor device, comprising:
a first source and a common drain in a substrate and on both sides of a first gate surrounded by a first gate spacer;
a second source, the second source and the common drain being in the substrate and on both sides of a second gate, the second gate being surrounded by a second gate spacer;
a first passivation layer formed along a sidewall of the first gate spacer, wherein a top surface of the first passivation layer has a first slope extending downward from an edge of a top surface of a sidewall of the first gate spacer;
a second passivation layer formed along a sidewall of the second gate spacer, wherein a top surface of the second passivation layer has a second slope extending downward from an edge of a top surface of a sidewall of the second gate spacer;
a lower drain contact formed between the first gate and the second gate; and
an upper drain contact formed above the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first ramp and the second ramp.
23. The semiconductor device of claim 22, wherein:
the lower drain contact has an inverted trapezoidal shape.
24. The semiconductor device of claim 22, wherein:
a sidewall of the first passivation layer is vertically aligned with a first sidewall of the common drain.
25. The semiconductor device of claim 22, wherein:
a sidewall of the second passivation layer is vertically aligned with a second sidewall of the common drain.
26. The semiconductor device of claim 22, wherein:
the first gate, the second gate, the lower drain contact, and the upper drain contact are in an interlayer dielectric layer over the substrate.
27. The semiconductor device according to claim 26, further comprising:
an etch stop layer over the interlayer dielectric layer, wherein the etch stop layer is formed of aluminum oxynitride.
28. The semiconductor device according to claim 27, further comprising:
a dielectric layer over and contacting the etch stop layer.
29. The semiconductor device of claim 28, wherein:
the upper drain contact includes a first portion having an inverted trapezoidal shape and a second portion having a rectangular shape.
30. The semiconductor device of claim 29, wherein:
the first portion of the upper drain contact is located in the interlayer dielectric layer and between the first gate and the second gate; and
the second portion of the upper drain contact extends along the etch stop layer and the dielectric layer.
31. A semiconductor device, comprising:
a first source/drain region and a second source/drain region in a substrate and on both sides of a first gate, wherein the second source/drain region and the first gate are separated by a first gate spacer;
a third source/drain region, wherein the second source/drain region and the third source/drain region are in the substrate and on both sides of a second gate, the second source/drain region and the second gate separated by a second gate spacer;
a first passivation layer formed along a sidewall of the first gate spacer, wherein the first passivation layer is over the second source/drain region, a top surface of the first passivation layer having a first slope extending downward from an edge of a top surface of a sidewall of the first gate spacer;
a second passivation layer formed along a sidewall of the second gate spacer, wherein the second passivation layer is over the second source/drain region, a top surface of the second passivation layer having a second slope extending downward from an edge of a top surface of a sidewall of the second gate spacer;
a lower drain contact located between the first protective layer and the second protective layer; and
and an upper drain contact located above the lower drain contact and between the first gate and the second gate, wherein the upper drain contact has a width greater than that of the lower drain contact.
32. The semiconductor device of claim 31, wherein:
the first source/drain region is the source of a first transistor;
the third source/drain region is the source of a second transistor; and
the second source/drain region is a drain shared by the first transistor and the second transistor.
33. The semiconductor device according to claim 31, further comprising:
an etch stop layer over the first gate and the second gate; and
a dielectric layer located above the etching stop layer.
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US20200402859A1 (en) 2020-12-24
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US11282750B2 (en) 2022-03-22
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