CN216563122U - Semiconductor device with a plurality of transistors - Google Patents

Semiconductor device with a plurality of transistors Download PDF

Info

Publication number
CN216563122U
CN216563122U CN202122955720.1U CN202122955720U CN216563122U CN 216563122 U CN216563122 U CN 216563122U CN 202122955720 U CN202122955720 U CN 202122955720U CN 216563122 U CN216563122 U CN 216563122U
Authority
CN
China
Prior art keywords
diode
semiconductor device
transient suppression
substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202122955720.1U
Other languages
Chinese (zh)
Inventor
李颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Huiding Electronic Technology Co ltd
Original Assignee
Wuxi Huiding Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Huiding Electronic Technology Co ltd filed Critical Wuxi Huiding Electronic Technology Co ltd
Priority to CN202122955720.1U priority Critical patent/CN216563122U/en
Application granted granted Critical
Publication of CN216563122U publication Critical patent/CN216563122U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes: a transient suppression chip; the low-capacitance chip comprises a second diode and a third diode, wherein the output end of the second diode is connected with the input end of the third diode, and the output end of the third diode is connected with the input end of the second diode; the output end of the transient suppression chip is connected with the input end of the second diode, the input end of the transient suppression chip is a first external connection end of the semiconductor device, and the output end of the second diode is a second external connection end of the semiconductor device. The present disclosure enables a semiconductor device to have surge protection capability and low capacitance characteristics.

Description

Semiconductor device with a plurality of transistors
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device.
Background
With the rapid development of science and technology, semiconductor devices are widely used in social production and life. However, the conventional semiconductor device cannot have both surge protection capability and low capacitance characteristic.
Disclosure of Invention
An object of the present disclosure is to provide a semiconductor device capable of providing surge protection capability and low capacitance characteristics.
According to an aspect of the present disclosure, there is provided a semiconductor device including:
a transient suppression chip;
the low-capacitance chip comprises a second diode and a third diode, wherein the output end of the second diode is connected with the input end of the third diode, and the output end of the third diode is connected with the input end of the second diode;
the output end of the transient suppression chip is connected with the input end of the second diode, the input end of the transient suppression chip is a first external connection end of the semiconductor device, and the output end of the second diode is a second external connection end of the semiconductor device.
Further, the transient suppression chip has a unidirectional TVS structure; or
The transient suppression chip is provided with a bidirectional TVS structure; or
The transient suppression chip is provided with a plurality of unidirectional TVS structures, one ends of the unidirectional TVS structures are connected with the input end of the second diode, and the other ends of the unidirectional TVS structures form a plurality of first external connection ends of the semiconductor device; or
The transient suppression chip is provided with a plurality of bidirectional TVS structures, one ends of the bidirectional TVS structures are connected with the input end of the second diode, and the other ends of the bidirectional TVS structures form a plurality of first external connecting ends of the semiconductor device.
Further, the transient suppression chip has a unidirectional TVS structure; or
The transient suppression chip is provided with a bidirectional TVS structure; or
The transient suppression chip is provided with a plurality of unidirectional TVS structures, one ends of the unidirectional TVS structures are connected with the input end of the second diode, and the other ends of the unidirectional TVS structures form a plurality of first external connection ends of the semiconductor device; or
The transient suppression chip is provided with a plurality of bidirectional TVS structures, one ends of the bidirectional TVS structures are connected with the input end of the second diode, and the other ends of the bidirectional TVS structures form a plurality of first external connection ends of the semiconductor device;
the unidirectional TVS structure or the bidirectional TVS structure is a PN junction structure, a PNP structure, an NPN structure, a NPNP silicon controlled structure, a PNPN silicon controlled structure, an NPNPNPN silicon controlled structure or a PNPNPNP silicon controlled structure.
Further, the transient suppression chip includes one or more first diodes, the first diodes including:
a first substrate of a first conductivity type, the first substrate having opposite first and second surfaces, the first surface being provided with one or more first implanted regions of a second conductivity type;
a first electrode covering the first injection region, the first electrode constituting a first external connection terminal of the semiconductor device;
and the second electrode covers the second surface and is electrically connected with the input end of the second diode.
Further, the transient suppression chip comprises one or more diode components, each diode component comprises two first diodes which are connected in reverse series, one end of each first diode which is connected in reverse series is connected with the input end of the corresponding second diode, and the other end of each first diode which is connected in reverse series forms a first external connection end of the semiconductor device;
the diode assembly includes:
a first substrate of a first conductivity type, the first substrate having opposing first and second surfaces;
the epitaxial layer comprises an epitaxial region of the second conductivity type and a doped region of the first conductivity type; the epitaxial region and the doped region are arranged in a stacked mode, and the epitaxial region is arranged on the first surface;
a first electrode covering the doped region, the first electrode constituting a first external connection terminal of the semiconductor device;
and the second electrode covers the second surface and is electrically connected with the input end of the second diode.
Further, the low capacitance chip includes:
the surface of the second substrate is provided with two second injection regions of a second conductivity type and two third injection regions of a first conductivity type, and the doping concentration of the third injection regions is greater than that of the second substrate; the two second injection regions are connected with the two third injection regions in a one-to-one correspondence manner; the second substrate, one of the second implanted regions, and one of the third implanted regions constitute the second diode; the second substrate, another of the second implant regions, and another of the third implant regions constitute the third diode.
Further, the second implantation region and the third implantation region constituting the second diode are located on one surface of the second substrate, and the second implantation region and the third implantation region constituting the third diode are located on the other surface of the second substrate; or
The two second implantation regions and the two third implantation regions are located on the same surface of the second substrate.
Further, the semiconductor device includes:
the transient suppression chip is arranged on the first bearing plate;
the second bearing plate is arranged at an interval with the first bearing plate, and the low-capacitance chip is arranged on the second bearing plate;
the first bearing plate is a conductor, the output end of the transient suppression chip is connected with the first bearing plate, and the first bearing plate is connected with the input end of the second diode through a lead.
The semiconductor device comprises the transient suppression chip, so that the semiconductor device has super surge protection capability; the semiconductor device also comprises a low-capacitance chip, wherein the low-capacitance chip comprises a second diode and a third diode which are connected in parallel in an inverse mode, and therefore the semiconductor device has the characteristic of low capacitance; meanwhile, the surge protection capability and the low capacitance characteristic of the semiconductor device are synchronously optimized under the condition that the size of the chip is not changed; moreover, the manufacturing method of the semiconductor device reduces the manufacturing cost, further improves the surge protection capability and further reduces the low-capacitance characteristic.
Drawings
Fig. 1 is a schematic diagram of a semiconductor device of an embodiment of the present disclosure.
Fig. 2 is an equivalent circuit diagram of the structure shown in fig. 1.
Fig. 3 is another equivalent circuit diagram of the structure shown in fig. 1.
Fig. 4 is a schematic view after a first masking layer is formed in a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 5 is a schematic view after a first implantation region is formed in a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 6 is a schematic view after a second masking layer is formed in the method of manufacturing a semiconductor device according to the embodiment of the present disclosure.
Fig. 7 is a schematic view after forming a first electrode and a second electrode in the method of manufacturing a semiconductor device according to the embodiment of the present disclosure.
Fig. 8 is a schematic perspective view of a transient suppression chip in a semiconductor device according to an embodiment of the disclosure.
Fig. 9 is a schematic view after an epitaxial layer is formed in the method of manufacturing a semiconductor device according to the embodiment of the present disclosure.
Fig. 10 is a schematic view after forming an isolation trench in the method of manufacturing a semiconductor device according to the embodiment of the present disclosure.
Fig. 11 is a schematic view after a fourth masking layer is formed in the method of manufacturing a semiconductor device according to the embodiment of the present disclosure.
Fig. 12 is a schematic view after a second lead hole is formed in the method of manufacturing a semiconductor device according to the embodiment of the present disclosure.
Fig. 13 is a schematic view after a transient suppression chip is formed in the method of manufacturing a semiconductor device according to the embodiment of the present disclosure.
Fig. 14 is a schematic diagram of a low capacitance chip of an embodiment of the disclosure.
Fig. 15 is a schematic perspective view of a low-capacitance chip according to an embodiment of the present disclosure.
Description of reference numerals: 1. a first substrate; 2. a first masking layer; 201. a first implantation window; 3. a first implanted region; 4. a second masking layer; 401. a first lead hole; 5. a first electrode; 6. a second electrode; 7. an epitaxial layer; 701. an epitaxial region; 702. a doped region; 8. a third masking layer; 9. a fourth masking layer; 10. an isolation structure; 11. an isolation trench; 12. a second lead hole; 13. a second substrate; 1301. a second implanted region; 1302. a third implanted region; 14. a fifth masking layer; 15. a sixth masking layer; 16. a third electrode; 17. a fourth electrode; 18. welding the layers; 19. an insulating structure; 20. an output electrode; 21. an input electrode; 22. a first bearing plate; 23. a second carrier plate; 100. a transient suppression chip; 200. a low capacitance chip; z1, a first diode; d1, a second diode; d2, a third diode.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in the description and claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The embodiment of the disclosure provides a preparation method of a semiconductor device. As shown in fig. 1 to 3, the method for manufacturing a semiconductor device may include steps S10 to S20, wherein:
step S10, forming the transient suppression chip 100, where the transient suppression chip 100 includes a first diode Z1.
Step S20, forming a low-capacitance chip 200, wherein the low-capacitance chip 200 includes a second diode D1 and a third diode D2, an output end of the second diode D1 is connected with an input end of a third diode D2, and an output end of the third diode D2 is connected with an input end of the second diode D1; the output terminal of the transient suppression chip 100 is connected to the input terminal of the second diode D1, the input terminal of the transient suppression chip 100 is a first external connection terminal of the semiconductor device, and the output terminal of the second diode D1 is a second external connection terminal of the semiconductor device.
According to the method for manufacturing the semiconductor device, the semiconductor device comprises the transient suppression chip 100, so that the semiconductor device has a surge protection function; the semiconductor device further comprises a low-capacitance chip 200, and because the junction capacitance of the second diode D1 and the junction capacitance of the third diode D2 in the low-capacitance chip 200 are both smaller than the junction capacitance of the first diode Z1, the second diode D1 and the third diode D2 which are connected in parallel in an opposite direction form a low-capacitance diode structure, and the semiconductor device has a low-capacitance characteristic.
The steps of the method for manufacturing a semiconductor device according to the embodiment of the present disclosure are explained in detail below:
in step S10, the transient suppression chip 100 is formed.
As shown in fig. 1-3, the transient suppression chip 100 may have one or more unidirectional TVS structures, and of course, the transient suppression chip 100 may also have one or more bidirectional TVS structures, but the disclosure is not limited thereto. The TVS structure is referred to as a transient suppression structure. Taking the transient suppression chip 100 with a plurality of unidirectional TVS structures as an example, one end of each of the plurality of unidirectional TVS structures is connected to the input terminal of the second diode D1, and the other end of each of the plurality of unidirectional TVS structures constitutes a first external connection terminal of the semiconductor device, that is, the other end of each of the unidirectional TVS structures constitutes a first external connection terminal of the semiconductor device. Taking the transient suppression chip 100 with a plurality of bidirectional TVS structures as an example, one end of each of the plurality of bidirectional TVS structures is connected to the input terminal of the second diode D1, and the other end of each of the plurality of bidirectional TVS structures constitutes a plurality of first external connection terminals of the semiconductor device.
In addition, the unidirectional TVS structure may be a PN junction structure, a PNP structure, an NPN structure, a thyristor structure of NPNP, a thyristor structure of PNPN, a thyristor structure of NPNPN, or a thyristor structure of PNPNP. The bidirectional TVS structure can be a PN junction structure, a PNP structure, an NPN structure, a NPNP silicon controlled structure, a PNPN silicon controlled structure, an NPNPN silicon controlled structure or a PNPNPNP silicon controlled structure.
Taking the transient suppression chip 100 having one or more unidirectional TVS structures as PN junction structures, the transient suppression chip 100 may include one or more first diodes Z1, the first diode Z1 is a transient suppression diode, and the junction capacitance of the second diode D1 and the junction capacitance of the third diode D2 are both smaller than the junction capacitance of the first diode Z1, based on which the step S10 may include:
step S101A, providing a first substrate 1 of a first conductivity type, the first substrate 1 having a first surface and a second surface opposite to each other, the first surface being provided with one or more first implanted regions 3 of a second conductivity type.
As shown in fig. 4, the first substrate 1 may be a silicon carbide substrate, or may be a silicon substrate, which is not limited in this embodiment. The first conductivity type may be N-type, but of course, may also be P-type. Taking the first conductive type as an N type as an example, the second conductive type is a P type; taking the first conductive type as P-type as an example, the second conductive type is N-type. The number of the first implantation regions 3 may be one or more, so that the transient suppression chip 100 has one or more unidirectional TVS structures. Taking the number of the first implantation regions 3 as an example, the plurality of first implantation regions 3 are arranged at intervals. Alternatively, the number of the first implantation regions 3 may be four, so that the transient suppression chip 100 has a unidirectional four-channel protection capability, but the disclosure does not limit this.
As shown in fig. 5, the forming process of the first implantation region 3 may include: forming a first masking layer 2 on a first surface of a first substrate 1; forming one or more first implantation windows 201 exposing a first surface on the first masking layer 2; ion implantation is performed through the plurality of first implantation windows 201 to form the first implantation regions 3. The material of the first masking layer 2 may be SiO2However, the present disclosure is not limited thereto. The first masking layer 2 may be formed by a thermal growth or deposition process. The first masking layer 2 may have a thickness of 2000 angstroms to 20000 angstroms. The present disclosure may form an implantation window on the first masking layer 2 through a photolithography process. In the ion implantation process, the implantation energy may be 30KEV-300KEV, and the implantation dose may be 1E13-1E 16. After ion implantation is completed, high temperature annealing at 1000-1200 deg.c is required.
After the high temperature annealing is completed, as shown in fig. 6, the present disclosure may form a second masking layer 4 on a surface of the first masking layer 2 facing away from the first substrate 1; a first wire hole 401 is formed in a region of the second masking layer 4 corresponding to the first injection window 201, and the first wire hole 401 communicates with the first window. The material of the second masking layer 4 may be SiO2But, however, doThe present disclosure is not limited thereto. The second masking layer 4 may be formed by a thermal growth or deposition process. The second masking layer 4 may have a thickness of 2000 angstroms to 20000 angstroms.
Step S102A, forming a first electrode 5 covering the first implantation region 3, the first electrode 5 constituting a first external connection terminal of the semiconductor device.
As shown in fig. 7 and 8, the material of the first electrode 5 may be AlSiCu. For example, the forming process of the first electrode 5 includes: forming a first electrode 5 material layer on the surface of the second masking layer 4 opposite to the first substrate 1, wherein the first electrode 5 material layer fills the first lead hole 401 and the first window and covers the first injection region 3; the first electrode 5 material layer is patterned to form a first electrode 5, and the first electrode 5 fills the first lead hole 401 and the first window and extends out of the first lead hole 401. The layer of the first electrode 5 material may be prepared by a sputtering process.
Step S103A, forming a second electrode 6 covering the second surface, the second electrode 6 being electrically connected to the input terminal of the second diode D1.
As shown in fig. 7 and 8, the second electrode may be prepared by thinning, back steaming, or the like.
Taking the example that the transient suppression chip 100 has one or more bidirectional TVS structures, and the bidirectional TVS structure is a PNP structure or an NPN structure, the transient suppression chip 100 may include one or more diode components, each diode component includes two first diodes Z1 connected in reverse series, one end of each of the two first diodes Z1 connected in reverse series is connected to an input end of the second diode D1, and the other end of each of the two first diodes Z1 connected in reverse series constitutes a first external connection end of the semiconductor device.
As shown in fig. 13, the diode assembly may include a first substrate 1 of a first conductivity type, an epitaxial layer 7, a first electrode 5, and a second electrode 6. The first substrate 1 may have opposite first and second surfaces. The epitaxial layer 7 may include an epitaxial region 701 of the second conductivity type and a doped region 702 of the first conductivity type. The epitaxial region 701 and the doped region 702 are stacked, and the epitaxial region 701 is disposed on the first surface. The first electrode 5 may cover the doped region 702, and the first electrode 5 constitutes a first external connection terminal of the semiconductor device. The second electrode 6 may cover the second surface and be electrically connected to an input terminal of the second diode D1. Based on this, step S10 may include:
step S101B, providing a first substrate 1 of a first conductivity type, the first substrate 1 having a first surface and a second surface opposite to each other.
As shown in fig. 9, the first substrate 1 may be a silicon carbide substrate, or may be a silicon substrate, which is not limited in this embodiment.
Step S102B, forming an epitaxial layer 7, where the epitaxial layer 7 includes an epitaxial region 701 of the second conductivity type and a doped region 702 of the first conductivity type; the epitaxial region 701 and the doped region 702 are stacked, and the epitaxial region 701 is disposed on the first surface.
As shown in fig. 9, forming the epitaxial layer 7 may include: forming an epitaxial material layer of a second conductive type on the first surface; ions of the second conductivity type are implanted in the surface of the layer of epitaxial material facing away from the first substrate 1 so that the layer of epitaxial material forms an epitaxial layer 7. The doped region 702 is formed in the region where the second conductive type ions are implanted, and the epitaxial region 701 is formed in the region where the second conductive type ions are not implanted. The epitaxial material layer may have a resistivity of 0.01 ohm cm to 0.1 ohm cm and a thickness of 3 μm to 20 μm. In the implantation of the ions of the second conductive type, the implantation energy may be 30KEV-300KEV and the implantation dose may be 1E13-1E 16. After ion implantation is finished, high-temperature annealing is required to be carried out at 1000-1200 ℃, and the annealing time is 30-600 min.
Step S103B, forming a first electrode 5 covering the doped region 702, the first electrode 5 constituting a first external connection terminal of the semiconductor device.
As shown in fig. 10, before forming the first electrode 5, the present disclosure may include: forming a third masking layer 8 on the surface of the epitaxial layer 7 opposite to the first substrate 1; forming one or more etching windows exposing the epitaxial layer 7 on the third masking layer 8; with the third masking layer 8 as a mask, etching is performed through the etching window to form an isolation Trench 11(Trench isolation Trench 11). The bottom of the isolation trench 11 extends into the first substrate 1. The isolation trench 11 is formed in the first substrateThe orthographic projection on 1 is annular. The number of the isolation trenches 11 may be one or more to form one or more bidirectional TVS structures. Alternatively, the number of the isolation slots 11 may be four, so that the transient suppression chip 100 has a bidirectional four-channel protection capability, but the disclosure does not limit this. The material of the third masking layer 8 may be SiO2However, the present disclosure is not limited thereto. The third masking layer 8 may be formed by a thermal growth or deposition process. The third masking layer 8 may be 2000-20000 angstroms thick. After forming the isolation trench 11, the present disclosure may fill the isolation trench 11 with an insulating material, for example, SiO2To form the isolation structure 10.
After forming the isolation structure 10, as shown in fig. 11, the present disclosure may form a fourth masking layer 9 on a surface of the third masking layer 8 facing away from the first substrate 1; as shown in fig. 12, second lead holes 12 are formed through the third masking layer 8 and the fourth masking layer 9; as shown in fig. 13, the first electrode 5 is formed at the second lead hole 12.
Step S104B, forming a second electrode 6 covering the second surface, wherein the second electrode 6 is electrically connected to the input terminal of the second diode D1.
As shown in fig. 13, the second electrode 6 may be prepared by thinning, back steaming, or the like.
In step S20, as shown in fig. 2, 14 and 15, the low capacitance chip 200 is formed, the low capacitance chip 200 includes a second diode D1 and a third diode D2, an output terminal of the second diode D1 is connected to an input terminal of the third diode D2, and an output terminal of the third diode D2 is connected to an input terminal of the second diode D1.
The low-capacitance chip 200 may include a second substrate 13 of the first conductive type. The surface of the second substrate 13 may be provided with two second implanted regions 1301 of the second conductivity type and two third implanted regions 1302 of the first conductivity type. The doping concentration of the third implant region 1302 may be greater than the doping concentration of the second substrate 13. The two second implant regions 1301 may be connected to the two third implant regions 1302 in a one-to-one correspondence. The second substrate 13, a second implanted region 1301 and a third implanted region 1302 constitute a second diode D1; the second substrate 13, the further second implanted region 1301 and the further third implanted region 1302 constitute a third diode D2.
In one embodiment of the present disclosure, the second implantation region 1301 and the third implantation region 1302 constituting the second diode D1 are located on one surface of the second substrate 13, and the second implantation region 1301 and the third implantation region 1302 constituting the third diode D2 are located on the other surface of the second substrate 13, that is, the second diode D1 and the third diode D2 are in an anti-parallel structure of longitudinal current.
In another embodiment of the present disclosure, two second implantation regions 1301 and two third implantation regions 1302 are located on the same surface of the second substrate 13, that is, the second diode D1 and the third diode D2 are in an anti-parallel structure of lateral current.
Taking the two second implantation regions 1301 and the two third implantation regions 1302 located on the same surface of the second substrate 13 as an example, step S20 may include:
step S201, a second substrate 13 of the first conductivity type is provided.
The second substrate 13 may be a silicon carbide substrate, but of course, the present embodiment is not limited thereto.
Step S202, forming two second implantation regions 1301 of the second conductivity type and two third implantation regions 1302 of the first conductivity type on the surface of the second substrate 13, wherein the doping concentration of the third implantation is greater than that of the second substrate 13; the two second implantation regions 1301 are connected to the two third implantation regions 1302 in a one-to-one correspondence; the second substrate 13, one second implanted region 1301 and one third implanted region 1302 constitute a second diode D1; the second substrate 13, the further second implanted region 1301 and the further third implanted region 1302 constitute a third diode D2.
The second and third implant regions 1301, 1302 are located on the same surface of the second substrate 13. The formation process of the second implantation region 1301 may include: forming a fifth mask layer 14 on the surface of the second substrate 13; forming two second implantation windows and two third implantation windows exposing the second substrate 13 on the fifth masking layer 14; ion implantation through two second implantation windows to formAnd a second implantation region 1301 for performing ion implantation through two third implantation windows to form a third implantation region 1302. The material of the third masking layer 8 may be SiO2However, the present disclosure is not limited thereto. The fifth masking layer 14 may be formed by a thermal growth or deposition process. The fifth masking layer 14 may be 2000-20000 angstroms thick. The present disclosure may form an implantation window on fifth masking layer 14 through a photolithography process. In the ion implantation process, the implantation energy may be 30KEV-300KEV, and the implantation dose may be 1E13-1E 16. After ion implantation is finished, high-temperature annealing is required to be carried out at 1000-1200 ℃, and the annealing time can be 30-600 min.
Step S203, forming a third electrode 16 covering one second injection region 1301 and one third injection region 1302, and forming a fourth electrode 17 covering another second injection region 1301 and another third injection region 1302.
After the high-temperature annealing is completed, the present disclosure may form a sixth masking layer 15 on a surface of the fifth masking layer 14 facing away from the first substrate 1; forming a third lead hole in a region of the sixth masking layer 15 corresponding to the second injection window, the third lead hole being in communication with the second injection window; forming a fourth lead hole in a region of the sixth masking layer 15 corresponding to the third injection window, the fourth lead hole being communicated with the third injection window; a third electrode 16 and a fourth electrode 17 are formed by a sputtering process, the third electrode 16 filling the third lead hole, the fourth electrode 17 filling the fourth lead hole. The material of the sixth masking layer 15 may be SiO2However, the present disclosure is not limited thereto. The sixth masking layer 15 may be formed by a thermal growth or deposition process. The fourth masking layer 9 may be 2000-20000 angstroms thick. After the third electrode 16 and the fourth electrode 17 are formed, the present disclosure may also form a solder layer 18 on a side of the second substrate 13 facing away from the third electrode 16. The third electrode 16 of the second diode D1 and the fourth electrode 17 of the third diode D2 may be electrically connected by a wire, and the fourth electrode 17 of the second diode D1 and the third electrode 16 of the third diode D2 may be electrically connected by a wire. The input terminal of the second diode D1 may be the third electrode 16 of the second diode D1, and the output terminal of the second diode D1 may be the second diodeAnd D1.
After the transient suppression chip 100 and the low capacitance chip 200 are formed, the transient suppression chip 100 and the low capacitance chip 200 are packaged by using an insulating material. The packaging shape can be SOD series, DFN series, etc. The insulating structure 19 employed by the package may be epoxy, ceramic, or the like. The encapsulated structure may include a first carrier plate 22 and a second carrier plate 23. The transient suppression chip 100 is disposed on the first carrier plate 22. The second carrier 23 is spaced apart from the first carrier 22, and the low-capacitance chip 200 is disposed on the second carrier 23. The first carrier 22 may be a conductor, the output terminal of the transient suppression chip 100 is connected to the first carrier 22, and the first carrier 22 is connected to the input terminal of the second diode D1 through a conducting wire. The encapsulated structure may also include an input electrode 21 and an output electrode 20. The input electrode 21 may be connected to a first external connection terminal of the semiconductor device. The output electrode 20 may be connected to a second external connection terminal of the semiconductor device.
The disclosed embodiments also provide a semiconductor device including:
a transient suppression chip 100;
the low-capacitance chip 200 comprises a second diode D1 and a third diode D2, wherein the output end of the second diode D1 is connected with the input end of the third diode D2, and the output end of the third diode D2 is connected with the input end of the second diode D1;
wherein the output terminal of the transient suppression chip 100 is connected to the input terminal of the second diode D1, the input terminal of the transient suppression chip 100 is the first external connection terminal of the semiconductor device, and the output terminal of the second diode D1 is the second external connection terminal of the semiconductor device.
Further, the transient suppression chip 100 has a unidirectional TVS structure; or
The transient suppression chip 100 has a bidirectional TVS structure; or
The transient suppression chip 100 has a plurality of unidirectional TVS structures, one end of each of the plurality of unidirectional TVS structures is connected to the input terminal of the second diode D1, and the other end of each of the plurality of unidirectional TVS structures constitutes a plurality of first external connection terminals of the semiconductor device; or
The transient suppression chip 100 has a plurality of bidirectional TVS structures, one end of each of the plurality of bidirectional TVS structures is connected to the input terminal of the second diode D1, and the other end of each of the plurality of bidirectional TVS structures constitutes a plurality of the first external connection terminals of the semiconductor device.
Further, the transient suppression chip 100 has a unidirectional TVS structure; or alternatively
The transient suppression chip 100 has a bidirectional TVS structure; or
The transient suppression chip 100 has a plurality of unidirectional TVS structures, one ends of the unidirectional TVS structures are all connected to the input end of the second diode D1, and the other ends of the unidirectional TVS structures constitute a plurality of first external connection ends of the semiconductor device; or alternatively
The transient suppression chip 100 has a plurality of bidirectional TVS structures, one ends of the plurality of bidirectional TVS structures are connected to the input terminal of the second diode D1, and the other ends of the plurality of bidirectional TVS structures constitute a plurality of first external connection terminals of the semiconductor device;
the unidirectional TVS structure or the bidirectional TVS structure is a PN junction structure, a PNP structure, an NPN structure, a NPNP silicon controlled structure, a PNPN silicon controlled structure, an NPNPNPN silicon controlled structure or a PNPNPNP silicon controlled structure.
Further, the transient suppression chip 100 includes one or more first diodes Z1, the first diode Z1 includes:
a first substrate 1 of a first conductivity type, said first substrate 1 having opposite first and second surfaces, said first surface being provided with one or more first implanted regions 3 of a second conductivity type;
a first electrode 5 covering the first implantation region 3, the first electrode 5 constituting a first external connection terminal of the semiconductor device;
and a second electrode 6 covering the second surface and electrically connected to an input terminal of the second diode D1.
Further, the transient suppression chip 100 includes one or more diode components, the diode components include two first diodes Z1 connected in reverse series, one end of the two first diodes Z1 connected in reverse series is connected with the input end of the second diode D1, and the other end of the two first diodes Z1 connected in reverse series constitutes a first external connection end of the semiconductor device;
the diode assembly includes:
a first substrate 1 of a first conductivity type, said first substrate 1 having opposite first and second surfaces;
an epitaxial layer 7 including an epitaxial region 701 of a second conductivity type and a doped region 702 of a first conductivity type; the epitaxial region 701 and the doped region 702 are stacked, and the epitaxial region 701 is arranged on the first surface;
a first electrode 5 covering the doped region 702, the first electrode 5 constituting a first external connection terminal of the semiconductor device;
and a second electrode 6 covering the second surface and electrically connected to an input terminal of the second diode D1.
Further, the low capacitance chip 200 includes:
a second substrate 13 of a first conductivity type, wherein two second implantation regions 1301 of the second conductivity type and two third implantation regions 1302 of the first conductivity type are arranged on the surface of the second substrate 13, and the doping concentration of the third implantation regions 1302 is greater than that of the second substrate 13; the two second implantation regions 1301 are connected to the two third implantation regions 1302 in a one-to-one correspondence; the second substrate 13, one of the second implanted regions 1301 and one of the third implanted regions 1302 constitute the second diode D1; the second substrate 13, the other second implantation region 1301 and the other third implantation region 1302 constitute the third diode D2.
Further, the second implantation region 1301 and the third implantation region 1302 constituting the second diode D1 are located at one surface of the second substrate 13, and the second implantation region 1301 and the third implantation region 1302 constituting the third diode D2 are located at the other surface of the second substrate 13; or
The two second implantation regions 1301 and the two third implantation regions 1302 are located on the same surface of the second substrate 13.
Further, the semiconductor device includes:
the first carrier plate 22, on which the transient suppression chip 100 is disposed;
the second bearing plate 23 is arranged at an interval with the first bearing plate 22, and the low-capacitance chip 200 is arranged on the second bearing plate 23;
the first carrier plate 22 is a conductor, the output terminal of the transient suppression chip 100 is connected to the first carrier plate 22, and the first carrier plate 22 is connected to the input terminal of the second diode D1 through the wire.
The semiconductor device and the method for manufacturing the same provided by the embodiment of the disclosure belong to the same inventive concept, and the description of the relevant details and the beneficial effects can be referred to each other and are not repeated.
Although the present disclosure has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.

Claims (8)

1. A semiconductor device, comprising:
a transient suppression chip;
the low-capacitance chip comprises a second diode and a third diode, wherein the output end of the second diode is connected with the input end of the third diode, and the output end of the third diode is connected with the input end of the second diode;
the output end of the transient suppression chip is connected with the input end of the second diode, the input end of the transient suppression chip is a first external connection end of the semiconductor device, and the output end of the second diode is a second external connection end of the semiconductor device.
2. The semiconductor device of claim 1, wherein the transient suppression chip has a unidirectional TVS structure; or alternatively
The transient suppression chip is provided with a bidirectional TVS structure; or
The transient suppression chip is provided with a plurality of unidirectional TVS structures, one ends of the unidirectional TVS structures are connected with the input end of the second diode, and the other ends of the unidirectional TVS structures form a plurality of first external connection ends of the semiconductor device; or
The transient suppression chip is provided with a plurality of bidirectional TVS structures, one ends of the bidirectional TVS structures are connected with the input end of the second diode, and the other ends of the bidirectional TVS structures form a plurality of first external connecting ends of the semiconductor device.
3. The semiconductor device of claim 1, wherein the transient suppression chip has a unidirectional TVS structure; or
The transient suppression chip is provided with a bidirectional TVS structure; or
The transient suppression chip is provided with a plurality of unidirectional TVS structures, one ends of the unidirectional TVS structures are connected with the input end of the second diode, and the other ends of the unidirectional TVS structures form a plurality of first external connection ends of the semiconductor device; or
The transient suppression chip is provided with a plurality of bidirectional TVS structures, one ends of the bidirectional TVS structures are connected with the input end of the second diode, and the other ends of the bidirectional TVS structures form a plurality of first external connection ends of the semiconductor device;
the unidirectional TVS structure or the bidirectional TVS structure is a PN junction structure, a PNP structure, an NPN structure, a NPNP silicon controlled structure, a PNPN silicon controlled structure, a NPNPNPN silicon controlled structure or a PNPNPNP silicon controlled structure.
4. The semiconductor device of claim 1, wherein the transient suppression chip comprises one or more first diodes, the first diodes comprising:
a first substrate of a first conductivity type, the first substrate having opposite first and second surfaces, the first surface being provided with one or more first implanted regions of a second conductivity type;
a first electrode covering the first injection region, the first electrode constituting a first external connection terminal of the semiconductor device;
and the second electrode covers the second surface and is electrically connected with the input end of the second diode.
5. The semiconductor device according to claim 1, wherein the transient suppression chip comprises one or more diode components, the diode components comprise two first diodes connected in reverse series, one end of the two first diodes connected in reverse series is connected with an input end of the second diode, and the other end of the two first diodes connected in reverse series constitutes a first external connection end of the semiconductor device;
the diode assembly includes:
a first substrate of a first conductivity type, the first substrate having opposing first and second surfaces;
the epitaxial layer comprises an epitaxial region of the second conductivity type and a doped region of the first conductivity type; the epitaxial region and the doped region are arranged in a stacked mode, and the epitaxial region is arranged on the first surface;
a first electrode covering the doped region, the first electrode constituting a first external connection terminal of the semiconductor device;
and the second electrode covers the second surface and is electrically connected with the input end of the second diode.
6. The semiconductor device according to claim 1, wherein the low-capacitance chip comprises:
the surface of the second substrate is provided with two second injection regions of a second conductivity type and two third injection regions of a first conductivity type, and the doping concentration of the third injection regions is greater than that of the second substrate; the two second injection regions are connected with the two third injection regions in a one-to-one correspondence manner; the second substrate, one of the second implanted regions, and one of the third implanted regions constitute the second diode; the second substrate, another of the second implant regions, and another of the third implant regions constitute the third diode.
7. The semiconductor device according to claim 6, wherein the second implanted region and the third implanted region constituting the second diode are located on one surface of the second substrate, and the second implanted region and the third implanted region constituting the third diode are located on the other surface of the second substrate; or
The two second implantation regions and the two third implantation regions are located on the same surface of the second substrate.
8. The semiconductor device according to claim 1, characterized in that the semiconductor device comprises:
the transient suppression chip is arranged on the first bearing plate;
the second bearing plate is arranged at an interval with the first bearing plate, and the low-capacitance chip is arranged on the second bearing plate;
the first bearing plate is a conductor, the output end of the transient suppression chip is connected with the first bearing plate, and the first bearing plate is connected with the input end of the second diode through a lead.
CN202122955720.1U 2021-11-29 2021-11-29 Semiconductor device with a plurality of transistors Active CN216563122U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202122955720.1U CN216563122U (en) 2021-11-29 2021-11-29 Semiconductor device with a plurality of transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202122955720.1U CN216563122U (en) 2021-11-29 2021-11-29 Semiconductor device with a plurality of transistors

Publications (1)

Publication Number Publication Date
CN216563122U true CN216563122U (en) 2022-05-17

Family

ID=81577476

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202122955720.1U Active CN216563122U (en) 2021-11-29 2021-11-29 Semiconductor device with a plurality of transistors

Country Status (1)

Country Link
CN (1) CN216563122U (en)

Similar Documents

Publication Publication Date Title
US9911730B2 (en) Transient voltage suppressor and manufacture method thereof
US9837516B2 (en) Bi-directional punch-through semiconductor device and manufacturing method thereof
US10128227B2 (en) ESD protection device and method for manufacturing the same
CN102171826B (en) Discrete semiconductor device and method of forming sealed trench junction termination
CN210296387U (en) Trench diode and power semiconductor device
US9929137B2 (en) Method for manufacturing ESD protection device
US9019667B2 (en) Protection device and related fabrication methods
JP2011018920A (en) Method of manufacturing integrated circuit structure having pin diode
EP2827373B1 (en) Protection device and related fabrication methods
CN106169508B (en) Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof
CN106158851B (en) Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof
CN216563122U (en) Semiconductor device with a plurality of transistors
DK157468B (en) Diode for monolithic integrated circuit
CN111180344A (en) Three-dimensional stacked structure and preparation method
CN114005817A (en) Semiconductor device and method for manufacturing the same
KR101779588B1 (en) Transient voltage suppressor and manufacturing method thereof
US9831327B2 (en) Electrostatic discharge protection devices and methods of forming the same
KR101006768B1 (en) Structure of a tvs diode array and its fabrication method
CN109326592B (en) Transient voltage suppressor and method of manufacturing the same
CN114171465A (en) Method for manufacturing integrated circuit and integrated circuit
CN113421930A (en) Structure of bidirectional high-voltage transient voltage suppressor and manufacturing method thereof
CN103178121B (en) Pin diode and manufacturing method thereof
CN111162046A (en) Three-dimensional stacked structure and preparation method
KR101893673B1 (en) Transient voltage suppressor and manufacturing method thereof
CN111180421B (en) Transistor structure for electrostatic protection and manufacturing method thereof

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant