CN109300902A - 3D memory device - Google Patents
3D memory device Download PDFInfo
- Publication number
- CN109300902A CN109300902A CN201811139608.7A CN201811139608A CN109300902A CN 109300902 A CN109300902 A CN 109300902A CN 201811139608 A CN201811139608 A CN 201811139608A CN 109300902 A CN109300902 A CN 109300902A
- Authority
- CN
- China
- Prior art keywords
- fence
- memory device
- channel
- layer
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
This application discloses a kind of 3D memory devices.The 3D memory device includes: rhythmic structure of the fence, and the rhythmic structure of the fence includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked；Multiple channel columns, the channel column is through the rhythmic structure of the fence to form transistor；And multiple pseudo- channel columns, at least partly described grid conductor of the puppet channel column in the rhythmic structure of the fence is to provide support, wherein the pseudo- channel column of at least one of the multiple puppet channel column is connected with radiator structure.The present invention is connected to radiator structure using pseudo- channel column and provides sinking path, and the yield and reliability of 3D memory device can be improved.
Description
Technical field
The present invention relates to memory technology fields, more particularly, to 3D memory device.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, memory cell array is formed using rhythmic structure of the fence, in the 3D memory
In part, being electrically connected between memory cell array and external circuit is provided using a large amount of metal lines, the increase of wiring density will
It will affect the yield and reliability of 3D memory device.It is expected that it is further improved the structure and its manufacturing method of 3D memory device, with
Improve the yield and reliability of 3D memory device.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of 3D memory devices, wherein the present invention is using pseudo- channel
Column is connected to radiator structure and provides sinking path, to improve the yield and reliability of 3D memory device.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising: rhythmic structure of the fence, the gate stack knot
Structure includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked；Multiple channel columns, the channel column run through the grid
Laminated construction is to form transistor；And multiple pseudo- channel columns, the puppet channel column run through in the rhythmic structure of the fence at least
The part grid conductor is to provide support, wherein the pseudo- channel column of at least one of the multiple puppet channel column is connected with scattered
Heat structure.
It preferably, include heat sink material in the pseudo- channel column.
Preferably, further includes: the first semiconductor substrate, the first surface and the gate stack of first semiconductor substrate
Structure is adjacent；Second insulating layer on the second surface of first semiconductor substrate, first semiconductor substrate
Second surface is relative to each other with first surface；And the first insulating layer of the covering rhythmic structure of the fence.
Preferably, the radiator structure is located at first insulating layer.
Preferably, the radiator structure is located at the second insulating layer.
Preferably, further includes: at least partially surrounding the insulation lining of the pseudo- channel column, for by the pseudo- channel column with
The rhythmic structure of the fence and first semiconductor substrate are separated from each other.
Preferably, further includes: the first end of multiple wiring layers in first insulating layer, the puppet channel column connects
It is connected to the A respective routing layer of the multiple wiring layer, second end connects the radiator structure.
Preferably, further includes: the groove being laterally extended on the surface of first insulating layer, the groove is from the grid
The first side wall of laminated construction reaches second sidewall, and the first end of the multiple puppet channel column extends to the groove, second end
Connect the radiator structure.
Preferably, further includes: the thermally conductive item in the groove.
Preferably, further includes: cmos circuit, the cmos circuit are bonded to the rhythmic structure of the fence by connection structure,
It and include: the second semiconductor substrate；Transistor in second semiconductor substrate；And it is led positioned at described the second half
Third insulating layer in body substrate.
Preferably, the rhythmic structure of the fence is as memory cell array, and described first in the memory cell array is absolutely
As the first bonding face, the rhythmic structure of the fence further includes the first outside weldering on first bonding face on the surface of edge layer
Disk, as the second bonding face, the cmos circuit further includes being located on the surface of the second insulating layer in the cmos circuit
The second external pads on second bonding face, wherein the first bonding face and the cmos circuit of the rhythmic structure of the fence
The second bonding face be in contact with each other, first external pads bond together with second external pads, thus realize described in
Electrical connection between rhythmic structure of the fence and the cmos circuit.
3D memory device according to this embodiment forms memory cell array using rhythmic structure of the fence, in storage unit battle array
The inside of column provides passage of heat, and passage of heat includes pseudo- channel column, and memory cell array Free Surface provide with
The connected radiator structure of passage of heat.A large amount of heat is generated during the work of memory cell array, via passage of heat and
Radiator structure is released, so as to keep the operating temperature of 3D memory device to meet the requirements, thus in 3D memory device benefit
It will not occur that error in data is written when data are written with tunnelling principle, and excessively high temperature is avoided to lead to device failure.Therefore,
Yield and reliability can be improved in 3D memory device according to this embodiment.
Further, cmos circuit is formed using semiconductor substrate, then each other by cmos circuit and memory cell array
Bonding.The amount of heat generated during the work of cmos circuit and memory cell array in bonding face, can also be via thermally conductive logical
Road and radiator structure are released, and excessive temperature is avoided to lead to device failure.Therefore, 3D memory device can according to this embodiment
To further increase yield and reliability.
Further, the passage of heat in the 3D memory device is pseudo- channel column and/or pseudo- conductive channel, the passage of heat
At least part be formed simultaneously with the channel column and/or the conductive channel, it is possible to reduce additional processing step and cover
Modulus amount.Therefore, 3D memory device can reduce manufacturing cost according to this embodiment.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 a and 2b be shown respectively the internal structure of 3D memory device according to a first embodiment of the present invention perspective view and
Overall perspective.
Fig. 3 shows 3D memory device sectional view according to a first embodiment of the present invention.
Fig. 4 shows 3D memory device sectional view according to a second embodiment of the present invention.
Fig. 5 shows 3D memory device sectional view according to a third embodiment of the present invention.
Fig. 6 a to 6f shows the section in each stage of 3D memory device manufacturing method according to a first embodiment of the present invention
Figure.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Term " Free Surface " refers to cmos circuit and storage unit battle array
The respective surface opposite with the two contact surface is arranged, term " bonding face " refers to that both cmos circuit and memory cell array contact
Surface, cmos circuit and memory cell array using both bonding face realize mechanical connection and electrical connection.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
In the 3D memory device of NAND structure, memory cell array, the rhythmic structure of the fence are formed using rhythmic structure of the fence
The grid conductor of selection transistor and memory transistor is provided, provides memory cell array and external electrical using a large amount of metal lines
Electrical connection between road.Further, cmos circuit is formed using semiconductor substrate, then by cmos circuit and storage unit battle array
Column bond together.Cmos circuit and memory cell array include wiring layer, wherein providing CMOS electricity using a large amount of metal lines
Electrical connection between road and memory cell array.
The inventors of the present application found that a large amount of heat can be generated during the work of memory cell array.The heat
Accumulation causes the temperature of 3D memory device excessively high.Data, therefore, 3D memory device pair are written using tunnelling principle in 3D memory device
More sensitive in environment temperature, excessively high temperature may cause write-in error in data.In more severe instances, excessively high temperature
The electrical connection that may cause between cmos circuit and memory cell array disconnects, and leads to device failure.And in cmos circuit work
During work, since the apparent surface of cmos circuit and memory cell array bonds together, cmos circuit and storage unit battle array
A large amount of wirings of column are located near bonding face, so that heat, which concentrates on, can not discharge herein, the temperature of 3D memory device can be into one
Step increases.Existing 3D memory device does not have heat dissipation path between cmos circuit and memory cell array, to affect 3D
The yield and reliability of memory device.
Present inventor notices the problem of yield and reliability of above-mentioned influence 3D memory device, thus propose into
The improved 3D memory device of one step.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line
The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of memory transistor M1 to M4 is respectively connected to
The respective word of wordline WL1 to WL4.
As shown in Figure 1 b, the first choice transistor Q1 of memory cell string 100 and the second selection transistor Q2 are respectively included
Grid conductor 122 and 123, memory transistor M1 to M4 respectively include grid conductor 121.Grid conductor 121,122 and 123 with deposit
The stacking order of transistor in storage unit string 100 is consistent, is separated each other using interlayer insulating film between adjacent grid conductor,
To form rhythmic structure of the fence.Further, memory cell string 100 includes channel column 110.Channel column 110 runs through gate stack knot
Structure.In the middle section of channel column 110, tunneling medium layer 112, charge storage are accompanied between grid conductor 121 and channel layer 111
Layer 113 and block media layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110,122 He of grid conductor
Block media layer 114 is accompanied between 123 and channel layer 111, to form first choice transistor Q1 and the second selection transistor
Q2。
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and block media layer
114 are made of oxide respectively, such as silica, and charge storage layer 113 is by the insulating layer comprising quantum dot or nanocrystal
Composition, such as the silicon nitride of the particle comprising metal or semiconductor, grid conductor 121,122 and 123 are made of metal, such as
Tungsten.Channel layer 111 is used to provide the channel region of control selection transistor and memory transistor, the doping type of channel layer 111 and choosing
It is identical with the type of memory transistor to select transistor.For example, for the selection transistor and memory transistor of N-type, channel layer 111
It can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Block media layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is attached
The insulating layer added, channel layer 111, tunneling medium layer 112, charge storage layer 113 and block media layer 114 are formed around core
Laminated construction.
In this embodiment, first choice transistor Q1 and the second selection transistor Q2, memory transistor M1 to M4 are used
Public channel layer 111 and block media layer 114.In channel column 110, channel layer 111 provides the source-drain area of multiple transistors
And channel layer.In alternate embodiments, step independent of one another can be used, first choice transistor Q1 and the is respectively formed
The semiconductor layer and block media layer of two selection transistor Q2 and the semiconductor layer and block media of memory transistor M1 to M4
Layer.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to greatly
About zero volts, so that the selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 a and 2b be shown respectively the internal structure of 3D memory device according to a first embodiment of the present invention perspective view and
Overall perspective, Fig. 3 show 3D memory device sectional view according to a first embodiment of the present invention, and the sectional view is along in Fig. 2 a
AA line interception.
For the sake of clarity, the internal structure of 3D memory device is only shown in fig. 2 a, wherein storage unit battle array is not shown
The semiconductor substrate of column and the insulating layer in cmos circuit and memory cell array, only show 3D memory in figure 2b
External structure.
The 3D memory device 200 shown in this embodiment includes the cmos circuit 210 stacked and memory cell array
220。
Cmos circuit 210 includes semiconductor substrate 201, multiple contact pads 261 in semiconductor substrate 201, position
In multiple wiring layers 263 on multiple contact pads 261, multiple external pads 264 on multiple wiring layers 263 and
The conductive channel 262 of interconnection is provided on the direction on the surface perpendicular to semiconductor substrate 201.It, can be with although being not shown
Understand, multiple transistors are formed in semiconductor substrate 201.Between multiple wiring layers 260 and multiple wiring layers
It is separated from each other between 260 and contact pad 261 and external pads 264 using interlayer insulating film, and using through layer insulation
The conductive channel 262 of layer is electrically connected to each other.Interlayer insulating film is not shown in fig. 2 a.
In cmos circuit 210, contact pad 261 is electrically connected with the transistor in semiconductor substrate 201, the contact pad
261 are connected to wiring layer 263 via conductive channel 262, and then wiring layer 263 is connected via conductive channel 262 from external pads
264.The external pads 264 provide the electrical connection between the transistor and memory cell array 220 inside cmos circuit 210.
Memory cell array 220 includes that 2*3 amounts to 6 memory cell strings, and each memory cell string includes that 4 storages are single
Member, to form the memory array that 4*2*3 amounts to 24 storage units.It is appreciated that the invention is not limited thereto, 3D memory
Part may include any number of memory cell strings, for example, 1024, the number of memory cells in each memory cell string can be
It is any number of, for example, 32 or 64.
Memory cell array 220 includes semiconductor substrate 101, the rhythmic structure of the fence in semiconductor substrate 101, runs through
Channel column 110, the interconnection structure on rhythmic structure of the fence of rhythmic structure of the fence.The interconnection structure includes multiple conductive channels
161, multiple contact pads 162, the multiple cloth on multiple contact pads 162 contacted respectively with multiple conductive channels 161
Line layer 164, multiple external pads 165 on multiple wiring layers 164 and on the surface perpendicular to semiconductor substrate 101
Direction on the conductive channel 163 of interconnection is provided.Rhythmic structure of the fence is for example including grid conductor 121,122 and 123.Gate stack knot
Multiple grid conductors in structure for example form step-like, extend up to corresponding grid conductor for providing conductive channel 161
Space.
In memory cell array 220, memory cell string respectively includes respective channel column 110 and public grid
Conductor 121,122 and 123.Grid conductor 121,122 and 123 is consistent with the stacking order of transistor in memory cell string 100,
It is separated each other using interlayer insulating film between adjacent grid conductor, to form rhythmic structure of the fence.Layer is not shown in fig. 2 a
Between insulating layer.
In this embodiment, the internal structure of channel column 110 is as shown in Figure 1 b, is no longer described in detail herein.Channel
Column 110 runs through rhythmic structure of the fence, and is arranged in array.Semiconductor substrate is located above rhythmic structure of the fence, is formed with public affairs
Common source area (not shown).The first end of channel column 110 is commonly connected to public source zone, the second end of channel column 110 via
Conductive channel and wiring are connected to corresponding external pads 165.The effect of conductive channel and wiring layer herein and bit line BL phase
Together.
The grid conductor 122 of first choice transistor Q1 is divided into difference by grid line gap (gate line slit) 151
Grid line.Grid line with multiple channel columns 110 of a line is connected to corresponding external pads via conductive channel and wiring respectively
165.For the sake of clarity, in a part of conductive channel and the wiring being not shown in the figure between grid conductor 122 and contact pad
Layer.The effect of conductive channel and wiring layer herein is identical as string selection line SSL.
The grid conductor 121 of memory transistor M1 and M4 are respectively connected to corresponding wordline.If memory transistor M1 and
The grid conductor 121 of M4 is divided into different grid lines by grid line gap 151, then the grid line of same level is respectively via conductive channel
Corresponding external pads 165 are connected to wiring.For the sake of clarity, grid conductor 121 and contact pad is being not shown in the figure
Between a part of conductive channel and wiring layer.The effect of conductive channel and wiring layer herein is identical as wordline WL1 to WL4.
The grid conductor of second selection transistor Q2 links into an integrated entity.If the grid conductor of the second selection transistor Q2
123 are divided into different grid lines by grid line gap 151, then grid line is connected to corresponding outside via conductive channel and wiring respectively
Pad 165.The effect of conductive channel and wiring layer herein is identical as ground selection line GSL.
Rhythmic structure of the fence and layer are respectively arranged in 101 each other relative first surface of semiconductor substrate and second surface
Between insulating layer 104, on interlayer insulating film 104 formed be provided with radiator structure 105.Radiator structure 105 is good by thermal conductivity
Metal or resin composition, such as copper, silver, aluminium heat conductive silica gel.
In this embodiment, passage of heat 143 and insulation lining 144 are formed in the inside of memory cell array 220.It is thermally conductive
Channel 143 is made of the good metal of thermal conductivity or resin, such as copper, silver, aluminium heat conductive silica gel.Passage of heat 143 is folded across grid
Layer structure, semiconductor substrate 101 and interlayer insulating film 104, and by insulating between rhythmic structure of the fence and semiconductor substrate 101
Lining 142 is insulated from each other.The first end of passage of heat 143 extends to the wiring layer 164 inside memory cell array 220, and second
End extends to the Free Surface of memory cell array 220, the i.e. surface opposite with bonding face, is connected with radiator structure 105, from
And provide heat dissipation path.
It preferably, in this embodiment can also include pseudo- channel column 130, the inside of pseudo- channel column 130 and channel column 110
Structure can be identical, and at least across at least part grid conductor in rhythmic structure of the fence.However, pseudo- channel column 130 is not
It is connected with external pads 165, so that it is provided solely for mechanical support effect, it is brilliant without being used to form selection transistor and storage
Body pipe.Therefore, pseudo- channel column 130 does not form effective storage unit.
It preferably, in this embodiment can also include conductive channel 141 and insulation lining 142.The conductive channel 141 is made
For through a part of contact through hole (TAC), for providing the conductive path between cmos circuit and external circuit.Conductive channel
141 pass through rhythmic structure of the fence, semiconductor substrate 101 and interlayer insulating film 104, and with rhythmic structure of the fence and semiconductor substrate
It is insulated from each other by insulation lining 142 between 101.The first end and second end of conductive channel 141 extends respectively to storage unit battle array
Two apparent surfaces (i.e. Free Surface and bonding face) of column 220 form external pads.
It preferably, in this embodiment can also include additional conductive channel and superinsulation lining (not shown).
The additional a part of the conductive channel as source line GL, for provide the common source in semiconductor substrate 101 and external circuit it
Between electrical connection.In this preferred embodiment, which passes through rhythmic structure of the fence, and with rhythmic structure of the fence and
It is insulated from each other by superinsulation lining between semiconductor substrate 101.The first end arrival public source zone of additional conductive channel, second
End is connected to wiring layer.
After forming cmos circuit 210 and memory cell array 220, the two is bonded together into 3D memory device 200.
Cmos circuit 210 and 220 surfaces opposite to each other of memory cell array are respective bonding face.Cmos circuit 210 and storage are single
A large amount of wirings of element array 220 are located near respective bonding face.
B referring to fig. 2, according to this embodiment 3D memory device 200, the conductive channel of cmos circuit 210 and wiring layer position
In at least one insulating layer 202, the conductive channel and wiring layer of memory cell array 220 are located at least one insulating layer 102
In.Cmos circuit 210 and the bonding face of memory cell array 220 are respectively the surfaces opposite to each other of insulating layer 202 and 102.Into
One step, the external pads 264 of cmos circuit 210 and the external pads 165 of memory cell array 220 are bonded accordingly respectively
Exposure on face, and it is positioned opposite to each other.Therefore, it deposits cmos circuit 210 and memory cell array 220 are bonded together into 3D
When memory device 200, the external pads 264 of cmos circuit 210 and the external pads 165 of memory cell array 220 are in contact with each other, from
And realize being electrically connected between cmos circuit 210 and memory cell array 220.
Further, 3D memory device 200 according to this embodiment, is formed in the inside of memory cell array 220 and leads
The passage of heat 143 is formed with radiator structure 105 in the Free Surface of memory cell array 220.The first end of passage of heat 143 arrives
Up to the wiring layer of memory cell array 220, second end is connected with radiator structure 105, to form heat dissipation path.Radiator structure
105 are laterally extended on the Free Surface of memory cell array 220, such as with substantially rectangular shape.In cmos circuit 210
It bonds together in the 3D memory device 200 to be formed with memory cell array 220, passage of heat 143 reaches wiring layer, radiator structure
105 are exposed to external environment, so that outside is conducted heat to from the wiring layer inside 3D memory device, to utilize 3D memory
Radiator structure on one side surface of part realizes heat release.
In alternate embodiments, passage of heat is formed in the inside of cmos circuit 210, in the freedom of cmos circuit 210
Surface is formed with radiator structure.The Free Surface of the interlayer insulating film formed in the Free Surface such as semiconductor substrate 201.It leads
The first end of the passage of heat reaches the wiring layer of cmos circuit 210, and second end is connected with radiator structure, to form heat dissipation path.
The alternative embodiment realizes that heat discharges using the radiator structure on another side surface of 3D memory device.
In a preferred embodiment, it is respectively formed conductive channel in the inside of cmos circuit 210 and memory cell array 220,
It is respectively formed radiator structure in the Free Surface of cmos circuit 210 and memory cell array 220, to utilize the phase of 3D memory device
Heat release is realized to the radiator structure on surface.
In a preferred embodiment, cross is formed in the bonding face of at least one cmos circuit 210 and memory cell array 220
To through-going recess, so that additional heat dissipation path is provided, to realize that heat discharges using through-going recess.
Fig. 4 shows 3D memory device sectional view according to a second embodiment of the present invention, and the sectional view is along in Fig. 2 a
The interception of AA line.
The 3D memory device 300 shown in this embodiment includes the cmos circuit 210 stacked and memory cell array
220.The difference of second embodiment and first embodiment is only described in detail below.
In this embodiment, multiple passage of heat 143 and multiple insulation linings 144 are formed in memory cell array 220.
Multiple passage of heat 143 are each passed through rhythmic structure of the fence, semiconductor substrate 101 and interlayer insulating film 104, and with gate stack knot
It is insulated from each other by the lining 142 that insulate accordingly between structure and semiconductor substrate 101.First group of the multiple passage of heat 143
The first end of passage of heat is extended to up to wiring layer 163, and the first end of second group of passage of heat reaches memory cell array 220
Bonding face.The second end of the multiple passage of heat 143 all extends to the Free Surface of memory cell array 220, i.e., be bonded
The opposite surface in face, is connected with radiator structure 105, to provide heat dissipation path.
3D memory device according to this embodiment provides passage of heat in the inside of memory cell array, and is storing
The surface of cell array provides the radiator structure being connected with passage of heat.Passage of heat extends to wiring layer and bonding face, thus
Heat dissipation path is provided.A large amount of heat is being generated during the work of cmos circuit and during the work of memory cell array, is being passed through
It is discharged by heat dissipation path.The release of the heat can keep the operating temperature of 3D memory device to meet the requirements, to store in 3D
Devices use tunnelling principle will not occur that error in data is written when data are written, and avoid excessively high temperature that device is caused to damage
It is bad.Therefore, 3D memory device improves yield and reliability according to this embodiment.
3D memory device sectional view according to a third embodiment of the present invention is shown respectively in Fig. 5, and the sectional view is along Fig. 2 a
In AA line interception.
The 3D memory device 400 shown in this embodiment includes the cmos circuit 210 stacked and memory cell array
220.The difference of 3rd embodiment and first embodiment is only described in detail below.
In this embodiment, groove is formed on the bonding face of memory cell array 220.Thermally conductive item 413 in the grooves,
It is laterally extended on the bonding face of memory cell array 220, it is preferable that thermally conductive item 413 runs through two of memory cell array 220
Opposite flank.
Further, multiple passage of heat 143 and multiple insulation linings 144 are formed in memory cell array 220.It is multiple
Passage of heat 143 is each passed through rhythmic structure of the fence, semiconductor substrate 101 and interlayer insulating film 104, and with rhythmic structure of the fence and
It is insulated from each other by the lining 142 that insulate accordingly between semiconductor substrate 101.First group of the multiple passage of heat 143 is thermally conductive
The first end in channel is extended to up to wiring layer 163, and the first end of second group of passage of heat reaches the bonding of memory cell array 220
Thermally conductive item 413 in face.The second end of the multiple passage of heat 143 all extends to the Free Surface of memory cell array 220,
That is the surface opposite with bonding face is connected with radiator structure 105, to provide heat dissipation path.
3D memory device according to this embodiment provides passage of heat in the inside of memory cell array, and is storing
The Free Surface of cell array provides the radiator structure being connected with passage of heat, provides and leads in the bonding face of memory cell array
The connected thermally conductive item of the passage of heat.Passage of heat extends to wiring layer and thermally conductive item, to provide heat dissipation path.In cmos circuit
A large amount of heat is generated during work and during the work of memory cell array.Due to cmos circuit and memory cell array
Apparent surface bonds together, and therefore, heat concentrates near bonding face, and discharges via heat dissipation path.The release of the heat
The operating temperature of 3D memory device can be kept to meet the requirements, thus not when 3D memory device is using tunnelling principle write-in data
It can occur that error in data is written, and excessively high temperature is avoided to lead to device failure.Therefore, 3D memory according to this embodiment
Part improves yield and reliability.
Fig. 6 a to 6f shows the section in each stage of 3D memory device manufacturing method according to a first embodiment of the present invention
Figure, wherein Fig. 6 a to 6d shows the manufacturing step of memory cell array, and Fig. 6 e shows the manufacturing step of cmos circuit, and Fig. 6 f is shown
CMOS is bonded with memory cell array.The sectional view is intercepted along the AA line in Fig. 2 a.
This method starts from the semiconductor structure that multiple well regions are formed in semiconductor substrate 101, in the embodiment
In, semiconductor substrate 101 is, for example, monocrystalline substrate.
In this embodiment, it for the ease of being programmed operation to the storage unit in 3D memory device, is served as a contrast in semiconductor
Multiple well regions are formed in bottom 101.For example, semiconductor substrate 101 includes the public source zone of multiple channel columns.
As shown in Figure 6 a, semiconductor substrate 101 includes each other relative first surface and second surface, in semiconductor substrate
Insulating laminate structure is formed on 101 first surface.
The insulating laminate structure include stack multiple sacrificial layers 152, adjacent sacrificial layer 152 by insulating layer 102 each other
It separates.In this embodiment, insulating layer 102 is for example made of silica, and sacrificial layer 152 is for example made of silicon nitride.
As described below, sacrificial layer 152 will be replaced as grid conductor 121 to 123, and 121 1 step of grid conductor is connected to string
Selection line, 123 1 step of grid conductor are connected to the ground selection line, and 122 1 step of grid conductor is connected to wordline.In order to be formed from grid
Conductor 121 to 123 reaches the conductive channel of wordline, and multiple sacrificial layers 152 are for example patterned step-like, that is, each sacrificial layer
152 marginal portion provides electrical connection area relative to the sacrificial layer exposure of top.In the patterning step of multiple sacrificial layers 152
Later, insulating laminate structure can be covered using insulating layer.In Fig. 6 a by between multiple sacrificial layers 152 interlayer insulating film and
The interlayer insulating film of covering insulating laminate structure is integrally shown as insulating layer 102.However, the invention is not limited thereto, can use
Multiple independent deposition steps are formed between multiple sacrificial layers 152 and its multiple interlayer insulating films of top.
Further, channel hole is formed in insulating laminate structure.In this embodiment, for example, semiconductor structure table
Photoresist mask is formed on face, then carries out anisotropic etching, and channel hole is formed in insulating laminate structure.Respectively to different
Property etching can use dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, laser ablation.For example, logical
Control etching period is crossed, so that the close beneath for being etched in public source zone stops, and is etched in the lower section of the first insulating regions
Nearby stop.After the etching by dissolving or being ashed removal photoresist mask in a solvent.
Further, channel column 110 is formed in channel hole.The lower part of channel column 110 includes semiconductor layer.Further
Ground, channel column 110 include the channel layer that semiconductor layer is extended to from upper part.For the sake of clarity, ditch is not shown in Fig. 6 a
The internal structure of road column 110.Referring to Fig. 1 b, in the middle section of channel column 110, channel column 110 includes being sequentially stacked on channel
Tunneling medium layer, charge storage layer and block media layer on layer, at the both ends of channel column 110, channel column 110 includes being stacked on
Block media layer on channel layer or semiconductor layer.The lower end of channel column 110 connects with the public source zone in semiconductor substrate 101
Touching.In final 3D memory device, the upper end of channel column 110 will be connected with wiring layer, so that it is single to form effective storage
Member.The structure of the channel column 110 is, for example, ONOP (oxidenitride oxide-polysilicon).
Preferably, pseudo- channel column 130 is formed in channel hole.The internal structure of pseudo- channel column 130 and channel column 110 can be with
It is identical, and at least across at least part grid conductor in rhythmic structure of the fence.However, in final 3D memory device,
The upper end of pseudo- channel column 130 is not connected with wiring layer, so that mechanical support effect is provided solely for, without being used to form selection
Transistor and memory transistor.
Preferably, through hole is formed in semiconductor substrate 101 and insulating laminate structure, and is formed and is led in through hole
Electric channel 141 and insulation lining 142.Conductive channel 141 pass through semiconductor substrate 101 and insulating laminate structure, and with partly lead
It is separated from each other between body substrate 101 and insulating laminate structure by insulation lining 142.One end of conductive channel 141 extends to insulation
The upper surface of laminated construction, the other end extend to the lower surface of semiconductor substrate 101.
Further, through hole is formed in semiconductor substrate 101 and insulating laminate structure, and is formed in through hole
Passage of heat 143 and insulation lining 144.Passage of heat 143 passes through semiconductor substrate 101 and insulating laminate structure, and with half
It is separated from each other between conductor substrate 101 and insulating laminate structure by insulation lining 144.One end of passage of heat 143 extends to absolutely
The upper surface of edge laminated construction, the other end extend to the lower surface of semiconductor substrate 101.
As shown in Figure 6 b, in insulating laminate structure, sacrificial layer 152 is replaced as grid conductor 121 to 123, forms grid
Laminated construction.
In this step, grid line gap 151 is formed in insulating laminate structure (referring to fig. 2 a), to make using insulating layer 102
For etching stopping layer, cavity is formed by etching removal sacrificial layer 152 via grid line gap 151, and is filled out using metal layer
Cavity is filled to form grid conductor 121 to 123, wherein multiple grid conductors 121 to 123 and insulating layer 102 are alternately stacked.Phase
Ying Di, multiple channel columns 110 run through rhythmic structure of the fence.
When forming grid line gap 151, anisotropic etching can be used, is lost for example, by using dry etching, such as ion beam milling
Quarter, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in semiconductor lining
The surface at bottom 101 nearby stops.In this embodiment, grid conductor 121 to 123 is divided into a plurality of grid line by grid line gap 151.
It is folded using isotropic etching removal insulation using grid line gap 151 as etchant channel when forming cavity
Sacrificial layer 152 in layer structure is to form cavity.Isotropic etching can be using wet etching or the gas phase erosion of selectivity
It carves.Use etching solution as etchant in wet etching, wherein in the etch solution by semiconductor structure submergence.In gas
Mutually use etching gas as etchant in etching, wherein semiconductor structure is exposed in etching gas.
The situation that insulating layer 102 and sacrificial layer 152 in insulating laminate structure are made of silica and silicon nitride respectively
Under, C4F8, C4F6, CH2F2 can be used in gas phase etching using phosphoric acid solution as etchant in wet etching
With one of O2 or a variety of.In an etching step, etchant is full of grid line gap 151.Sacrificial layer in insulating laminate structure
152 end is exposed in the opening in grid line gap 151, and therefore, sacrificial layer 152 touches etchant.Etchant is stitched by grid line
The opening of gap 151 is gradually to the etched inside sacrificial layer 152 of insulating laminate structure.Due to the selectivity of etchant, the etching phase
Sacrificial layer 152 is removed for the insulating layer 102 in insulating laminate structure.
When forming grid conductor 121 to 123, using grid line gap 151 as deposit channel, using atomic layer deposition
(ALD), metal layer is filled in grid line gap 151 and cavity.
In this embodiment, metal layer is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, hexafluoro
Change tungsten WF6, the reducing gas of use is, for example, silane SiH4 or diborane B2H6.In the atomic layer deposition the step of, six are utilized
The chemisorption of the reaction product of tungsten fluoride WF6 and silane SiH4 obtains tungsten material and realizes deposition process.
As fig. 6 c, above rhythmic structure of the fence, interconnection structure is formed.
The interconnection structure includes multiple conductive channels 161 above the rhythmic structure of the fence, divides with multiple conductive channels 161
Multiple contact pads 162 for not contacting, are located at multiple wiring layers at multiple wiring layers 164 on multiple contact pads 162
Multiple external pads 165 on 164 and the conduction of interconnection is provided on the direction on the surface perpendicular to semiconductor substrate 101
Channel 163.
It is memory cell array 220 in the semiconductor structure that the step is formed, wherein rhythmic structure of the fence is together with channel column
Form selection transistor and memory transistor.In the middle section of channel column 110, grid conductor 121 to 123 and channel column
Channel layer, tunneling medium layer, charge storage layer and block media layer inside 110 together, form memory transistor.In channel column
Channel layer (or semiconductor layer) and block media layer one inside 110 both ends, grid conductor 121 to 123 and channel column 110
It rises, forms selection transistor.
Grid conductor 121,122 and 123 in rhythmic structure of the fence for example formed it is step-like, for providing conductive channel 161
Extend up to the space of corresponding grid conductor.The conductive channel and wiring layer of memory cell array 220 are located at least one absolutely
In edge layer 102.As described above, being shown in figure insulating layer 102 is single layer, however, insulating layer 102 can be actually by multiple layers
Between insulating layer form, including multiple interlayer insulating films for separating grid conductor 121,122 and 123 and for separating different cloth
Multiple interlayer insulating films of line layer.In addition, contact pad 162 and external pads 165 can also be located at individual interlayer insulating film
On.
Further, the first end of channel column 110 is commonly connected to the public source zone in semiconductor substrate 101, channel column
110 second end is connected to contact pad 162 via conductive channel 161, is then connected to accordingly via conductive channel and wiring
External pads 165.The first end of conductive channel 141 extends to the public source zone in semiconductor substrate 101, and second end is via leading
Electric channel 161 is connected to contact pad 162, is then connected to corresponding external pads 165 via conductive channel and wiring.
The bonding face of memory cell array 220 is the first surface of insulating layer 102.In this step, first surface is sudden and violent
The Free Surface of dew.The contact surface of external pads 165 exposes on the first surface.
In this embodiment, using the technique similar with conductive channel 161 and 163, by conductive channel 141 from gate stack knot
The bonding face of memory cell array 220 is extended to above structure.
As shown in fig 6d, interlayer insulating film 104 and radiator structure are sequentially formed in the second surface of semiconductor substrate 101
105。
In this step, for example, semiconductor structure is overturn, so that second surface is upward, to form interlayer insulating film 104
With radiator structure 105.The interlayer insulating film 104 is for semiconductor substrate 101 and radiator structure 105 to be separated from each other.In the reality
It applies in example, interlayer insulating film 104 is for example made of silica, and radiator structure 105 is made of the good metal of thermal conductivity or resin,
Such as copper, silver, aluminium heat conductive silica gel.
Between the step of forming interlayer insulating film 104 and radiator structure 105, further includes: the shape in interlayer insulating film 104
At the through hole being aligned with conductive channel 141, and conductive material is filled, so that conductive channel 141 is extended to layer insulation
The surface of layer 104, and the through hole being aligned with passage of heat 143 is formed in interlayer insulating film 104, and fill heat conduction material
Material, so that passage of heat 143 to be extended to the surface of interlayer insulating film 104.
The first end and second end of conductive channel 141 extends respectively to two apparent surfaces of memory cell array 220 (i.e.
Free Surface and bonding face), form external pads.The conductive channel 141 is used as a part for running through contact through hole (TAC)
Conductive path between offer cmos circuit and external circuit.
The first end and second end of passage of heat 143 extends respectively to Free Surface and the wiring of memory cell array 220
Layer 164.
Radiator structure 105 is for example by patterning, the open area including the first end for exposing conductive channel 141.
Radiator structure 105 is connected with the first end of passage of heat 143, to provide heat dissipation path.
As shown in fig 6e, the transistor (not shown) of cmos circuit is formed in semiconductor substrate 201, and in semiconductor
Interconnection structure is formed on substrate 201.
In this embodiment, semiconductor substrate 201 is, for example, monocrystalline substrate.In order to form transistor, served as a contrast in semiconductor
Multiple doped regions are formed in bottom 201.For example, semiconductor substrate 201 includes source region and the drain region of multiple transistors.
It is cmos circuit 210 in the semiconductor structure that the step is formed, wherein what is formed in semiconductor substrate 201 is more
The doped region of a transistor provides external electrical connections via interconnection structure.
Interconnection structure includes the multiple contact pads 261 being located in semiconductor substrate 201, is located at multiple contact pads 261
On multiple wiring layers 263, multiple external pads 264 on multiple wiring layers 263 and perpendicular to semiconductor substrate
The conductive channel 262 of interconnection is provided on the direction on 201 surface.Between multiple wiring layers 260 and multiple wiring layers
It is separated from each other between 260 and contact pad 261 and external pads 264 using insulating layer 202, and using in insulating layer 202
Conductive channel 262 is electrically connected to each other.
As shown in Figure 6 f, cmos circuit 210 and memory cell array 220 are bonded together into 3D memory device 200.
When cmos circuit 210 and memory cell array 220 are bonded together into 3D memory device 200, cmos circuit 210
External pads 264 in first group of pad and the external pads 165 of memory cell array 220 be in contact with each other, to realize
Being electrically connected between cmos circuit 210 and memory cell array 220, second group of weldering in the external pads 264 of cmos circuit 210
The second end of disk and the conductive channel of memory cell array 220 141 is in contact with each other, and connects so that conductive channel 141 is used as to run through
The a part of through-hole (TAC) is touched, realizes being electrically connected between cmos circuit 210 and external circuit.
In the above-described embodiment, describing 3D memory device is the bonding group comprising cmos circuit and memory cell array
Part forms passage of heat and radiator structure in memory cell array to provide heat dissipation path.In alternate embodiments, this hair
It is bright also to can be applied to only comprising memory cell array and not comprising the 3D memory device of cmos circuit, in memory cell array
Middle formation passage of heat and radiator structure are to provide heat dissipation path.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (11)
1. a kind of 3D memory device, comprising:
Rhythmic structure of the fence, the rhythmic structure of the fence include the multiple grid conductors and multiple interlayer insulating films being alternately stacked；
Multiple channel columns, the channel column is through the rhythmic structure of the fence to form transistor；And
Multiple puppet channel columns, at least partly described grid conductor of the puppet channel column in the rhythmic structure of the fence is to provide
Support,
Wherein, the pseudo- channel column of at least one of the multiple pseudo- channel column is connected with radiator structure.
2. 3D memory device according to claim 1, wherein include heat sink material in the puppet channel column.
3. 3D memory device according to claim 1, further includes:
First semiconductor substrate, the first surface and the rhythmic structure of the fence of first semiconductor substrate are adjacent；
Second insulating layer on the second surface of first semiconductor substrate, the second table of first semiconductor substrate
Face is relative to each other with first surface；And
Cover the first insulating layer of the rhythmic structure of the fence.
4. 3D memory device according to claim 3, wherein the radiator structure is located at first insulating layer.
5. 3D memory device according to claim 3, wherein the radiator structure is located at the second insulating layer.
6. 3D memory device according to claim 3, further includes: the insulation at least partially surrounding the pseudo- channel column serves as a contrast
In, for the pseudo- channel column to be separated from each other with the rhythmic structure of the fence and first semiconductor substrate.
7. 3D memory device according to claim 5, further includes: multiple wiring layers in first insulating layer,
The first end of the puppet channel column is connected to the A respective routing layer of the multiple wiring layer, and second end connects the radiator structure.
8. 3D memory device according to claim 5, further includes: be laterally extended on the surface of first insulating layer
Groove, the groove reach second sidewall, the first end of the multiple puppet channel column from the first side wall of the rhythmic structure of the fence
The groove is extended to, second end connects the radiator structure.
9. 3D memory device according to claim 8, further includes: the thermally conductive item in the groove.
10. 3D memory device according to claim 3, further includes:
Cmos circuit, the cmos circuit is bonded to the rhythmic structure of the fence by connection structure, and includes:
Second semiconductor substrate；
Transistor in second semiconductor substrate；And
Third insulating layer in second semiconductor substrate.
11. 3D memory device according to claim 10, wherein the rhythmic structure of the fence as memory cell array,
As the first bonding face, the rhythmic structure of the fence is also wrapped on the surface of first insulating layer in the memory cell array
The first external pads being located on first bonding face are included,
The surface of the second insulating layer in the cmos circuit further includes being located at as the second bonding face, the cmos circuit
The second external pads on second bonding face,
Wherein, the first bonding face of the rhythmic structure of the fence is in contact with each other with the second bonding face of the cmos circuit, and described
One external pads bond together with second external pads, to realize between the rhythmic structure of the fence and the cmos circuit
Electrical connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811139608.7A CN109300902A (en) | 2018-09-28 | 2018-09-28 | 3D memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811139608.7A CN109300902A (en) | 2018-09-28 | 2018-09-28 | 3D memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109300902A true CN109300902A (en) | 2019-02-01 |
Family
ID=65164744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811139608.7A Pending CN109300902A (en) | 2018-09-28 | 2018-09-28 | 3D memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109300902A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110896671A (en) * | 2019-03-29 | 2020-03-20 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| CN111180344A (en) * | 2020-01-02 | 2020-05-19 | 长江存储科技有限责任公司 | Three-dimensional stacked structure and preparation method |
| CN111223871A (en) * | 2020-01-14 | 2020-06-02 | 长江存储科技有限责任公司 | Preparation method of memory device and memory device |
| CN111524895A (en) * | 2019-02-05 | 2020-08-11 | 东芝存储器株式会社 | Semiconductor memory device with a memory cell having a plurality of memory cells |
| CN111863783A (en) * | 2020-07-30 | 2020-10-30 | 长江存储科技有限责任公司 | Three-dimensional packaged semiconductor structure |
| TWI709229B (en) * | 2019-02-05 | 2020-11-01 | 日商東芝記憶體股份有限公司 | Semiconductor memory device and manufacturing method thereof |
| CN112701123A (en) * | 2020-12-25 | 2021-04-23 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| US11004861B2 (en) | 2019-03-29 | 2021-05-11 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11011540B2 (en) | 2019-03-29 | 2021-05-18 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11081496B2 (en) | 2019-03-29 | 2021-08-03 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11665903B2 (en) | 2019-03-29 | 2023-05-30 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080099909A1 (en) * | 2006-10-30 | 2008-05-01 | Samsung Electronics Co., Ltd. | Wafer stacked package having vertical heat emission path and method of fabricating the same |
| US20100187670A1 (en) * | 2009-01-26 | 2010-07-29 | Chuan-Yi Lin | On-Chip Heat Spreader |
| CN102376657A (en) * | 2010-08-04 | 2012-03-14 | 南亚科技股份有限公司 | Integrated circuit structure with through via for heat evacuating |
| US20120153358A1 (en) * | 2010-12-21 | 2012-06-21 | Stmicroelectronics Pte Ltd. | Integrated heat pillar for hot region cooling in an integrated circuit |
| CN102782841A (en) * | 2010-03-03 | 2012-11-14 | 超威半导体公司 | Dummy TSV to improve process uniformity and heat dissipation |
| US20160225785A1 (en) * | 2015-01-30 | 2016-08-04 | Chaeho Kim | Semiconductor memory device and method of fabricating the same |
| US20170040337A1 (en) * | 2015-08-07 | 2017-02-09 | Jong Won Kim | Vertical memory devices having dummy channel regions |
| KR20170054142A (en) * | 2015-11-09 | 2017-05-17 | 에스케이하이닉스 주식회사 | Manufacturing method of semiconductor device |
| CN107731828A (en) * | 2017-08-21 | 2018-02-23 | 长江存储科技有限责任公司 | NAND memory and preparation method thereof |
| CN208796999U (en) * | 2018-09-28 | 2019-04-26 | 长江存储科技有限责任公司 | 3D memory device |
-
2018
- 2018-09-28 CN CN201811139608.7A patent/CN109300902A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080099909A1 (en) * | 2006-10-30 | 2008-05-01 | Samsung Electronics Co., Ltd. | Wafer stacked package having vertical heat emission path and method of fabricating the same |
| US20100187670A1 (en) * | 2009-01-26 | 2010-07-29 | Chuan-Yi Lin | On-Chip Heat Spreader |
| CN102782841A (en) * | 2010-03-03 | 2012-11-14 | 超威半导体公司 | Dummy TSV to improve process uniformity and heat dissipation |
| CN102376657A (en) * | 2010-08-04 | 2012-03-14 | 南亚科技股份有限公司 | Integrated circuit structure with through via for heat evacuating |
| US20120153358A1 (en) * | 2010-12-21 | 2012-06-21 | Stmicroelectronics Pte Ltd. | Integrated heat pillar for hot region cooling in an integrated circuit |
| US20160225785A1 (en) * | 2015-01-30 | 2016-08-04 | Chaeho Kim | Semiconductor memory device and method of fabricating the same |
| US20170040337A1 (en) * | 2015-08-07 | 2017-02-09 | Jong Won Kim | Vertical memory devices having dummy channel regions |
| KR20170054142A (en) * | 2015-11-09 | 2017-05-17 | 에스케이하이닉스 주식회사 | Manufacturing method of semiconductor device |
| CN107731828A (en) * | 2017-08-21 | 2018-02-23 | 长江存储科技有限责任公司 | NAND memory and preparation method thereof |
| CN208796999U (en) * | 2018-09-28 | 2019-04-26 | 长江存储科技有限责任公司 | 3D memory device |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111524895A (en) * | 2019-02-05 | 2020-08-11 | 东芝存储器株式会社 | Semiconductor memory device with a memory cell having a plurality of memory cells |
| CN111524895B (en) * | 2019-02-05 | 2023-11-24 | 铠侠股份有限公司 | semiconductor memory device |
| TWI709229B (en) * | 2019-02-05 | 2020-11-01 | 日商東芝記憶體股份有限公司 | Semiconductor memory device and manufacturing method thereof |
| US11011540B2 (en) | 2019-03-29 | 2021-05-18 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11502102B2 (en) | 2019-03-29 | 2022-11-15 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11943923B2 (en) | 2019-03-29 | 2024-03-26 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US10964718B2 (en) | 2019-03-29 | 2021-03-30 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11665903B2 (en) | 2019-03-29 | 2023-05-30 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11581332B2 (en) | 2019-03-29 | 2023-02-14 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11004861B2 (en) | 2019-03-29 | 2021-05-11 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| CN110896671A (en) * | 2019-03-29 | 2020-03-20 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| CN110896671B (en) * | 2019-03-29 | 2021-07-30 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| US11081496B2 (en) | 2019-03-29 | 2021-08-03 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| US11462565B2 (en) | 2019-03-29 | 2022-10-04 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabrication methods thereof |
| CN111180344B (en) * | 2020-01-02 | 2021-12-07 | 长江存储科技有限责任公司 | Three-dimensional stacked structure and preparation method |
| CN111180344A (en) * | 2020-01-02 | 2020-05-19 | 长江存储科技有限责任公司 | Three-dimensional stacked structure and preparation method |
| CN111223871A (en) * | 2020-01-14 | 2020-06-02 | 长江存储科技有限责任公司 | Preparation method of memory device and memory device |
| CN111863783A (en) * | 2020-07-30 | 2020-10-30 | 长江存储科技有限责任公司 | Three-dimensional packaged semiconductor structure |
| CN111863783B (en) * | 2020-07-30 | 2021-04-09 | 长江存储科技有限责任公司 | Three-dimensional packaged semiconductor structure |
| CN112701123B (en) * | 2020-12-25 | 2022-05-10 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN112701123A (en) * | 2020-12-25 | 2021-04-23 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109300902A (en) | 3D memory device | |
| CN109192734A (en) | 3D memory device | |
| TWI713203B (en) | Memory device and method for fabricating the same | |
| CN109037227A (en) | 3D memory device and its manufacturing method | |
| CN109300903A (en) | The three heap memory structures and manufacturing method stacked based on through silicon via | |
| CN109346473A (en) | 3D memory device and its manufacturing method | |
| CN109686739A (en) | 3D memory device and its manufacturing method | |
| CN109326557A (en) | Three-dimensional memory structure and manufacturing method | |
| CN109273453A (en) | The manufacturing method and 3D memory device of 3D memory device | |
| CN109904170A (en) | Memory device and its manufacturing method | |
| CN208796999U (en) | 3D memory device | |
| CN109390349A (en) | 3D memory device and its manufacturing method | |
| CN109003983A (en) | 3D memory device and its manufacturing method | |
| CN109712987A (en) | The manufacturing method and 3D memory device of 3D memory device | |
| CN109585454A (en) | 3D memory device and its manufacturing method | |
| CN110277404A (en) | 3D memory device and its manufacturing method | |
| CN109935596A (en) | 3D memory device and its manufacturing method | |
| CN109103199A (en) | 3D memory device and its manufacturing method | |
| CN109390303A (en) | The manufacturing method of silicon perforation technique and three-dimensional memory structure | |
| US11087844B2 (en) | Non-volatile memory device | |
| CN109346478A (en) | The manufacturing method of 3D memory device | |
| CN109712986A (en) | 3D memory device and its manufacturing method | |
| CN109712988A (en) | 3D memory device and its manufacturing method | |
| CN109148459A (en) | 3D memory device and its manufacturing method | |
| CN109449161A (en) | The manufacturing method of 3D memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |