CN111863783B

CN111863783B - Three-dimensional packaged semiconductor structure

Info

Publication number: CN111863783B
Application number: CN202010751200.6A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-07-30
Filing date: 2020-07-30
Publication date: 2021-04-09
Anticipated expiration: 2040-07-30
Also published as: CN111863783A

Abstract

The invention relates to a three-dimensional packaged semiconductor structure, comprising: a first semiconductor structure and a second semiconductor structure bonded to each other; the first semiconductor structure comprises a first substrate, one or more logic devices arranged on the first substrate, a first bonding surface positioned above the one or more logic devices, a first through hole structure penetrating through the one or more logic devices, and first micro-channels distributed in the first substrate; the second semiconductor structure comprises a second substrate, one or more storage devices arranged on the second substrate, a second bonding surface positioned above the one or more storage devices, a second through hole structure penetrating through the one or more storage devices, and second micro-channels distributed in the second substrate; and the first semiconductor structure and the second semiconductor structure are bonded with each other through the first bonding surface and the second bonding surface. The semiconductor structure can effectively dissipate heat.

Description

Three-dimensional packaged semiconductor structure

Technical Field

The invention relates to the field of semiconductors, in particular to a three-dimensional packaged semiconductor structure with a heat dissipation micro-channel and heat dissipation through hole structure.

Background

In the integrated circuit manufacturing industry, as the integration level of circuits is gradually increased, the three-dimensional packaging technology (3D-IC) breaks through the concept of the conventional planar packaging, so that a plurality of chips can be stacked in a single package to achieve multiplication of the storage capacity, which is also called a stacked 3D package. The three-dimensional packaging technology has the advantages of low power consumption, high speed and the like, so that the size and the weight of an electronic information product are greatly reduced. However, in the three-dimensional packaging process, a large amount of heat generated due to the multi-layer chip stack is accumulated inside the chip. The heat dissipated by the underlying Wafer (Wafer) or Chip (Die) or Die (Die) may cause the overlying Wafer or Chip or Die to overheat and thus be damaged. Therefore, a reasonable heat dissipation structure needs to be designed to prevent damage of the device.

Disclosure of Invention

The invention aims to provide a three-dimensional packaged semiconductor structure with a heat dissipation structure.

The present invention has been made to solve the above problems, and an aspect of the present invention is a three-dimensional packaged semiconductor structure, including: a first semiconductor structure and a second semiconductor structure bonded to each other; the first semiconductor structure comprises a first substrate, one or more logic devices arranged on the first substrate, a first bonding surface positioned above the one or more logic devices, a first through hole structure penetrating through the one or more logic devices, and first micro-channels distributed in the first substrate; the second semiconductor structure comprises a second substrate, one or more storage devices arranged on the second substrate, a second bonding surface positioned above the one or more storage devices, a second through hole structure penetrating through the one or more storage devices, and second micro-channels distributed in the second substrate; and the first semiconductor structure and the second semiconductor structure are bonded with each other through the first bonding surface and the second bonding surface.

In an embodiment of the present invention, the first bonding surface includes a plurality of first conductive contacts and a first dielectric layer thereon; the second bonding surface comprises a plurality of second conductive contacts and a second dielectric layer.

In an embodiment of the present invention, the first conductive contacts and the second conductive contacts correspond to each other one by one.

In an embodiment of the present invention, the first dielectric layer and the second dielectric layer are in contact with each other.

In an embodiment of the invention, the one or more logic devices comprise an active area and a first dummy area not comprising a functional device, the first micro-channel is located in the first substrate below the active area, and the first via structure penetrates through the dummy area and/or the active area.

In an embodiment of the invention, the one or more memory devices include a second substrate, the second substrate includes a memory array region and a second dummy region not including a functional device, and the memory array region includes a stacked structure formed by alternately stacking gate layers and dielectric layers.

In an embodiment of the invention, the second via structure penetrates through the memory array region and reaches the second substrate.

In an embodiment of the invention, the second via structure penetrates through the second virtual area.

In an embodiment of the invention, the memory array region includes a contact region penetrating through the stacked structure, and the second via structure penetrates through the stacked structure around the contact region and reaches the second substrate.

In an embodiment of the invention, the second substrate includes an array common source therein, and the second via structure penetrates through the stacked structure and reaches the array common source.

In an embodiment of the invention, the second micro channel is located in the second substrate under the memory array region and/or the second dummy region.

In one embodiment of the present invention, the first microchannel and the second microchannel include a cooling medium therein.

In an embodiment of the present invention, the first microchannel and the second microchannel are respectively connected to a cooling pump, and the cooling pump is adapted to promote circulation of the cooling medium in the first microchannel and the second microchannel.

The invention provides a micro-channel for heat dissipation and a through hole structure penetrating through a three-dimensional device in a semiconductor device, wherein the cooling medium in the heat dissipation micro-channel can take away heat in the three-dimensional packaging process, and the through hole structure fully utilizes a virtual area without a functional device, thereby being beneficial to the heat dissipation between layers of the three-dimensional semiconductor device, ensuring that the heat distribution in the semiconductor device is more uniform and avoiding local overheating. The semiconductor structure of the invention provides an effective heat dissipation structure and a heat dissipation function for the three-dimensional packaged semiconductor structure.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a schematic structural diagram of a three-dimensional packaged semiconductor structure according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a first semiconductor structure in a semiconductor structure according to an embodiment of the invention;

fig. 3 is a schematic structural diagram of a second semiconductor structure in the semiconductor structure according to an embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.

As used herein, the term "substrate" refers to a material upon which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

In the three-dimensional packaging process, the bonding process between wafers comprises the main steps of surface plasma activation, surface cleaning treatment, wafer alignment, wafer bonding, furnace tube annealing and the like. During the bonding process, a large amount of heat is generated, and the heat exists in the bonded stacked wafers and is greatly increased along with the increase of the number of the stacked wafers, so that the stability of the formed device is reduced, the performance of the device is further influenced, and even the device is damaged.

Fig. 1 is a schematic structural diagram of a three-dimensional packaged semiconductor structure 100 according to an embodiment of the invention. Referring to fig. 1, a semiconductor structure 100 of this embodiment includes: a first semiconductor structure 110 and a second semiconductor structure 120 bonded to each other, wherein the first semiconductor structure 110 includes a first substrate 111, one or more logic devices disposed on the first substrate 111, a first bonding surface located above the one or more logic devices, a first via structure 130 penetrating the one or more logic devices, and first micro-vias 140 distributed in the first substrate 111; the second semiconductor structure 120 includes a second substrate 121, one or more memory devices disposed on the second substrate 121, a second bonding surface located above the one or more memory devices, a second via structure 150 extending through the one or more memory devices, and second micro-vias 160 distributed in the second substrate 121.

The first semiconductor structure 110 and the second semiconductor structure 120 are bonded to each other through the first bonding surface and the second bonding surface. After the first bonding surface and the second bonding surface are bonded, a bonding surface 170 as shown in fig. 1 is formed.

As shown in fig. 1, the second semiconductor structure 120 is located above the first semiconductor structure 110. However, the illustration in fig. 1 is merely illustrative and is not intended to limit the absolute position between the first semiconductor structure 110 and the second semiconductor structure 120.

As shown in fig. 1, a plurality of logic devices that have already been formed may be included in the first semiconductor structure 110, and may be formed on the same wafer, sharing the same first substrate 111; the plurality of logic devices may also be formed on different wafers, and after wafer dicing, the logic devices may be recombined on the same first substrate 111. Therefore, the first semiconductor structure 110 in the present invention is not limited to being based on one wafer. Each logic device occupies a certain area on the first substrate 111. As shown in fig. 1, the first substrate 111 extends along a first direction X, which is an extending direction of a surface of the first substrate 111, and the second direction Y is perpendicular to the first direction X. The one or more logic devices shown in fig. 1 may be 2D structures or 3D structures. When the logic device is a 3D structure, the logic device forms a three-dimensional stacked structure along the second direction Y, i.e., over the first substrate 111.

The logic device in the embodiment of the present invention may be, for example, a Central Processing Unit (CPU), a microprocessor unit (MPU), an image processing unit (GPU), an Application Processor (AP), and the like, and may further include, for example, a Static Random-Access Memory (SRAM), an I/O device, and the like. The first semiconductor structure 110 and the logic devices included therein will be described later.

In the embodiment shown in fig. 1, the CPU101, the SRAM102, and the logic device 103 are arranged in the first direction X. Among them, the CPU101, the SRAM102, and the logic device 103 may be a 2D structure or a 3D structure. The logic device 103 may be any logic gate circuit or the like.

As shown in fig. 1, a plurality of first microchannels 140 are distributed in the first substrate 111. In an embodiment of the present invention, the plurality of first microchannels 140 are located entirely in the first substrate 111. Fig. 1 is a side cross-sectional view, and it will be understood by those skilled in the art from the description of fig. 1 that the plurality of first microchannels 140 may be composed of a plurality of independent microchannels, or may be interconnected. The present invention is not limited to the critical dimensions of first microchannel 140. Preferably, the critical dimension of the first micro-channel 140 is such that the micro-channel structure with a cross section of 2 rows by 24 columns can be formed in the first substrate 111 of the first semiconductor structure 100 as shown in fig. 1, and the first micro-channel 141 is also included at the two side edge portions of the first substrate 111. As shown in fig. 1, the second semiconductor structure 120 may be bonded to the first semiconductor structure 110 after wafer flipping, so that the second substrate 121 of the second semiconductor structure 120 is located on the upper surface of the semiconductor structure 100.

A plurality of memory devices that have already been formed may be included in the second semiconductor structure 210, and may be formed on the same wafer, sharing the same second substrate 121; the plurality of memory devices may also be formed on different wafers, and after wafer dicing, the plurality of memory devices may be re-assembled on the same second substrate 121. Therefore, the second semiconductor structure 120 in the present invention is not limited to being based on one wafer. Each memory device occupies a certain area on the second substrate 121. As shown in fig. 1, the second substrate 121 extends in a first direction X. The one or more memory devices shown in fig. 1 may be 2D structures or 3D structures. When the memory device is a 3D structure, the memory device forms a three-dimensional stacked structure along the second direction Y, i.e., below the second substrate 121.

The memory device in the embodiment of the present invention may be, for example, a Dynamic Random Access Memory (DRAM), a 3D NAND flash memory, a ROM, or the like.

As shown in fig. 1, a plurality of second micro-channels 160 are distributed in the second substrate 121. In an embodiment of the present invention, the plurality of second microchannels 160 are located entirely in the second substrate 111. Fig. 1 is a side cross-sectional view, and it will be understood by those skilled in the art from the description of fig. 1 that the plurality of second microchannels 160 may be composed of a plurality of independent microchannels, or may be interconnected. The invention is not limited to the critical dimensions of second microchannel 160. In the embodiment shown in fig. 1, the second micro-channels 160 are located only at both side edge portions of the second substrate 121. In other embodiments, the second microchannel 160 may also be located in a middle portion of the second substrate 121, similar to the location of the first microchannel 140.

In the embodiment shown in fig. 1, the second semiconductor structure 120 includes a 3D NAND flash memory therein. The 3D NAND flash memory includes a memory cell array and peripheral devices formed on a second substrate 121. The second semiconductor structure 120 and the memory device included therein will be described later.

As shown in fig. 1, most of the first microchannels 140 have the same cross-sectional area, and the plurality of second microchannels 160 have the same cross-sectional area. Fig. 1 is not intended to limit the specific size, number, and location of first microchannels 140 and second microchannels 160. The cross-sectional sizes of the plurality of first microchannels 140 and second microchannels 160 may be different. The present invention also does not limit the shape of the first microchannel 140 and the second microchannel 160 to a linear channel or a curved channel.

The illustration of fig. 1 is not intended to limit the specific structure and function of the logic devices and memory devices in the semiconductor structure of the present invention, which may be used to design the logic devices and memory devices to be included therein as desired to form a desired integrated circuit.

As shown in fig. 1, the first semiconductor structure 110 and the second semiconductor structure 120 are bonded at the bonding face 170 through the first bonding face and the second bonding face. At the bonding face 170, the first semiconductor structure 110 and the second semiconductor structure 120 may be bonded by means of hybrid bonding. Hybrid bonding is a direct bonding technique, for example, where a bond is formed between surfaces without the use of an intermediate layer (e.g., solder or adhesive), and both metal-to-metal and dielectric-to-dielectric bonds can be achieved. For hybrid bonding, conductive contacts for metal-to-metal bonding and dielectric layers for dielectric-to-dielectric bonding are included at both the first bonding face of the first semiconductor structure 110 and the second bonding face of the second semiconductor structure 120.

Fig. 1 shows a bonding structure of a first semiconductor structure 110 and a second semiconductor structure 120, however, fig. 1 is not intended to limit the number of wafers that are bonded in the three-dimensional packaged semiconductor structure of the present invention and the number of devices included in each wafer, and in other embodiments, more than two wafer bonding structures may be included in each of the first semiconductor structure and the second semiconductor structure.

Specific structures of the first semiconductor structure 110 and the second semiconductor structure 120 will be described below in conjunction with schematic structural diagrams of the first semiconductor structure 110 and the second semiconductor structure 120, respectively. Thus, the following may also be used to illustrate the semiconductor structure 100 shown in fig. 1.

Fig. 2 is a schematic structural diagram of a first semiconductor structure in the semiconductor structure according to an embodiment of the invention. As shown in fig. 2, the first semiconductor structure 200 of this embodiment includes three logic devices 240, which are a first logic device 241, a second logic device 242, and a third logic device 243. The three logic devices 240 are distributed in parallel along the first direction X. The first direction X and the second direction Y in fig. 2 have the same meaning as in fig. 1.

As shown in fig. 2, the first logic device 241 is a CPU core die, the second logic device 242 is an SRAM cache, and the third logic device 243 is another logic device. Doped regions such as P-wells (PW), N-wells (NW), deep N-wells (DNW), etc., which have been formed, are included in the first substrate 211 under the respective logic devices 240. Fig. 2 is merely an example, and is not intended to limit the type of doping in the substrate, and may be arranged according to the specific function of the logic device.

The one or more logic devices include an active region and a first dummy region 212 that does not include a functional device, the first micro-via 220 is located in the first substrate 211 below the active region, and the first via structure 230 extends through the dummy region and/or the active region. The active region refers to a region including an active device therein, and a large amount of heat is generated in the region where the active device is formed during a process of forming a semiconductor structure, and thus, the first micro channel 220 is located in the active region to effectively help heat dissipation from the active region.

As shown in fig. 2, the logic device 240 is located in the active area. A first microchannel 220 is distributed below the logic device 240.

Fig. 2 shows a side cross-sectional view of a first semiconductor structure 200, in which a cross-sectional view of a first microchannel 220 is shown. As shown in fig. 2, assuming that the third direction Z is perpendicular to the plane formed by the first direction X and the second direction Y, the first micro-channel 220 may be an elongated channel extending along the third direction Z. A plurality of rectangles 221 are shown in fig. 2 to represent a cross section of the first microchannel 220, which shows the cross-sectional shape and size of the first microchannel 220. The plurality of rectangles 221 shown in fig. 2 may indicate that the plurality of first microchannels 220 are arranged in parallel along the third direction Z, and the plurality of first microchannels 220 are not communicated with each other; the rectangles 221 may also represent a first microchannel 220 meandering back and forth in the first substrate 211, i.e. the first microchannels 220 represented by the rectangles 221 are interconnected, so that there is only one first microchannel 220 in total in the first substrate 211 below the active area. Of course, the first microchannel 220 may also include a plurality of microchannels that are interconnected and tortuous.

In some embodiments, the entirety of the first microchannel 220 is located in the first substrate 211.

In some embodiments, the first microchannel 220 may be partially located in one or more logic devices above the first substrate 211.

Fig. 2 is not intended to limit the specific structure, size, and distribution of first microchannels 220. As shown in fig. 2, the cross-section of the first microchannel 220 is rectangular, meaning that the first microchannel is a rectangular channel. In other embodiments, the cross-section of the first microchannel 220 can be any other shape, such as circular, oval, triangular, etc. As shown in fig. 2, the cross-sectional area of the first micro-vias 220 is significantly smaller than the size of the logic device 240 in the first semiconductor structure 200. For example, the first logic device 241(CPU) in the first semiconductor structure 200 includes 2 rows by 10 columns of micro-vias below it, and there is also a certain pitch between adjacent via cross-sections, so the ratio between the critical dimension of the first micro-via 220 and the dimension of the logic device 240 in the first semiconductor structure 200 along the first direction X is about 1: 20.

in some embodiments, the first microchannel 220 is a linear channel. In another embodiment, the first microchannel 220 is a curvilinear or irregular channel.

In some embodiments, first microchannel 220 includes a cooling medium therein, which may be a cooling liquid or gas.

In some embodiments, the first micro-channel 220 is connected to a cooling pump for promoting the circulation of a cooling medium in the first micro-channel 220, thereby removing heat generated by the first semiconductor structure 200. The cooling pump may drive the cooling medium to be cooled outside the first semiconductor structure 200, and then the cooled cooling medium is re-injected into the first micro-channel 220, so as to form an uninterrupted flow of the cooling medium in the first micro-channel 220.

For embodiments having interconnected first microchannels 220, the cooling pump flows cooling medium in from one end of the first microchannels 220 and out the other end.

For embodiments having a plurality of first microchannels 220, a cooling pump is used to facilitate the flow of cooling medium into and out of the plurality of first microchannels, respectively.

As shown in fig. 2, a first micro channel 222 may also be included in the first substrate 211 below the first dummy area 212. The size, number, and distribution of the first micro-channels 220 in different regions may be different.

As shown in fig. 2, the first dummy regions 212 are respectively located at two ends of the first semiconductor structure 200, that is, the first semiconductor structure 200 includes two separately disposed first dummy regions 212. The first dummy area 212 does not include a functional device therein. The logic device 240 is surrounded in the middle by the first virtual area 212. In forming the first semiconductor structure 200, the first dummy region 212 may be at an edge region of the corresponding die.

In the embodiment shown in fig. 2, 2 first via structures 231 respectively penetrate through the 2

first dummy regions

212, and 3 first via structures 232 penetrate through the active region including the logic device. Wherein the first via structure 232 penetrates through the dielectric material in the active region and does not penetrate or contact the logic device.

In some embodiments, the first via structure 230 is a through silicon via, formed using a through silicon via process. The through silicon via structure for heat dissipation can provide heat conduction between layers of the three-dimensional stacked structure, heat distribution in a semiconductor device can be more uniform while heat dissipation is achieved, and damage to part of the device due to local overheating is avoided.

The number and specific location of the first via structures 230 in the first semiconductor structure 200 are not limited as shown in fig. 2.

In some embodiments, the first via structure 230 may be filled with a heat dissipation material, which is a good conductor of heat, such as a metal with good thermal conductivity, for example, any one or a combination of aluminum, iron, and copper.

Referring to fig. 2, a first bonding surface 250 is included on an upper surface of the first semiconductor structure 200. The first bonding surface 250 is for indicating the position thereof, and after the first semiconductor structure 200 and the second semiconductor structure are bonded, the first bonding surface 250 is bonded with a second bonding surface in the second semiconductor structure to form the bonding surface 170 shown in fig. 1.

A plurality of first conductive contacts 251 and a first dielectric layer 252 are included on the first bonding surface 250. As shown in fig. 2, the plurality of first conductive contacts 251 are each connected to a conductive component in the logic device 240, thereby interconnecting the logic device 240 to other devices through the first conductive contacts 251. When the first bonding surface 250 is formed, a first conductive contact 251 may be formed first, and then the upper surface of the first semiconductor structure 200 is covered with a first dielectric layer 252; the top surface is then subjected to Chemical Mechanical Planarization (CMP) such that each of the first conductive contacts 251 is exposed on the top surface of the first semiconductor structure 200, and a first dielectric layer 252 is disposed between different first conductive contacts 251.

Fig. 2 is not intended to limit the number and positional distribution of the first conductive contacts 251.

Fig. 3 is a schematic structural diagram of a second semiconductor structure in the semiconductor structure according to an embodiment of the invention. Referring to fig. 3, the second semiconductor structure 300 of this embodiment includes one 3D NAND memory device 310 therein. The second semiconductor structure 300 includes a second substrate 311, and includes a memory array region 340 and a second dummy region 312 that does not include a functional device on the second substrate 311. Doped regions such as a Deep N Well (DNW), a High Voltage P Well (HVPW), etc. which have been formed are included in the second substrate 311. Fig. 3 is merely an example, and is not intended to limit the type of doping in the substrate, and may be arranged according to the specific function of the memory device. The first direction X, the second direction Y, and the third direction Z in fig. 3 have the same meanings as in fig. 1.

As shown in fig. 3, the memory array region 340 in the second semiconductor structure 300 includes a stacked structure 343 formed by alternately stacking gate layers and dielectric layers. The stacked structure 343 may be a stack in which first material layers and second material layers are alternately stacked. The first material layer and the second material layer may be selected from materials and include at least one insulating dielectric such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer and the second material layer have different etching selectivity. For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like may be used. The deposition method of the first material layer and the second material layer of the stack structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or a physical vapor deposition method such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, among various methods thereof. The first material layer can be a gate layer or a dummy gate layer, and the second material layer is a dielectric layer. The material for the gate sacrificial layer may be, for example, a silicon nitride layer. The material for the gate layer may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or may be polysilicon, doped silicon, or any combination thereof. The material for the dielectric layer may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.

The stacked structure 343 may be divided into a Core region (Core Array)341 and a Step region (SS, standing Step)342 by regions. In the core region 341, a complete stacked structure 343 and memory strings 344 through the stacked structure 343 are included. The memory string 344 is a vertical channel structure that may include a channel layer and a memory layer. Disposed sequentially from the outside inward along the radial direction of the memory string 344 are a memory layer and a channel layer. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed from an outside to an inside in a radial direction of the channel hole. A filling layer can be arranged in the channel layer. The filler layer may function as a support. The material of the fill layer may be silicon oxide. The filling layer can be solid or hollow without affecting the reliability of the device. The formation of the vertical channel structure may be accomplished using one or more thin film deposition processes, such as ALD, CVD, PVD, the like, or any combination thereof.

Included in the stepped region 342 is a contact 345 connected to the gate layer, the contact 345 extending upwardly in the second direction Y in the dielectric material 348 in the second semiconductor structure 300. The step region 342 includes a plurality of gate layers arranged in a step shape, some of the gate layers being used as Word Lines (WL), some of the gate layers being used as Bottom Select Gates (BSG), and some of the gate layers being used as Top Select Gates (TSG) in the 3D NAND flash memory. A contact 345 may be used for the extraction of a word line, a bottom select gate, or a top select gate in the second semiconductor structure 200 to facilitate interconnection with other elements. Also included in the memory Array area 340 is a Contact area (TAC) 346 that extends Through the stack 343. Contact regions 346 function as supports and/or barriers. An Array Common Source (ACS)347 may also be included in the second substrate 311.

In the embodiment shown in fig. 3, the second semiconductor structure 300 includes two second dummy regions 312 at two ends of the device, i.e., two separately disposed second dummy regions 312 are included in the second semiconductor structure 300. A portion of the second semiconductor structure 300, which is a functional part of the memory device, is surrounded in the middle by the second dummy region 312. In forming the second semiconductor structure 300, the second dummy regions 312 may be at edge regions of the respective dies.

As shown in fig. 3, a plurality of second micro-channels 320 are included in the second substrate 311 under the second dummy region 312.

Fig. 3 illustrates a side cross-sectional view of a second semiconductor structure 300, in which a cross-sectional view of a second microchannel 320 is shown. The first direction X, the second direction Y, and the third direction Z shown in fig. 3 have the same meaning as fig. 2. As shown in fig. 3, the second microchannel 320 may be an elongated channel extending along the third direction Z. A plurality of rectangles 321 are shown in fig. 3 to represent a cross section of the second microchannel 320, which shows the cross-sectional shape and size of the second microchannel 320. The plurality of rectangles 321 shown in fig. 3 may indicate that a plurality of second micro-channels 320 are arranged in parallel along the third direction Z, and the plurality of second micro-channels 320 are not communicated with each other; the plurality of rectangles 321 may also represent a second microchannel 320 meandering back and forth in the second substrate 311, i.e. the second microchannels 320 represented by the plurality of rectangles 321 are interconnected, so that there is only one second microchannel 320 in the second substrate 311. Of course, the second microchannel 320 may also include a plurality of microchannels that are interconnected and tortuous.

In some embodiments, second microchannel 320 is entirely located in second substrate 311.

In some embodiments, second microchannel 320 may be partially located in one or more memory devices above second substrate 311.

Fig. 3 is not intended to limit the specific structure, size and distribution of second microchannels 320. As shown in fig. 3, the cross-section of the second microchannel 320 is rectangular, meaning that the second microchannel is a rectangular channel. In other embodiments, the cross-section of the second microchannel 320 may be any other shape, such as circular, oval, triangular, etc. The present invention does not limit the sectional area of the second microchannel 320. According to fig. 3, there should be a considerable number of second microchannels 320 in the second substrate 311 to achieve efficient heat dissipation. As shown in fig. 3, the second micro channels 320 of 2 rows by 2 columns are included under each of the second dummy regions 321.

In some embodiments, the second microchannel 320 is a linear channel. In another embodiment, the second microchannel 320 is a curvilinear or irregular channel.

In some embodiments, second microchannel 320 includes a cooling medium therein, which may be a cooling liquid or gas.

In some embodiments, the second micro-channel 320 is coupled to a cooling pump for promoting the circulation of a cooling medium in the second micro-channel 320, thereby removing heat generated by the second semiconductor structure 300. The cooling pump may drive the cooling medium to be cooled outside the second semiconductor structure 300, and then the cooled cooling medium is re-injected into the second micro-channel 320, so as to form an uninterrupted flow of the cooling medium in the second micro-channel 320.

For embodiments having interconnected second microchannels 320, the cooling pump may flow cooling medium in from one end of the second microchannels 320 and out the other end.

For embodiments having a plurality of second microchannels 320, a cooling pump is used to facilitate the flow of cooling medium into and out of the plurality of first microchannels, respectively.

In some embodiments, a plurality of second micro-channels 320 (not shown) may also be included in the second substrate 311 under the memory array region 340 of the second semiconductor structure 300. The size, number and distribution of the second micro-channels 320 may be the same as or different from the second micro-channels 320 located under the second virtual area 312. The size, number, and distribution of the second micro-channels 320 in different regions may be different.

In the embodiment shown in FIG. 3, second micro-tunnel 320 is located in second substrate 311 below storage array region 340 and/or second dummy region 312.

In the embodiment shown in fig. 3, 2 second via structures 331 respectively penetrate 2 second dummy areas 312.

In the embodiment shown in fig. 3, the second via structure 332 penetrates the memory array region 340 and reaches the second substrate 311.

In the embodiment shown in fig. 3, the second via structure 332 penetrates the stack 343 around the contact region 346 and reaches the second substrate 311.

In the embodiment shown in fig. 3, the second via structure 333 extends through the stacked structure 343 and to the array common source 347. In these embodiments, the second via structure 333 is located on the opposite side of the electrical connection structure of the array common source 347, i.e. if the electrical connection structure is located at the back end in the third direction Z, the second via structure 333 is located at the front end in the third direction Z.

In some embodiments, the second via structure 231 is a through silicon via, formed using a through silicon via process. The through silicon via structure for heat dissipation can provide heat conduction between layers of the three-dimensional stacked structure, heat distribution in a semiconductor device can be more uniform while heat dissipation is achieved, and damage to part of the device due to local overheating is avoided.

The number and specific locations of the second via structures 330 in the second semiconductor structure 300 are not limited as shown in fig. 3.

In some embodiments, the second via structure 330 may be filled with a heat dissipation material, which is a good conductor of heat, such as a metal with good thermal conductivity, for example, any one or a combination of aluminum, iron, and copper.

Referring to fig. 3, a second bonding surface 350 is included on an upper surface of the second semiconductor structure 300. The second bonding surface 350 is for indicating the position thereof, and after the second semiconductor structure 300 and the first semiconductor structure 200 are bonded, the second bonding surface 350 is bonded with the first bonding surface 250 in the first semiconductor structure 200 to become the bonding surface 170 shown in fig. 1.

A plurality of second conductive contacts 351 and a second dielectric layer 352 are included on the second bonding surface 350. As shown in fig. 3, the plurality of second conductive contacts 351 are all connected to respective conductive features in the second semiconductor structure 300, thereby interconnecting the second semiconductor structure 300 to other devices through the second conductive contacts 351. For example, a certain word line in the 3D NAND memory is connected to other devices through the second conductive contact 351, and the like.

When forming the second bonding surface 350, a second conductive contact 351 may be formed first, and then the upper surface of the second semiconductor structure 300 is covered with a second dielectric layer 352; the top surface is then subjected to Chemical Mechanical Planarization (CMP) such that each of the second conductive contacts 351 is exposed on the top surface of the second semiconductor structure 300 with a second dielectric layer 352 between different second conductive contacts 351.

Fig. 3 is not intended to limit the number and location distribution of the second conductive contacts 351.

In a preferred embodiment, after bonding, the first conductive contact 251 in the first semiconductor structure 200 and the second conductive contact 351 in the second semiconductor structure 300 contact each other at the bonding surface 170 in a one-to-one correspondence, and at the same time, the first dielectric layer 252 and the second dielectric layer 352 contact each other, so that a hybrid bonded structure is formed at the bonding surface 170. Therefore, the semiconductor structure of the invention has the advantages of high integration level, high speed, low cost and the like brought by hybrid bonding.

In some embodiments, the first conductive contacts 251 and the second conductive contacts 351 may not be in a perfect one-to-one correspondence, and the number and location of the first conductive contacts 251 and the number and location of the second conductive contacts 351 may be different.

The first substrate and the second substrate in the present invention may be a Silicon substrate (Si), a Germanium substrate (Ge), a Silicon Germanium substrate (SiGe), a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like. In some embodiments, the first and second substrates may also be substrates comprising other elemental or compound semiconductors, such as GaAs, InP, SiC, or the like. But also a stacked structure such as Si/SiGe or the like. Other epitaxial structures may also be included, such as Silicon Germanium On Insulator (SGOI) and the like. In some embodiments, the first and second substrates may be made of a non-conductive material, such as glass, plastic, or sapphire wafers, among others. The first and second substrates shown in fig. 1-3 may have undergone some necessary processing, such as the formation of a common active region and the necessary cleaning, etc.

According to the semiconductor structure, an effective heat dissipation structure and a heat dissipation function are provided for the three-dimensional packaged semiconductor structure.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A three-dimensional packaged semiconductor structure, comprising:

a first semiconductor structure and a second semiconductor structure bonded to each other;

the first semiconductor structure comprises a first substrate, one or more logic devices arranged on the first substrate, a first bonding surface located above the one or more logic devices, a first through hole structure extending from the first bonding surface through the one or more logic devices for heat dissipation, the first through hole structure not extending through the first substrate, and first micro-channels distributed in the first substrate;

the second semiconductor structure comprises a second substrate, one or more memory devices arranged on the second substrate, a second bonding surface located above the one or more memory devices, a second through hole structure extending from the second bonding surface and penetrating through the one or more memory devices for heat dissipation, the second through hole structure not penetrating through the second substrate, and second micro-channels distributed in the second substrate; and

the first semiconductor structure and the second semiconductor structure are bonded to each other through the first bonding surface and the second bonding surface.

2. The semiconductor structure of claim 1, wherein the first bonding surface includes a plurality of first conductive contacts and a first dielectric layer thereon; the second bonding surface comprises a plurality of second conductive contacts and a second dielectric layer.

3. The semiconductor structure of claim 2, wherein the first conductive contact and the second conductive contact correspond one-to-one.

4. The semiconductor structure of claim 2, wherein the first dielectric layer and the second dielectric layer are in contact with each other.

5. The semiconductor structure of claim 1, in which the first semiconductor structure comprises an active region and a first dummy region that does not comprise a functional device, the first microchannel being located in the first substrate below the active region, the first via structure extending through the dummy region and/or the active region.

6. The semiconductor structure of claim 1, wherein the second semiconductor structure comprises a memory array region and a second dummy region not including a functional device, the memory array region comprising a stacked structure of gate layers and dielectric layers alternately stacked.

7. The semiconductor structure of claim 6, wherein the second via structure extends through the memory array region and to the second substrate.

8. The semiconductor structure of claim 6, wherein the second via structure extends through the second dummy area.

9. The semiconductor structure of claim 6, wherein the memory array region includes a contact region extending through the stack structure, and wherein the second via structure extends through the stack structure around the contact region and to the second substrate.

10. The semiconductor structure of claim 6, comprising an array common-source in the second substrate, the second via structure penetrating through the stack structure and reaching the array common-source.

11. The semiconductor structure of claim 6, in which the second microchannel is located in the second substrate below the memory array region and/or the second dummy region.

12. The semiconductor structure of claim 1, wherein the first microchannel and the second microchannel comprise a cooling medium therein.

13. The semiconductor structure of claim 12, wherein the first microchannel and the second microchannel are each coupled to a cooling pump adapted to facilitate circulation of the cooling medium through the first microchannel and the second microchannel.