CN112864317B

CN112864317B - Forming method of three-dimensional phase change memory and three-dimensional phase change memory

Info

Publication number: CN112864317B
Application number: CN202110263417.7A
Authority: CN
Inventors: 杨红心; 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-03-11
Filing date: 2021-03-11
Publication date: 2024-04-19
Anticipated expiration: 2041-03-11
Also published as: CN112864317A

Abstract

The embodiment of the application provides a method for forming a three-dimensional phase change memory and the three-dimensional phase change memory, wherein the method comprises the following steps: forming a dielectric layer positioned on a substrate, wherein at least one first etching hole is formed in the dielectric layer, and the extending direction of the first etching hole is parallel to the plane of the substrate; forming a memory array on the surface of the dielectric layer; forming at least one second etching hole at the periphery of the phase change memory array, wherein the extending direction of the second etching hole is perpendicular to the extending direction of the first etching hole; and filling a cooling agent in each first etching hole and each second etching hole respectively to correspondingly form a first cooling pipeline and a second cooling pipeline so as to form the three-dimensional phase change memory.

Description

Forming method of three-dimensional phase change memory and three-dimensional phase change memory

Technical Field

The embodiment of the application relates to the technical field of semiconductors, and relates to a method for forming a three-dimensional memory and the three-dimensional memory.

Background

With the continuous increase of the demands of various electronic devices for integration level and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the demands, and in this case, a three-dimensional memory has been developed.

The three-dimensional memory includes a memory array and peripheral devices for controlling signals to and from the memory array. Currently, a three-dimensional memory is commonly used as a three-dimensional phase change memory (Three Dimensional PHASE CHANGE memory,3D PCM), and since the phase change memory is formed by performing heat treatment on a phase change material by an electrical heating method and performing data writing through a crystalline state or an amorphous state of the phase change material, a large amount of heat is accumulated in the memory array, so that the temperature of the environment in the memory array is increased, which affects the data retention or writing performance of the phase change memory. Therefore, how to cool the memory array and keep the ambient temperature low is an important research direction in the art.

Disclosure of Invention

In view of the above, the embodiment of the application provides a method for forming a three-dimensional memory and the three-dimensional memory.

The technical scheme of the application is realized as follows:

In a first aspect, an embodiment of the present application provides a method for forming a three-dimensional memory, including:

forming a dielectric layer positioned on a substrate, wherein at least one first etching hole is formed in the dielectric layer, and the extending direction of the first etching hole is parallel to the plane of the substrate;

forming a memory array on the surface of the dielectric layer;

forming at least one second etching hole at the periphery of the memory array, wherein the extending direction of the second etching hole is perpendicular to the extending direction of the first etching hole;

And filling a cooling agent in each first etching hole and each second etching hole respectively to correspondingly form a first cooling pipeline and a second cooling pipeline so as to form the three-dimensional memory.

In some embodiments, the coolant comprises water or a thermally conductive oil.

In some embodiments, the conduit shape of the first and second heat dissipation conduits includes any one of: linear, L-shaped, U or serpentine;

When the first heat dissipation pipeline and the second heat dissipation pipeline are multiple, the first heat dissipation pipeline and the second heat dissipation pipeline are uniformly or non-uniformly distributed on the periphery of the dielectric layer and the periphery of the memory array.

In some embodiments, each of the first heat dissipation pipes is in communication with at least one of the second heat dissipation pipes, or each of the first heat dissipation pipes is independent of each of the second heat dissipation pipes;

When the first heat dissipation pipeline is communicated with the second heat dissipation pipeline, the same heat dissipation agent is filled in the first heat dissipation pipeline and the second heat dissipation pipeline;

When the first heat dissipation pipeline and the second heat dissipation pipeline are independent of each other, the same or different heat dissipation agents are filled in the first heat dissipation pipeline and the second heat dissipation pipeline.

In some embodiments, the cross-sectional shape of the first and second heat dissipation conduits includes any one of: oval, circular or any polygon.

In some embodiments, forming at least one second etching hole at a periphery of the memory array includes:

forming a peripheral insulating layer surrounding the memory array;

and etching the peripheral insulating layer to form at least one second etching hole in the peripheral insulating layer, wherein the extending direction of the second etching hole is parallel to the growth direction of the memory array.

In some embodiments, the method further comprises:

And filling a heat dissipation metal material in at least one first etching hole or at least one second etching hole to form the three-dimensional memory, wherein the heat dissipation metal material at least comprises metal tungsten.

In some embodiments, the forming a memory array on the surface of the dielectric layer includes:

forming a plurality of semiconductor stacking structures which are sequentially stacked along a third direction on the surface of the dielectric layer;

Etching the semiconductor stacked structure in a first direction and/or a second direction to form a phase change memory cell with a plurality of first gaps and/or second gaps, wherein the third direction is perpendicular to the first direction and the second direction, the third direction is perpendicular to a plane where the substrate is located, and a plane formed by the first direction and the second direction is parallel to the plane where the substrate is located;

gap material is filled in each of the first gap and/or the second gap to form the memory array.

In some embodiments, forming each of the semiconductor stack structures includes:

Sequentially stacking from bottom to top to form a first address line layer, a bottom electrode layer, a gating layer, a middle electrode layer, a phase change memory layer, a top electrode layer and a second address line layer;

Correspondingly, each semiconductor stacked structure is etched in the first direction and/or the second direction to form a phase change memory cell with a plurality of first gaps and/or second gaps, and the phase change memory cell comprises:

And etching the second address line layer, the top electrode layer, the phase change memory layer, the middle electrode layer, the gating layer, the bottom electrode layer and the first address line layer in the first direction and/or the second direction from top to bottom in sequence until the substrate is exposed, forming a plurality of first gaps and/or second gaps which are arranged along the second direction and/or the first direction, and obtaining the phase change memory cells alternately arranged with the first gaps and/or the second gaps, wherein the etching directions of the top electrode layer, the phase change memory layer, the middle electrode layer, the gating layer, the bottom electrode layer and the first address line layer are perpendicular to the first direction and the second direction.

In a second aspect, an embodiment of the present application provides a method for forming a three-dimensional memory, including:

filling a cooling agent in each first etching hole to form a first cooling pipeline;

forming a memory array on the surface of the medium layer with the first heat dissipation pipeline;

and filling the heat radiating agent in each second etching hole to form a second heat radiating pipeline so as to form the three-dimensional memory.

In a third aspect, an embodiment of the present application provides a three-dimensional memory, where the three-dimensional memory is formed by the method for forming a three-dimensional memory, including:

the dielectric layer is positioned on the substrate;

The first heat dissipation pipeline is positioned in the medium layer, the first heat dissipation pipeline is filled with a heat dissipation agent, and the extending direction of the first heat dissipation pipeline is parallel to the plane where the substrate is positioned;

a memory array located over a dielectric layer having the first heat dissipation conduit;

And the second heat dissipation pipeline is positioned at the periphery of the memory array, the second heat dissipation pipeline is filled with the heat dissipation agent, and the extending direction of the second heat dissipation pipeline is perpendicular to the extending direction of the first heat dissipation pipeline.

The embodiment of the application provides a forming method of a three-dimensional memory and the three-dimensional memory, and because at least one first etching hole in a dielectric layer and at least one second etching hole at the periphery of the memory array are respectively filled with a cooling agent, a first cooling pipeline positioned at the bottom of the memory array and a second cooling pipeline positioned at the periphery of the memory array can be formed, and the heat dissipation treatment of the memory array can be realized through the first cooling pipeline and the second cooling pipeline, so that the temperature inside the memory array is reduced, and the performance of the prepared three-dimensional memory is further improved.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

FIG. 1A is A transmission electron microscope diagram of A3D X-point memory in the related art;

FIG. 1B is a diagram showing a stacked structure of a 3D X-point memory according to the related art;

FIG. 1C is a schematic diagram of a phase change memory cell of a 3D X-point memory according to the related art;

FIG. 1D is a graph showing the thermal profile of the interior of a phase change memory cell;

FIG. 2A is a schematic flow chart of an alternative implementation of a method for forming a three-dimensional memory according to an embodiment of the present application;

FIG. 2B is a schematic diagram illustrating a cross-sectional structure of a dielectric layer according to an embodiment of the present application;

fig. 2C is a schematic structural diagram of forming a packaging dielectric layer according to an embodiment of the present application;

FIG. 2D is a cross-sectional view of a semiconductor stacked structure according to an embodiment of the present application;

FIG. 2E is a schematic diagram of a phase change memory cell in a first direction according to an embodiment of the present application;

FIG. 2F is a schematic diagram illustrating a phase change memory cell in a second direction according to an embodiment of the present application;

FIG. 2G is a schematic diagram illustrating a complete stack structure according to an embodiment of the present application;

FIG. 2H is a schematic diagram illustrating a structure of a memory array according to an embodiment of the present application;

Fig. 2I is a schematic structural diagram of forming a peripheral insulating layer according to an embodiment of the present application;

FIG. 2J is a schematic diagram of a structure for forming at least one second etching hole according to an embodiment of the present application;

fig. 2K is a schematic structural diagram of forming a first heat dissipation pipe and a second heat dissipation pipe according to an embodiment of the present application;

Fig. 2L is a schematic diagram of another structure for forming a first heat dissipation channel and a second heat dissipation channel according to an embodiment of the present application;

FIG. 3A is a schematic diagram of an implementation flow of a method for forming a three-dimensional memory according to an embodiment of the present application;

FIG. 3B is a schematic cross-sectional view of a dielectric layer according to an embodiment of the present application;

Fig. 3C is a schematic top view of a dielectric layer according to an embodiment of the present application;

FIG. 3D is a schematic diagram illustrating a structure of a memory array according to an embodiment of the present application;

FIG. 3E is a schematic diagram illustrating a structure of forming two second etching holes according to an embodiment of the present application;

Fig. 3F is a schematic structural diagram of forming a second heat dissipation pipe according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a three-dimensional memory according to an embodiment of the present application;

FIG. 5A is A schematic cross-sectional view of an alternative 3D X-point memory according to one embodiment of the present application;

fig. 5B is a schematic cross-sectional view of an alternative 3D X-point memory according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of the specific technical solutions of the present application will be given with reference to the accompanying drawings in the embodiments of the present application. The following examples are illustrative of the application and are not intended to limit the scope of the application.

In the following description, suffixes such as "module" or "unit" for representing elements are used only for facilitating the description of the present application, and have no specific meaning per se. Thus, "module" or "unit" may be used in a hybrid.

Three-dimensional phase change memories include three-dimensional cross point (3D X-point) memories that store data based on a change in resistance (e.g., in a high-resistance state or a low-resistance state) of a bulk material property. The 3D X-point memory has a transistor-less cross-point architecture that positions the memory cells at the intersections of vertical conductors, where the vertical conductors include Word Lines (WL) and Bit Lines (BL) that intersect each other perpendicularly, WL and BL typically being composed of 20nm/20nm constant width lines (line/space, L/S) formed after the patterning process. As shown in fig. 1A, which is A transmission electron microscope diagram of A3D X-point memory in the related art, the 3DX-point memory includes: a bottom bit line 101, a top bit line 102 in the same plane above the bottom bit line 101, a bottom word line 111, a top word line 112 in the same plane above the bottom word line 111, a bottom memory cell 121 located between the bottom bit line 101 and the bottom word line 111, and a top memory cell 122 located between the top bit line 102 and the top word line 112. Each top/bottom memory cell 121/122 includes at least a vertically stacked PCM element and a selector.

As shown in fig. 1B, which is a stacked structure diagram of a 3D X-point memory in the related art, each bottom bit line 101 and each top bit line 102 of the 3D X-point memory extend laterally in a bit line direction in a top plan view (parallel to a wafer plane), and each bottom word line 111 and top word line 112 extend laterally in a word line direction in a top plan view, each bottom word line 111 and top word line 112 being perpendicular to each bottom bit line 101 and each top bit line 102. Currently, as the requirements of the memory performance of the memory are increasing, more memory stacks are to be integrated into the high density application program, such as a 3D X-point memory 10 formed by one top memory cell, a 3D X-point memory 10 formed by one top memory cell and one bottom memory cell stacked, and a 3D X-point memory 10 formed by alternately stacking two top memory cells and two bottom memory cells, as shown in fig. 1B.

As shown in fig. 1C, which is a schematic diagram of a phase change memory cell of a 3D X-point memory in the related art, it can be seen that the phase change memory cell includes a first address line layer (tungsten line) 1217, a bottom electrode layer 1216, a gate layer 1215, an intermediate electrode layer 1214, a phase change memory layer 1213, a top electrode layer 1212, and a second address line layer (tungsten line) 1211, which are sequentially stacked from bottom to top. As shown in fig. 1D, since the 3D X-point memory is configured to perform writing operation by electrically heating the phase-change material, more and more heat may not be rapidly dissipated and concentrated around the phase-change memory layer 1213, and as can be seen in fig. 1C, the temperature around the phase-change memory layer 1213 may be 873K, which may increase the temperature of the internal environment of the 3D X-point memory, which may affect the data retention or writing performance, so it is important to cool the memory array and keep the internal environment of the memory at a low temperature.

Based on the above-mentioned problems of the three-dimensional memory in the related art, embodiments of the present application provide a three-dimensional memory and a method for forming the three-dimensional memory, which can reduce the ambient temperature inside the memory array, so that the ambient temperature inside the memory array is kept at a lower temperature.

Fig. 2A is a schematic flow chart of an alternative implementation of a method for forming a three-dimensional memory according to an embodiment of the present application, as shown in fig. 2A, where the method includes the following steps:

Step S201, a dielectric layer positioned on a substrate is formed.

At least one first etching hole is formed in the dielectric layer, and the extending direction of the first etching hole is parallel to the plane where the substrate is located.

Step S202, forming a memory array on the surface of the dielectric layer.

Step S203, forming at least one second etching hole on the periphery of the memory array.

The extending direction of the second etching hole is perpendicular to the extending direction of the first etching hole.

And S204, respectively filling a cooling agent in each first etching hole and each second etching hole to correspondingly form a first cooling pipeline and a second cooling pipeline so as to form the three-dimensional memory.

According to the method for forming the three-dimensional memory, disclosed by the embodiment of the application, as the at least one first etching hole in the dielectric layer and the at least one second etching hole at the periphery of the memory array are respectively filled with the cooling agent, a first cooling pipeline positioned at the bottom of the memory array and a second cooling pipeline positioned at the periphery of the memory array can be formed, and the at least one first cooling pipeline and the at least one second cooling pipeline can realize cooling treatment of the memory array, so that the temperature inside the memory array is reduced, and the performance of the prepared three-dimensional memory is further improved.

In the following, taking a three-dimensional phase change memory as an example, a method for manufacturing a three-dimensional memory according to an embodiment of the present application is described in further detail with reference to a structural cross-sectional view of the three-dimensional phase change memory in fig. 2B to 2L during a manufacturing process.

The method for forming the three-dimensional memory starts in step S201, please refer to fig. 2B and 2C, and step S201 is performed to form a dielectric layer on a substrate.

Fig. 2B is a cross-sectional structure diagram of a dielectric layer according to an embodiment of the present application, where a material of a substrate (not shown) may be any one of silicon (Si), silicon germanium alloy (SiGe), silicon carbide (SiC), aluminum oxide (Al ₂O₃), aluminum nitride (AlN), zinc oxide (ZnO), gallium oxide (Ga ₂O₃), or lithium aluminate (LiAlO ₂). Since the Si substrate is inexpensive and is easy to dope, and at the same time is easy to react to form a heterogeneous isolation layer, si is selected as the substrate in the embodiment of the present application.

The substrate may include a top surface at the front side and a bottom surface at the back side opposite the front side; the direction perpendicular to the top and bottom surfaces of the substrate is defined as a third direction, ignoring the flatness of the top and bottom surfaces. In the direction of the top and bottom surfaces of the substrate (i.e. the plane in which the substrate lies), two first and second directions intersecting each other (e.g. perpendicular to each other) are defined, based on which the plane direction of the substrate can be determined. Here, the first direction, the second direction, and the third direction are perpendicular to each other. For example, the first direction may be defined as an X-axis direction, the second direction may be defined as a Y-axis direction, and the third direction may be defined as a Z-axis direction.

In the embodiment of the present application, the dielectric layer 100 is deposited along the third direction, and the material of the dielectric layer 100 is silicon oxide, and in other embodiments, the material of the dielectric layer 100 may also be silicon oxynitride or silicon nitride.

Here, the dielectric layer may be deposited on the substrate surface by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), or thermal oxidation process.

In some embodiments, in the cross-sectional view of the structure shown in fig. 2B, the structural layer below the dielectric layer 100 is not limited, and the structural layer below the dielectric layer 100 may be a substrate or other material layer, which is not limited by the embodiment of the present application.

At least one first etching hole is formed in the dielectric layer 100, and the extending direction of the first etching hole is parallel to the plane where the substrate is located, that is, the extending direction of the first etching hole is parallel to the planes where the X axis and the Y axis are located. Here, the positional relationship of the plurality of first etching holes in the dielectric layer in the third direction is not limited.

In the embodiment of the present application, at least one first etching hole may be formed in the dielectric layer 100 by a dry etching technique, where the dry etching technique may be a photolithography technique.

With continued reference to fig. 2B, before forming at least one first etching hole, patterning the dielectric layer 100 to form a first etching mask 101, where the first etching mask 101 may be a photoresist mask or a hard mask patterned based on a photoresist; when the first etching mask 101 is a photoresist mask, the dielectric layer 100 is patterned by exposing, developing, photoresist removing, and the like, and the dielectric layer 100 is etched according to the pattern of the first etching mask, so as to form a first etching hole 100'.

In some embodiments, after the first etching holes 100' are formed, the first etching mask 101 is removed by a specific concentration of acid solution, and an encapsulation dielectric layer is formed on the dielectric layer surface. As shown in fig. 2C, in the schematic structural diagram of forming the encapsulation dielectric layer according to the embodiment of the present application, after the first etching mask is removed, an encapsulation dielectric layer 100-1 is deposited on the surface of the dielectric layer 100, the material of the encapsulation dielectric layer 100-1 is the same as that of the dielectric layer 100, the length of the encapsulation dielectric layer 100-1 in the Y-axis direction is greater than the length of the dielectric layer 100 in the Y-axis direction, and the encapsulation dielectric layer 100-1 is used for encapsulating the first etching hole 100'.

Next, referring to fig. 2D to fig. 2H, step S202 is performed to form a memory array on the surface of the dielectric layer 100.

In an embodiment of the present application, the process of forming the memory array 200 on the surface of the dielectric layer 100 includes the following steps:

In step S2021, a plurality of semiconductor stacked structures stacked in sequence along the third direction are formed on the surface of the dielectric layer.

Step S2022, etching each semiconductor stack structure in the first direction and/or the second direction to form a phase change memory cell having a plurality of first gaps and/or second gaps.

The third direction is perpendicular to the first direction and the second direction, the third direction is perpendicular to the plane where the substrate is located, and the plane formed by the first direction and the second direction is parallel to the plane where the substrate is located.

Step S2023 fills a gap material in each of the first gap and/or the second gap to form the memory array.

In some embodiments, forming each of the semiconductor stack structures includes: sequentially stacking from bottom to top to form a first address line layer, a bottom electrode layer, a gate layer, a middle electrode layer, a phase change memory layer, a top electrode layer and a second address line layer, correspondingly, etching each semiconductor stacked structure in a first direction and/or a second direction to form a phase change memory unit with a plurality of first gaps and/or second gaps, wherein the phase change memory unit comprises: and etching the second address line layer, the top electrode layer, the phase change memory layer, the middle electrode layer, the gating layer, the bottom electrode layer and the first address line layer in the first direction and/or the second direction from top to bottom in sequence until the substrate is exposed, forming a plurality of first gaps and/or second gaps which are arranged along the second direction and/or the first direction, and obtaining the phase change memory cells alternately arranged with the first gaps and/or the second gaps, wherein the etching directions of the top electrode layer, the phase change memory layer, the middle electrode layer, the gating layer, the bottom electrode layer and the first address line layer are perpendicular to the first direction and the second direction.

Fig. 2D is a schematic diagram illustrating a cross-sectional structure of forming a semiconductor stacked structure according to an embodiment of the present application, as shown in fig. 2D, a first address line layer 201-1, a bottom electrode layer 202-1, a gate layer 203, an intermediate electrode layer 202-2, a phase change memory layer 204, a top electrode layer 202-3, and a second address line layer 201-2 are sequentially deposited on a surface of a dielectric layer 100 from bottom to top to form the semiconductor stacked structure 200'.

Here, the first address line layer 201-1 and the second address line layer 201-2 are bit lines or word lines of the three-dimensional memory, respectively, and materials of the first address line layer 201-1 and the second address line layer 201-2 include, but are not limited to, at least one of: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon, polysilicon, doped silicon, silicide, or any combination thereof. The materials of the bottom electrode layer 202-1, the intermediate electrode layer 202-2, and the top electrode layer 202-3 may be carbon materials, such as amorphous carbon (Amorphous Carbon, a-C). The material of the material layer of the gate layer 203 may include any suitable ovonic threshold switch (Ovonic Threshold Switch, OTS) material, such as Zn _xTe_y、Ge_xTe_y、Nb_xO_y or Si _xAs_yTe_z, etc. The phase change material of phase change memory layer 204 includes a chalcogenide-based alloy (chalcogenide glass), such as a Ge ₂Sb₂Te₅ (GST) alloy, or any other suitable phase change material.

Fig. 2E is a schematic structural diagram of a phase change memory cell in a first direction provided in an embodiment of the present application, and fig. 2F is a schematic structural diagram of a phase change memory cell in a second direction provided in an embodiment of the present application, as shown in fig. 2E and 2F, in the embodiment of the present application, a process of etching the semiconductor stacked structure 200 'includes two etching processes, wherein the first etching process etches the semiconductor stacked structure 200' in the first direction to obtain a first etched semiconductor stacked structure 200'-1, and the second etching process etches the first etched semiconductor stacked structure 200' -1 in the second direction to obtain a second etched semiconductor stacked structure 200'-2, and a plurality of first gaps 1' and/or second gaps 2 'arranged along the second direction and/or the first direction can be formed through the two etching processes, so as to obtain the phase change memory cells 3' alternately arranged with each of the first gaps 1 'and/or each of the second gaps 2'.

Fig. 2G is a schematic structural diagram of forming a complete stack structure according to an embodiment of the present application, as shown in fig. 2G, a gap material 4' is filled in the first gap and the second gap to form a complete stack structure 20, where the gap material at least includes: siO ₂ or SiO ₂ aerogel.

In an actual implementation, a photoresist mask (not shown) may be formed on the semiconductor stack structure, and the photoresist mask may be patterned by exposure and development. The semiconductor stack structure is etched based on the photoresist mask or based on the photoresist mask patterned hard mask.

In some embodiments, the detailed process of forming the phase change memory cell includes the steps of:

And S10, sequentially etching the top electrode layer and the phase change memory layer from top to bottom in the first direction until the middle electrode layer is exposed, so as to form a plurality of first sub-gaps and first phase change structures which are arranged at intervals along the second direction.

It should be appreciated that after forming the first phase change structures, a first sub-encapsulation layer is deposited on the surface of each of the first phase change structures, where the first sub-encapsulation layer may be a cyclically alternating layer of silicon nitride layers, silicon nitride layers and oxide layers.

And S20, sequentially etching the middle electrode layer, the gating layer, the bottom electrode layer and the first address line layer from top to bottom in the first direction until the dielectric layer is exposed, so as to form the first gaps and the first phase change memory cells which are alternately arranged along the second direction. Here, the first phase change memory cell wraps the first phase change structure, and the first gap wraps the first sub-gap.

It should be appreciated that after forming the first phase change memory cells, a first encapsulation layer is deposited on the surface of each of the first phase change memory cells, where the first encapsulation layer may be a cyclically alternating layer of silicon nitride layers, and oxide layers.

In some embodiments, a gap material is filled in the first gap where the first encapsulation layer is deposited, the gap material being used to isolate heat conduction between every two adjacent first phase change memory cells.

In some embodiments, after etching the semiconductor stacked structure in the first direction, a second address line layer, i.e., a word line layer of the three-dimensional memory, is formed on a surface of the etched semiconductor stacked structure.

And S30, sequentially etching the second address line layer, the top electrode layer and the phase change memory layer from top to bottom in the second direction until the middle electrode layer is exposed, so as to form a second sub-gap and a second phase change structure body which are alternately arranged along the first direction.

It will be appreciated that after the formation of the second phase change structures, a second sub-encapsulation layer is deposited on the surface of each of the second phase change structures, where the second sub-encapsulation layer may be a cyclically alternating layer of silicon nitride layers, silicon nitride layers and oxide layers.

And S40, sequentially etching the middle electrode layer, the gating layer, the bottom electrode layer and the first address line layer from top to bottom by taking the bottom of each second sub-gap as an etching starting point in the second direction until the dielectric layer is exposed, so as to form second gaps and second phase change memory cells which are alternately arranged along the first direction, wherein the second phase change memory cells wrap the second phase change structure body, and the second gaps wrap the second sub-gaps.

It should be appreciated that after forming the second phase change memory cells, a second encapsulation layer is deposited on the surface of each of the second phase change memory cells, where the second encapsulation layer may be a cyclically alternating layer of silicon nitride layers, and oxide layers.

In some alternative embodiments, the second gap in which the second encapsulation layer is deposited is filled with a gap material for isolating heat conduction between every two adjacent second phase change memory cells.

Here, the first phase change memory cell and the second phase change memory cell constitute the phase change memory cell in the above embodiment.

Through the steps S10 to S40, a complete stack structure can be formed, and the memory array in the embodiment of the present application is formed by stacking a plurality of complete stack structures in turn, where the memory array includes two stack results as an example.

Fig. 2H is a schematic structural diagram of forming a memory array according to an embodiment of the present application, as shown in fig. 2H, the memory array 200 includes a first stack structure 20 and a second stack structure 20' formed on a surface of the first stack structure 20, where the first stack structure 20 and the second stack structure 20' have the same structure, and a detailed formation process of the stack structure is described below by taking the second stack structure 20' as an example.

First, a second address line layer 201-2', a bottom electrode layer 202-1', a gate layer 203', an intermediate electrode layer 202-2', a phase change memory layer 204', a top electrode layer 202-3', and a first address line layer 201-1' are sequentially stacked on a surface of a second address line layer 201-2 of a first stack structure 20; and etching the first address line layer, the top electrode layer, the phase change memory layer, the middle electrode layer, the gating layer, the bottom electrode layer and the second address line layer in the first direction and/or the second direction from top to bottom in sequence until the second address line layer of the first stack structure is exposed, so as to form a plurality of first gaps and/or second gaps which are arranged along the second direction and/or the first direction, and obtain the phase change memory cells which are alternately arranged with the first gaps and/or the second gaps.

Here, the second address line layer (word line) 201-2 of the first stack structure 20 is in contact with the second address line layer (word line) 201-2 'of the second stack structure 20'. When the third stack structure and the fourth stack structure are formed on the surface of the second stack structure, the forming method of the third stack structure and the forming method of the first stack structure are completely the same, and the forming method of the fourth stack structure and the forming method of the second stack structure are completely the same, so that a memory array with any number of stack structures can be formed according to the forming methods of the first stack structure and the second stack structure.

Next, referring to fig. 2I to 2J, step S203 is performed to form at least one second etching hole on the periphery of the memory array 200.

In an embodiment of the present application, at least one second etching hole is formed at the periphery of the memory array 200, including the following steps:

step S2031, forming a peripheral insulating layer surrounding the memory array.

Fig. 2I is a schematic structural diagram of forming a peripheral insulating layer according to an embodiment of the present application, and as shown in fig. 2I, a peripheral insulating layer 205 is formed on the periphery of the memory array 200, where the peripheral insulating layer may be formed on the periphery of the memory array 200 by any deposition method. In an embodiment of the present application, the peripheral insulating layer 205 is used to isolate the memory array 200 from other peripheral devices, and the peripheral insulating layer 205 may be an oxide layer, for example, a material of the peripheral insulating layer may be silicon oxide.

Step S2032, etching the peripheral insulating layer, and forming at least one second etching hole in the peripheral insulating layer 205, where the extension direction of the second etching hole is parallel to the growth direction of the memory array.

In the embodiment of the application, at least two second etching holes can be formed in the peripheral insulating layer by a dry etching technology, wherein the dry etching technology can be a photoetching technology.

Fig. 2J is a schematic structural diagram of forming at least one second etching hole according to an embodiment of the present application, as shown in fig. 2J, the peripheral insulating layer is patterned to form a second etching mask 101', where the second etching mask 101' may be a photoresist mask or a hard mask patterned based on a photoresist; when the second etching mask is a photoresist mask, the peripheral insulating layer is patterned through steps of exposure, development, photoresist removal, and the like, and the peripheral insulating layer 205 is etched through the second etching mask 101', so that two second etching holes 205' are formed. The extending direction of the second etching hole is parallel to the growing direction of the memory array, and the growing direction of the memory array is perpendicular to the plane where the substrate is located, namely, the extending direction of the second etching hole is perpendicular to the plane where the substrate is located.

In some embodiments, after the second etching holes 205 'are formed, the second etching mask 101' is removed by a specific concentration of acid solution.

Next, referring to fig. 2K and 2L, step S204 is performed to fill the first etching holes and the second etching holes with a coolant respectively, so as to form a first heat dissipation pipeline and a second heat dissipation pipeline correspondingly, so as to form the three-dimensional memory.

Here, the heat-dissipating agent includes: water or a thermally conductive oil. In other embodiments, the coolant may also include any other medium having a relatively high specific heat capacity.

In some embodiments, the conduit shapes of the first and second heat dissipation conduits include, but are not limited to, at least one of: in other embodiments, the first heat dissipation pipe and the second heat dissipation pipe may have a V-shape, a W-shape, an M-shape, an X-shape, or the like. Here, the shapes of the first heat dissipation duct and the second heat dissipation duct are not limited.

In some embodiments, the cross-sectional shape of the first and second heat dissipation conduits may be elliptical, circular, or any polygonal. In other embodiments, the cross-sectional shapes of the first heat dissipation pipe and the second heat dissipation pipe may also be heart-shaped, circular ring-shaped, etc.

As shown in fig. 2K, in the schematic structural diagram of forming the first heat dissipation pipeline and the second heat dissipation pipeline according to the embodiment of the present application, water is filled in each of the first etching holes and each of the second etching holes, respectively, so as to form a first heat dissipation pipeline 100 "and a second heat dissipation pipeline 205", and the pipeline shapes of the first heat dissipation pipeline and the second heat dissipation pipeline in fig. 2K are all straight.

In some embodiments, when the first heat dissipation pipeline and the second heat dissipation pipeline are multiple, the first heat dissipation pipeline and the second heat dissipation pipeline are uniformly or non-uniformly arranged on the periphery of the dielectric layer and the memory array respectively. Here, the non-uniform arrangement includes: arranged at random intervals, at progressively increasing intervals, or at progressively decreasing intervals.

In some embodiments, when the plurality of first heat dissipation pipes are uniformly arranged on the dielectric layer, the plurality of first heat dissipation pipes are also arranged in parallel; when the plurality of second heat dissipation pipelines are uniformly arranged at the periphery of the memory array, the plurality of second heat dissipation pipelines are also arranged in parallel. When the plurality of first heat dissipation pipelines are unevenly distributed in the medium layer, the plurality of first heat dissipation pipelines can be distributed in parallel or non-parallel; when the plurality of second heat dissipation pipes are unevenly distributed around the memory array, the plurality of second heat dissipation pipes may be arranged in parallel or non-parallel.

In this embodiment of the present application, each of the first heat dissipation pipes is communicated with at least one of the second heat dissipation pipes, or each of the first heat dissipation pipes is independent of each of the second heat dissipation pipes; as shown in fig. 2K, one first heat dissipation duct 100 "communicates with two second heat dissipation ducts 205". When the first heat dissipation pipeline is communicated with the second heat dissipation pipeline, the same heat dissipation agent is filled in the first heat dissipation pipeline and the second heat dissipation pipeline; when the first heat dissipation pipeline and the second heat dissipation pipeline are independent of each other, the same or different heat dissipation agents are filled in the first heat dissipation pipeline and the second heat dissipation pipeline.

In some embodiments, the method of forming the three-dimensional memory further comprises: and filling a heat dissipation metal material in at least one first etching hole or at least one second etching hole to form the three-dimensional memory, wherein the heat dissipation metal material at least comprises metal tungsten.

Here, the heat dissipation metal material includes any one of the following: metallic tungsten, metallic cobalt, metallic copper and metallic aluminum. As shown in fig. 2L, another schematic structural diagram of forming the first heat dissipation pipeline and the second heat dissipation pipeline according to the embodiment of the present application is shown, it can be seen that the first etching hole is filled with water, one second etching hole is filled with heat dissipation metal material, and the other second etching hole is filled with water, so that the first heat dissipation pipeline 100 "and the second heat dissipation pipeline 205" are correspondingly formed, and in fig. 2L, the first heat dissipation pipeline and the second heat dissipation pipeline are both in straight lines.

In the embodiment of the application, the heat dissipation treatment of the memory array can be realized by forming the first heat dissipation pipeline positioned at the bottom of the memory array and forming the second heat dissipation pipeline positioned at the periphery of the memory array, so that the ambient temperature in the memory array is reduced, and the performance of the prepared three-dimensional memory is further improved.

Fig. 3A is a schematic implementation flow chart of a method for forming a three-dimensional memory according to an embodiment of the present application, as shown in fig. 3A, where the method includes the following steps:

Step S301, a dielectric layer positioned on a substrate is formed.

And step S302, filling a cooling agent in each first etching hole to form a first cooling pipeline.

And step S303, forming a memory array on the surface of the dielectric layer with the first heat dissipation pipeline.

Step S304, forming at least one second etching hole on the periphery of the memory array.

And step S305, filling the heat radiating agent in each second etching hole to form a second heat radiating pipeline so as to form the three-dimensional memory.

According to the method for forming the three-dimensional memory, the first heat dissipation pipeline positioned at the bottom of the memory array and the second heat dissipation pipeline positioned at the periphery of the memory array are formed, so that heat dissipation treatment of the memory array can be realized by the first heat dissipation pipeline and the second heat dissipation pipeline, the temperature inside the memory array is reduced, and the performance of the prepared three-dimensional memory is improved.

In the following, taking a three-dimensional phase change memory as an example, a method for manufacturing a three-dimensional memory according to an embodiment of the present application is described in further detail with reference to a structural cross-sectional view of the three-dimensional phase change memory in fig. 3B to 3F during a manufacturing process.

The method for forming the three-dimensional memory begins in step S301 with forming a dielectric layer over a substrate.

In this embodiment of the present application, the material of the dielectric layer 100 is silicon oxide, and the extending direction of the first etching hole is parallel to the plane where the substrate is located, and the cross section of the first etching hole is square.

The implementation procedure and the implemented function of step S301 are the same as those of step S201 in the above-described embodiment, and will be understood with reference to the above-described embodiment.

Next, referring to fig. 3B and 3C, step S302 is performed to fill the first etching holes with a cooling agent to form first cooling channels.

Here, the heat-dissipating agent includes: water or a thermally conductive oil. The duct shape of the first heat dissipation duct includes, but is not limited to, at least one of: in other embodiments, the first heat dissipation pipe may have a V-shape, W-shape, M-shape, X-shape, or the like.

In some embodiments, when the plurality of first heat dissipation pipes is provided, the plurality of first heat dissipation pipes are uniformly or non-uniformly arranged in the dielectric layer.

Fig. 3B is a cross-sectional view of a dielectric layer provided by an embodiment of the present application, and fig. 3C is a schematic top view of a dielectric layer provided by an embodiment of the present application, and it can be seen in conjunction with fig. 3B and fig. 3C that two first heat dissipation pipes 100"-1 and 100" -2 are formed inside the dielectric layer 100. Here, the shapes of the first heat dissipation pipes 100"-1 and the first heat dissipation pipes 100" -2 are U-shaped, and the depth positions of the two first heat dissipation pipes in the dielectric layer 100 are different, that is, the positions of the first heat dissipation pipes 100"-1 and the first heat dissipation pipes 100" -2 in the Z-axis direction are different.

Next, referring to fig. 3D, step S303 is performed to form a memory array on the surface of the dielectric layer with the first heat dissipation channel.

The implementation procedure and the implemented function of step S303 are the same as those of step S202 in the above-described embodiment, and will be understood with reference to the above-described embodiment.

Fig. 3D is a schematic diagram of a structure for forming a memory array according to an embodiment of the present application, and as shown in fig. 3D, a memory array 200 is formed on a surface of a dielectric layer 100 having a first heat dissipation pipe 100"-1 and a first heat dissipation pipe 100" -2.

It should be understood that only a schematic diagram of the memory array is shown in fig. 3D, and for the detailed structure of the memory array and the detailed formation process of the memory array, please refer to the above embodiment for understanding.

Next, referring to fig. 3E, step S304 is performed to form at least one second etching hole on the periphery of the memory array. The extending direction of the second etching hole is perpendicular to the extending direction of the first etching hole.

In an embodiment of the present application, forming at least one second etching hole on the periphery of the memory array includes the following steps:

Step S3041, forming a peripheral insulating layer wrapping the memory array.

Step S3042, etching the peripheral insulating layer to form at least one second etching hole in the peripheral insulating layer, where the extending direction of the second etching hole is parallel to the growth direction of the memory array.

Fig. 3E is a schematic structural diagram of forming two second etching holes according to an embodiment of the present application, as shown in fig. 3E, a peripheral insulating layer 205 surrounding the memory array is formed on the periphery of the memory array 200, and four second etching holes, namely, a second etching hole 205'-1, a second etching hole 205' -2, a second etching hole 205'-3 and a second etching hole 205' -4, are formed in the peripheral insulating layer 205 through photolithography. The extending direction of the second etching hole is parallel to the growing direction of the memory array, and the growing direction of the memory array is perpendicular to the plane where the substrate is located, namely, the extending direction of the second etching hole is perpendicular to the plane where the substrate is located.

For technical details not disclosed in step S304, please refer to the above embodiment for step S203 for understanding.

Next, referring to fig. 3F, step S305 is performed to fill the second etching holes with the coolant to form second heat dissipation channels, so as to form the three-dimensional memory.

The heat-dissipating agent comprises: water or a thermally conductive oil. Fig. 3F is a schematic structural diagram of forming a second heat dissipation pipe according to an embodiment of the present application, as shown in fig. 3F, water is filled in the second etching holes 205'-2 and 205' -3 to form a second heat dissipation pipe 205"-2 and 205" -3, and heat conduction oil is filled in the second etching holes 205'-1 and 205' -4 to form a second heat dissipation pipe 205"-1 and 205" -4. Here, the shapes of the second heat dissipation pipes 205"-1, the second heat dissipation pipes 205" -2, the second heat dissipation pipes 205"-3, and the second heat dissipation pipes 205" -4 are all linear.

In the embodiment of the application, the second heat dissipation pipeline and the first heat dissipation pipeline are mutually independent. In some embodiments, when the second heat dissipation pipes are plural, the plural second heat dissipation pipes are uniformly or non-uniformly arranged at the periphery of the memory array.

The method for forming the three-dimensional memory according to the embodiment of the present application is similar to the method for forming the three-dimensional memory according to the above embodiment, and for technical features not described in detail in the embodiment of the present application, please refer to the above embodiment for understanding.

The embodiment of the present application further provides a three-dimensional memory formed by the method for forming a three-dimensional memory provided by the embodiment of the present application, and fig. 4 is a schematic structural diagram of the three-dimensional memory provided by the embodiment of the present application, as shown in fig. 4, where the three-dimensional memory 40 includes:

dielectric layer 400 is located over the substrate.

At least one first heat dissipation pipe 400 'is located in the dielectric layer 400, and the first heat dissipation pipe 400' is filled with a heat dissipation agent, and the extending direction of the first heat dissipation pipe is parallel to the plane where the substrate is located.

A memory array 401 is located over the dielectric layer 400 with the first heat sink pipe 400'.

At least one second heat dissipation pipe 401'-1 and 401' -2 is located at the periphery of the memory array 401, and the second heat dissipation pipe 401'-1 and the second heat dissipation pipe 401' -2 are filled with the heat dissipation agent, and the extending direction of the second heat dissipation pipe is perpendicular to the extending direction of the first heat dissipation pipe.

Here, the pipe shapes of the first heat dissipation pipe 400', the second heat dissipation pipe 401' -1, and the second heat dissipation pipe 401' -2 include, but are not limited to, at least one of: linear, L-shaped, U-shaped or serpentine; each of the first heat dissipation pipes and each of the second heat dissipation pipes are uniformly or non-uniformly arranged at the periphery of the dielectric layer 400 and the memory array 401, respectively.

In some embodiments, the coolant comprises water or a thermally conductive oil. Each first heat dissipation pipeline is communicated with at least one second heat dissipation pipeline, or each first heat dissipation pipeline and each second heat dissipation pipeline are independent; when the first heat dissipation pipeline is communicated with the second heat dissipation pipeline, the same heat dissipation agent is filled in the first heat dissipation pipeline and the second heat dissipation pipeline; when the first heat dissipation pipeline and the second heat dissipation pipeline are independent of each other, the same or different heat dissipation agents are filled in the first heat dissipation pipeline and the second heat dissipation pipeline. In the embodiment of the present application, the first heat dissipation pipe 400' is communicated with the second heat dissipation pipe 401' -1 and the second heat dissipation pipe 401' -2, and the first heat dissipation pipe and the second heat dissipation pipe are filled with coolant water.

In some embodiments, at least one first etching hole is formed inside the dielectric layer, and the extending direction of the first etching hole is parallel to the plane of the substrate; the at least one first heat dissipation pipe is formed by filling the heat dissipation agent in each first etching hole. And forming at least one second etching hole at the periphery of the memory array, wherein the extending direction of the second etching hole is perpendicular to the extending direction of the first etching hole.

In some embodiments, at least one of the first heat dissipation channels or at least one of the second heat dissipation channels has a heat dissipation metal material therein, wherein the heat dissipation metal material comprises at least tungsten metal.

In some embodiments, the memory array is formed by: forming a plurality of semiconductor stacking structures which are sequentially stacked along a third direction on the surface of the dielectric layer; etching the semiconductor stacked structure in a first direction and/or a second direction to form a phase change memory cell with a plurality of first gaps and/or second gaps, wherein the third direction is perpendicular to the first direction and the second direction, the third direction is perpendicular to a plane where the substrate is located, and a plane formed by the first direction and the second direction is parallel to the plane where the substrate is located; gap material is filled in each of the first gap and/or the second gap to form the memory array.

The three-dimensional memory provided by the embodiment of the present application is formed by the three-dimensional memory forming method in the above embodiment, and for technical features of the embodiment of the present application that are not described in detail, please refer to the above embodiment for understanding, and details are not described here.

The three-dimensional memory provided by the embodiment of the application comprises: the at least one first heat dissipation pipeline, the memory array and the at least one second heat dissipation pipeline are arranged at the bottom of the memory array, and the at least one second heat dissipation pipeline is arranged at the periphery of the memory array, so that heat dissipation treatment of the memory array can be realized through the first heat dissipation pipeline and the second heat dissipation pipeline, the ambient temperature inside the memory array is reduced, and the performance of the three-dimensional memory is improved.

In addition, embodiments of the present application propose a novel cooling system to form a 3D X-point memory. In the proposed cooling system for stacking 3D X-points, a novel cooling water piping system (corresponding to the first heat dissipation duct and the second heat dissipation duct in the above-described embodiment) is formed around the memory array. All heat generated by the operation of the memory array can be carried away by the cooling water piping system and the ambient temperature inside the 3D X-point memory can be kept at a low level, thus improving the operation and data retention performance of the memory array.

As shown in fig. 5A, which is A schematic cross-sectional view of an alternative 3D X-point memory according to an embodiment of the present application, it can be seen that A cooling water pipeline system 501 'is formed around the memory array 501, and when the memory array 501 is packaged, cooling water (corresponding to the coolant in the above embodiment) is connected to the cooling water pipeline system 501', so that heat generated by the memory array can be rapidly dissipated.

In embodiments of the present application, the accumulated heat inside the memory array may also be conducted by forming a metal wall around the memory array, for example, the metal wall may be: tungsten walls, copper walls, or aluminum walls, etc. fig. 5B is a schematic cross-sectional view of an alternative 3D X-point memory provided by an embodiment of the present application, as shown in fig. 5B, where both the W-wall 501 "and the cooling water piping 501' have been formed around the memory array 501, and where the cooling water is to be connected to the cooling water piping 501' when packaging the memory array, so that heat can be quickly conducted to the W-wall 501" and through the W-wall 501 "to the cooling water piping 501', and heat can be quickly carried away through the cooling water piping.

In some embodiments, the cooling water pipe system may include a plurality of cooling water pipes (corresponding to the first heat radiation pipe or the second heat radiation pipe in the above embodiments) that communicate with each other or are independent of each other in the X-direction or the Y-direction, or the cooling water pipe system may include a plurality of cooling water pipes that communicate with each other or are independent of each other in the X-direction and the Y-direction.

In some embodiments, the cooling water pipe system may further include a plurality of cooling water pipes communicating with each other or independent of each other in the X direction and a metal wall in the Y direction, or the cooling water pipe system may further include a plurality of cooling water pipes communicating with each other or independent of each other in the Y direction and a metal wall in the X direction.

In some embodiments, the cooling water pipe system may further include a metal wall and a plurality of cooling water pipes in an X-direction, or the cooling water pipe system may further include a metal wall and a plurality of cooling water pipes in a Y-direction.

In some embodiments, the cooling water piping system may also be a conductive coil that conducts heat inside the memory array by forming a conductive coil around the memory array.

The 3D X-point memory provided by the embodiment of the application has the advantages that the cooling water pipeline system is formed around the memory array, so that the heat in the memory array can be quickly conducted through the cooling water pipeline system, the ambient temperature in the memory array can be kept at a lower level, and further, the performance of the memory array can be kept.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined, or some features may be omitted, or not performed.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The features disclosed in the embodiments of the method or the apparatus provided by the application can be arbitrarily combined without conflict to obtain new embodiments of the method or the apparatus.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method of forming a three-dimensional phase change memory, the method comprising:

forming a phase change memory array on the surface of the dielectric layer;

Forming at least one second etching hole at the periphery of the phase change memory array, wherein the extending direction of the second etching hole is perpendicular to the extending direction of the first etching hole;

Filling a heat radiation agent in each first etching hole and each second etching hole respectively to correspondingly form a first heat radiation pipeline and a second heat radiation pipeline so as to form the three-dimensional phase change memory; each of the plurality of first heat dissipation pipelines positioned inside the dielectric layer is communicated with two second heat dissipation pipelines positioned at the left side and the right side of the periphery of the phase change memory array to form a plurality of U-shaped heat dissipation pipelines, and the plurality of U-shaped heat dissipation pipelines are distributed at gradually increased intervals in the direction away from the memory array so as to reduce heat accumulated in a phase change memory layer in the phase change memory array; wherein the heat-dissipating agent comprises water or heat-conducting oil.

2. The method of claim 1, wherein the conduit shape of the first and second heat dissipation conduits comprises any one of: linear, L-shaped, U-shaped or serpentine;

When the first heat dissipation pipelines and the second heat dissipation pipelines are multiple, the first heat dissipation pipelines and the second heat dissipation pipelines are uniformly or non-uniformly distributed on the peripheries of the dielectric layer and the memory array respectively.

3. The method of claim 1, wherein each of the first heat dissipation conduits is independent of each of the second heat dissipation conduits;

4. The method of claim 1, wherein the cross-sectional shape of the first and second heat dissipation conduits comprises any one of: oval, circular or any polygon.

5. The method of claim 1, wherein forming at least one second etch hole at a periphery of the memory array comprises:

forming a peripheral insulating layer surrounding the memory array;

6. The method according to claim 1, wherein the method further comprises:

and filling a heat dissipation metal material in at least one first etching hole or at least one second etching hole to form the three-dimensional phase change memory, wherein the heat dissipation metal material at least comprises metal tungsten.

7. The method of claim 1, wherein forming a memory array on the dielectric layer surface comprises:

8. The method of claim 7, wherein forming each of the semiconductor stack structures comprises:

9. A method of forming a three-dimensional phase change memory, the method comprising:

forming a phase change memory array on the surface of the medium layer with the first heat dissipation pipeline;

Filling the heat radiating agent in each second etching hole to form a second heat radiating pipeline so as to form the three-dimensional phase change memory;

each of the plurality of first heat dissipation pipelines is communicated with two second heat dissipation pipelines positioned at the left side and the right side of the periphery of the phase change memory array to form a plurality of U-shaped heat dissipation pipelines, and the plurality of U-shaped heat dissipation pipelines are distributed at gradually increased intervals in the direction away from the phase change memory array so as to reduce heat accumulated in a phase change memory layer in the phase change memory array; wherein the heat-dissipating agent comprises water or heat-conducting oil.

10. A three-dimensional phase change memory formed by the method of any one of claims 1 to 9, comprising:

the dielectric layer is positioned on the substrate;

the second heat dissipation pipeline is positioned at the periphery of the phase change memory array, the second heat dissipation pipeline is filled with the heat dissipation agent, and the extending direction of the second heat dissipation pipeline is perpendicular to the extending direction of the first heat dissipation pipeline;

Each of the plurality of first heat dissipation pipelines is communicated with two second heat dissipation pipelines positioned at the left side and the right side of the periphery of the phase change memory array to form a plurality of U-shaped heat dissipation pipelines, and the plurality of U-shaped heat dissipation pipelines are distributed at gradually increased intervals in the direction away from the phase change memory array; wherein the heat-dissipating agent comprises water or heat-conducting oil.