CN112951991B - Phase change memory and preparation method thereof - Google Patents
Phase change memory and preparation method thereof Download PDFInfo
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- CN112951991B CN112951991B CN202110198358.XA CN202110198358A CN112951991B CN 112951991 B CN112951991 B CN 112951991B CN 202110198358 A CN202110198358 A CN 202110198358A CN 112951991 B CN112951991 B CN 112951991B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
- H10N70/8616—Thermal insulation means
Abstract
The embodiment of the disclosure discloses a phase change memory and a preparation method thereof, wherein the phase change memory comprises: a plurality of phase change memory cells arranged in parallel and positioned on the substrate; an electrically insulating isolation structure located between adjacent phase change memory cells for electrically isolating adjacent phase change memory cells; wherein, the constituent material of the isolation structure comprises ceramic.
Description
Technical Field
The present disclosure relates to the field of microelectronic devices, and more particularly, to a phase change memory and a method for fabricating the same.
Background
The phase change memory is a novel nonvolatile data storage device, and data storage is realized by utilizing conductivity or optical characteristic difference which is shown when phase change materials are mutually converted between crystalline states and amorphous states, but the stability of the phase change memory can be influenced due to complicated thermal process in the operation process of the phase change memory unit.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a phase change memory and a method for manufacturing the same.
According to a first aspect of embodiments of the present disclosure, there is provided a phase change memory comprising:
a plurality of phase change memory cells arranged in parallel and positioned on the substrate;
an electrically insulating isolation structure located between adjacent phase change memory cells for electrically isolating adjacent phase change memory cells; wherein, the constituent material of the isolation structure comprises ceramic.
In some embodiments, the constituent materials of the isolation structure further comprise: a polymer.
In some embodiments, the ceramic is present in an amount of greater than or equal to 80% of the constituent materials of the isolation structure.
In some embodiments, the constituent materials of the isolation structure further comprise: carbon and oxides.
In some embodiments, the ceramic is present in the constituent materials of the isolation structure in a range of 10% to 80%.
In some embodiments, the phase change memory further comprises:
a plurality of first conductive lines extending along a first direction, the plurality of first conductive lines being juxtaposed in parallel with a second direction; wherein the first direction and the second direction are parallel to the plane of the substrate and are perpendicular to each other;
a plurality of second conductive lines extending in a second direction; the second conductive wires are arranged in parallel in the first direction;
the phase change memory cell is positioned between the first conductive line and the second conductive line and is perpendicular to the first conductive line and the second conductive line respectively.
In some embodiments, the isolation structure comprises:
the first sub-isolation structures extend along the direction perpendicular to the plane of the substrate and are parallel to the second direction, and are used for electrically isolating the adjacent phase change memory cells and the adjacent first conductive wires;
the plurality of second sub-isolation structures extend along the direction perpendicular to the plane of the substrate and are arranged in parallel to the first direction, and are used for electrically isolating the adjacent second conductive wires and the adjacent phase change memory cells;
wherein the constituent material of the first sub-isolation structure and/or the second sub-isolation structure comprises the ceramic.
According to a second aspect of embodiments of the present disclosure, there is provided a method of manufacturing a phase change memory, the method including:
forming a memory cell material layer on a substrate;
forming a plurality of electrically insulating isolation structures penetrating through the memory cell material layer along a direction perpendicular to a plane of the substrate so as to divide the memory cell material layer into a plurality of phase change memory cells; wherein, the constituent material of the isolation structure comprises ceramic.
In some embodiments, the forming a plurality of electrically insulating isolation structures through the memory cell material layer includes:
forming a plurality of trenches through the memory cell material layer;
and filling the component materials of the isolation structure into the groove by using sol-gel spin coating to form the isolation structure.
In some embodiments, the method further comprises:
forming a first conductive material layer on a substrate before forming a memory cell material layer;
the forming a memory cell material layer on a substrate includes: forming the memory cell material layer covering the first conductive material layer on the substrate;
the method further comprises the steps of:
forming a plurality of first sub-trenches penetrating the memory cell material layer and the first conductive material layer along a direction perpendicular to the substrate; the first sub-grooves extend along a first direction, and the plurality of first sub-grooves are arranged in parallel in a second direction; the first direction and the second direction are parallel to the plane of the substrate and are perpendicular to each other;
filling the first sub-grooves to form first sub-isolation structures; the first sub-isolation structures divide the first conductive material layer into a plurality of first conductive wires parallel to each other;
forming a second conductive material layer covering the first sub-isolation structures and the memory cell material layer;
forming a plurality of second sub-trenches penetrating the second conductive material layer and the memory cell material layer along a direction perpendicular to the substrate; the second sub-grooves extend along the second direction, and the plurality of second sub-grooves are arranged in parallel with the first direction;
filling the second sub-grooves to form second sub-isolation structures; the second sub-isolation structures divide the second conductive material layer into a plurality of second conductive wires parallel to each other; the isolation structure comprises the first sub isolation structure and the second sub isolation structure, and the constituent materials of the first sub isolation structure and/or the second sub isolation structure comprise the ceramic.
In the embodiment of the disclosure, the ceramic is added into the component material of the electrically insulating isolation structure between the adjacent phase-change memory cells, so that the conduction of current and heat between the adjacent phase-change memory cells can be well reduced, the thermal crosstalk between the adjacent memory cells is reduced, and the memory performance of the phase-change memory is improved.
Drawings
FIG. 1 is a perspective view of a phase change memory provided by an embodiment of the present disclosure;
FIG. 2 is a cross-sectional view of a phase change memory provided by an embodiment of the present disclosure;
FIG. 3 is a cross-sectional view of another side of a phase change memory provided by an embodiment of the present disclosure;
FIG. 4 is a schematic flow chart of a method for fabricating a phase change memory according to an embodiment of the disclosure;
fig. 5a to 5h are schematic views of a device structure of a phase change memory in a manufacturing process according to an embodiment of the disclosure.
Reference numerals illustrate:
10-a substrate;
20-a first conductive line; a layer of 20' -first conductive material;
30-a phase change memory cell; a 30' -memory cell material layer; 31-a first electrode; 32-a gating layer; 33-a second electrode; 34-a phase change memory layer; 35-a third electrode; 36-fourth electrode; 37-a fifth electrode;
40-a second conductive line; a 40' -second conductive material layer;
50-isolation structures; 51-a first sub-isolation structure; 52-a second sub-isolation structure;
61-a first etch mask; 62-a second etch mask;
71-a first sub-trench; 72-second sub-trenches.
Detailed Description
Exemplary implementations of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
In the related art, a phase change memory generally uses conductivity or optical property differences of phase change materials when the phase change materials are converted between crystalline and amorphous states to realize data storage, and a high phase change temperature is generated when the phase change memory cells are subjected to read-write operation, and heat generated by the phase change memory cells can generate a certain thermal crosstalk to adjacent phase change memory cells due to a thermal conduction effect. Therefore, in order to realize that each phase change memory cell can independently operate and reduce the influence of thermal crosstalk between adjacent phase change memory cells, the insulation and heat-insulating properties of the material of the isolation structure between adjacent phase change memory cells are particularly important.
Based on this, the embodiment of the disclosure provides a phase change memory. Fig. 1 is a perspective view of a phase change memory provided by an embodiment of the present disclosure, fig. 2 is a cross-sectional view of the phase change memory provided by an embodiment of the present disclosure, and fig. 3 is a cross-sectional view of another side of the phase change memory provided by an embodiment of the present disclosure.
Referring to fig. 1 to 3, the phase change memory includes:
a plurality of phase change memory cells 30 arranged in parallel on the substrate 10;
an electrically insulating isolation structure 50 between adjacent phase change memory cells 30 for electrically isolating adjacent phase change memory cells 30; wherein the constituent materials of the isolation structure 50 comprise ceramic.
Illustratively, the thermal conductivity of the ceramic added in the isolation structure 50 may be lower than 0.06W/(m.k), so that the thermal insulation function may be well performed, and it is ensured that the heat generated by each phase change memory cell 30 may act on its own phase change, so that the phase change memory cell 30 may be independently and accurately operated, and memory failure caused by thermal crosstalk between adjacent phase change memory cells 30 may be reduced, so that the state of the adjacent phase change memory cells 30 is not affected.
The ceramic may comprise at least one of aluminum silicate, aluminum oxide, silicon dioxide, magnesium oxide, or zirconium oxide.
The ceramic has a smaller particle size, and illustratively, the ceramic particle size can be nano-sized, so that the ceramic can be more uniformly mixed with other materials in the isolation structure, the mixed solvent is easier to form, and the performance is better.
Here, the substrate 10 may be a simple substance semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.
The phase change memory may store data based on heating and quenching a material of a phase change memory layer in an electrothermal manner, thereby utilizing a difference between resistivity of an amorphous phase and a crystalline phase in the material of the phase change memory layer (e.g., chalcogenide alloy).
In one embodiment, the constituent materials of the isolation structure 50 further include: a polymer.
The polymer may include at least one of polyethylene, polypropylene, ethylene, polyvinyl alcohol, or polyacrylamide.
In some embodiments, the ceramic is present in an amount greater than or equal to 80% of the constituent materials of the isolation structure 50.
In this embodiment, the polymer is used as a solvent and mixed with the ceramic to prepare a sol which is easy to spin-coat, and the ceramic content exceeds 80%, so that the thermal conductivity of the isolation structure can be reduced, and the heat insulation and insulation effects can be improved, thereby improving the storage performance of the phase change memory cell.
In one embodiment, the constituent materials of the isolation structure 50 further include: carbon and oxides.
The carbon refers to a carbon-based substance including at least one of carbon black, carbon nanotubes, or graphite.
The oxide may include at least one of aluminum oxide, magnesium oxide, calcium oxide, or silicon oxide.
In some embodiments, the ceramic content ranges from 10% to 80% in the constituent materials of the isolation structure 50.
In this embodiment, carbon and oxide are mixed with ceramic, so that the filling effect of the isolation structure can be improved and the storage performance of the phase change memory cell can be improved while the heat insulation effect is improved.
In an embodiment, the phase change memory further comprises: a plurality of first conductive lines 20 extending along a first direction, the plurality of first conductive lines 20 being juxtaposed in parallel with a second direction; wherein the first direction and the second direction are parallel to the plane of the substrate 10 and perpendicular to each other; a plurality of second conductive lines 40 extending in a second direction; a plurality of second conductive lines 40 are juxtaposed in parallel with the first direction; the phase change memory cell 30 is located between the first conductive line 20 and the second conductive line 40 and perpendicular to the first conductive line 20 and the second conductive line 40, respectively.
Here, when the first conductive line 20 is a bit line or a word line, the second conductive line 40 is a word line or a bit line. Specifically, if the first conductive line 20 is a bit line, the second conductive line 40 is a word line; if the first conductive line 20 is a word line, the second conductive line 40 is a bit line.
The material of the first conductive line 20 and the second conductive line 40 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
In one embodiment, the isolation structure 50 includes: a plurality of first sub-isolation structures 51 extending in a direction perpendicular to the plane of the substrate 10 and arranged in parallel to the second direction for electrically isolating adjacent phase change memory cells 30 and adjacent first conductive lines 20; a plurality of second sub-isolation structures 52 extending in a direction perpendicular to the plane of the substrate 10 and juxtaposed in parallel with the first direction for electrically isolating adjacent second conductive lines 40 from adjacent phase change memory cells 30; wherein the constituent material of the first sub-isolation structure 51 and/or the second sub-isolation structure 52 comprises the ceramic.
Here, the first sub-isolation structure and the second sub-isolation structure electrically isolate the adjacent first conductive wire, second conductive wire and phase change memory unit, and because the first sub-isolation structure and the second sub-isolation structure comprise ceramics, the effects of heat insulation and insulation can be improved, so that the storage performance of the phase change memory layer is improved, and the stability of the phase change memory is further improved.
In one embodiment, the phase change memory cell 30 includes a gate layer 32, a phase change memory layer 34, a first material electrode layer, and a second material electrode layer distributed along a third direction. The third direction is perpendicular to the first direction and the second direction.
In some embodiments, referring to fig. 1, the gating layer 32 is disposed on the side of the phase-change memory layer 34 facing the substrate 10 along the third direction, i.e., the gating layer 32 is closer to the substrate 10 than the phase-change memory layer 34.
In some other embodiments, the phase change memory layer is arranged on the substrate facing side of the gating layer in said third direction, i.e. the phase change memory layer is closer to the substrate than the gating layer.
In one embodiment, the material of phase change memory layer 34 includes a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material.
The material of the gating layer 32 may include any suitable Ovonic Threshold Switch (OTS) material, such as Zn x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z Etc.
Each phase change memory cell 30 stores a single bit of data and each phase change memory cell 30 may be written to or read from by varying the voltage applied to the corresponding strobe layer 32. Each phase change memory cell 30 may be individually accessed by a current applied through a top conductor and a bottom conductor (e.g., respective first conductive line 20 and second conductive line 40) in contact with each phase change memory cell 30.
Here, when the first conductive line 20 is a top conductor or a bottom conductor, the second conductive line 40 is a bottom conductor or a top conductor. Specifically, if the first conductive line 20 is a top conductor, the second conductive line 40 is a bottom conductor; if the first conductive line 20 is a bottom conductor, the second conductive line 40 is a top conductor.
In one embodiment, the first material electrode layer includes: a first electrode 31, a second electrode 33, and a third electrode 35.
Materials for the first electrode material layer include, but are not limited to: amorphous carbon, graphene, graphite, carbon nanotubes, or other similar carbon-based materials.
Referring to fig. 1, in an embodiment in which the gate layer 32 is closer to the substrate 10 than the phase-change memory layer 34, the first electrode 31 is located between the first conductive line 20 and the gate layer 32, the second electrode 33 is located between the gate layer 32 and the phase-change memory layer 34, and the third electrode 35 is located between the phase-change memory layer 34 and the second conductive line 40.
In an embodiment in which the phase change memory layer is closer to the substrate than the gate layer, the first electrode is located between the first conductive line and the phase change memory layer, the second electrode is located between the phase change memory layer and the gate layer, and the third electrode is located between the gate layer and the second conductive line.
In one embodiment, the second material electrode layer includes: a fourth electrode 36 and a fifth electrode 37.
The material of the second material electrode layer includes, but is not limited to W, W 2 N, co, cu, al, carbon, polysilicon, doped silicon, silicide, or any combination thereof.
When a second material electrode layer is disposed on the phase change memory layer 34 side facing the first conductive line 20 in the third direction, the second material electrode layer may refer to the fourth electrode 36 in the drawing; when the second material electrode layer is disposed on the side of the phase change memory layer 34 facing the second conductive line 40 in the third direction, the second material electrode layer may refer to the fifth electrode 37 in the drawing.
The embodiment of the disclosure also provides a method for preparing the phase change memory, referring to fig. 4, as shown in the figure, the method comprises the following steps:
step 401: forming a memory cell material layer on a substrate;
step 402: forming a plurality of electrically insulating isolation structures penetrating through the memory cell material layer along a direction perpendicular to a plane of the substrate so as to divide the memory cell material layer into a plurality of phase change memory cells; wherein, the constituent material of the isolation structure comprises ceramic.
The method for manufacturing the phase change memory according to the embodiments of the present disclosure is described in further detail below with reference to specific embodiments.
Fig. 5a to 5h are schematic views of a device structure of a phase change memory in a manufacturing process according to an embodiment of the disclosure.
First, as shown in fig. 5a, step 401 is performed to form a memory cell material layer 30' on a substrate 10.
The first conductive material layer 20 'may be formed on the substrate 10 before the memory cell material layer 30' is formed. The material of the first conductive material layer 20' includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
Note that forming the memory cell material layer 30' on the substrate 10 includes: on the substrate 10, a memory cell material layer 30 'is formed to cover the first conductive material layer 20'.
Here, the substrate 10 may be a simple substance semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.
In an embodiment, first conductive material layer 20 'and memory cell material layer 30' are deposited using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof.
Referring next to fig. 5b to 5h, step 402 is performed to form a plurality of electrically insulating isolation structures 50 extending through the memory cell material layer 30 'in a direction perpendicular to the plane of the substrate 10 to divide the memory cell material layer 30' into a plurality of phase change memory cells 30; wherein the constituent materials of the isolation structure 50 comprise ceramic.
By adding ceramic into the component materials of the isolation structure, the insulation and heat insulation performance of the ceramic material is good, so that the conduction of current and heat between adjacent phase-change memory units can be well reduced, the thermal crosstalk between the adjacent memory units is reduced, and the memory performance of the phase-change memory is improved.
In one embodiment, the forming of the plurality of electrically insulating isolation structures 50 through the memory cell material layer 30' includes: forming a plurality of trenches penetrating the memory cell material layer 30'; the trench is filled with constituent materials of the isolation structure 50 using sol-gel spin coating to form the isolation structure 50.
Next, further detailed description will be made.
First, as shown in fig. 5b, the first conductive material layer 20' and the memory cell material layer 30' on the first conductive material layer 20' are patterned in the extending direction (first direction) of the first conductive line 20 to form a first etch mask 61 extending along the first direction. The first etch mask 61 may be patterned through a photolithography process. The first etch mask 61 may be a photoresist mask or a hard mask patterned based on a photolithography mask; when the first etching mask 61 may be a photoresist mask, the first etching mask 61 is patterned specifically by steps of exposure, development, photoresist removal, and the like.
As shown in fig. 5c, the memory cell material layer 30 'and the first conductive material layer 20' are etched in a direction perpendicular to the substrate 10, forming a plurality of first sub-trenches 71 penetrating the memory cell material layer 30 'and the first conductive material layer 20'; the first sub-grooves 71 extend along a first direction, and the plurality of first sub-grooves 71 are arranged in parallel with the second direction; the first direction and the second direction are parallel to the plane of the substrate 10 and perpendicular to each other.
Next, as shown in fig. 5d, the first sub-trench 71 is filled to form a first sub-isolation structure 51; the first sub-isolation structures 51 divide the first conductive material layer 20' into a plurality of first conductive lines 20 parallel to each other.
Note that, the filling the first sub-trench 71 specifically includes: the first sub-trench 71 is filled with constituent materials of the first sub-isolation structure 51 using a sol-gel spin coating method to form the first sub-isolation structure 51.
Next, as shown in fig. 5e, a second conductive material layer 40 'is formed to cover the first sub-isolation structures 51 and the memory cell material layer 30'.
The material of the second conductive material layer 40' includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
In an embodiment, the second conductive material layer 40' is deposited using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof.
As shown in fig. 5f, the second conductive material layer 40' is patterned in the extending direction (second direction) of the second conductive line 40 to form a second etch mask 62 extending along the second direction. The second etch mask 62 may be patterned by a photolithography process. The second etch mask 62 may be a photoresist mask or a hard mask patterned based on a photolithographic mask; when the second etch mask 62 may be a photoresist mask, the second etch mask 62 is patterned, in particular, by exposing, developing, photoresist stripping, and the like.
Next, as shown in fig. 5g, the memory cell material layer 30 'and the second conductive material layer 40' are etched in a direction perpendicular to the substrate 10, forming a plurality of second sub-trenches 72 penetrating the second conductive material layer 40 'and the memory cell material layer 30'; the second sub-grooves 72 extend along the second direction, and the plurality of second sub-grooves 72 are arranged in parallel to the first direction.
Here, etching is stopped at the first conductive line 20, so that the first conductive line 20 remains intact.
As shown in fig. 5h, the second sub-trench 72 is filled to form the second sub-isolation structure 52; the second sub-isolation structures 52 divide the second conductive material layer 40' into a plurality of second conductive lines 40 parallel to each other.
The isolation structure 50 includes a first sub-isolation structure 51 and a second sub-isolation structure 52, and constituent materials of the first sub-isolation structure 51 and/or the second sub-isolation structure 52 include the ceramic.
Note that, the filling the second sub-trench 72 specifically includes: the second sub-trenches 72 are filled with constituent materials of the second sub-isolation structures 52 using sol-gel spin coating to form the second sub-isolation structures 52.
In this way, the preparation of the phase change memory is substantially completed. Some interconnect processes may also be involved in the following and will not be discussed further herein.
It should be noted that, the phase change memory provided by the embodiments of the present disclosure and the method for manufacturing the phase change memory belong to the same concept; the technical features in the technical solutions described in the embodiments may be arbitrarily combined without any conflict, and are not described herein.
The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the scope of the present disclosure, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the present disclosure.
Claims (7)
1. A phase change memory, comprising:
a plurality of phase change memory cells arranged in parallel and positioned on the substrate;
a plurality of first conductive lines extending in a first direction; the first conductive wires are parallel to the second direction; wherein the first direction and the second direction are parallel to the plane of the substrate and are perpendicular to each other;
a plurality of second conductive lines extending in a second direction; the second conductive wires are arranged in parallel in the first direction; the phase change memory cell is positioned between the first conductive wire and the second conductive wire and is perpendicular to the first conductive wire and the second conductive wire respectively;
an electrically insulating isolation structure located between adjacent phase change memory cells for electrically isolating adjacent phase change memory cells; wherein, the constituent materials of the isolation structure comprise ceramics;
the isolation structure includes: the first sub-isolation structures extend along the direction perpendicular to the plane of the substrate and are parallel to the second direction, and are used for electrically isolating the adjacent phase change memory cells and the adjacent first conductive wires;
and the plurality of second sub-isolation structures extend along the direction perpendicular to the plane of the substrate and are arranged in parallel to the first direction, and are used for electrically isolating the adjacent second conductive wires and the adjacent phase change memory cells.
2. The phase change memory of claim 1, wherein,
the constituent materials of the isolation structure further comprise: a polymer.
3. The phase change memory of claim 2, wherein,
in the constituent material of the isolation structure, the content of the ceramic is 80% or more.
4. The phase change memory according to claim 1 or 2, wherein,
the constituent materials of the isolation structure further comprise: carbon and oxides.
5. The phase change memory of claim 4, wherein,
the content of the ceramic in the constituent material of the isolation structure is in the range of 10% to 80%.
6. A method of fabricating a phase change memory, the method comprising:
forming a first conductive material layer on a substrate;
forming a memory cell material layer covering the first conductive material layer on the substrate;
forming a plurality of electrically insulating isolation structures penetrating through the memory cell material layer along a direction perpendicular to a plane of the substrate so as to divide the memory cell material layer into a plurality of phase change memory cells; wherein, the constituent materials of the isolation structure comprise ceramics;
the forming a plurality of electrically insulating isolation structures through the memory cell material layer, comprising:
forming a plurality of first sub-trenches penetrating the memory cell material layer and the first conductive material layer along a direction perpendicular to the substrate; the first sub-grooves extend along a first direction, and the plurality of first sub-grooves are arranged in parallel in a second direction; the first direction and the second direction are parallel to the plane of the substrate and are perpendicular to each other;
filling the first sub-grooves to form first sub-isolation structures; the first sub-isolation structures divide the first conductive material layer into a plurality of first conductive wires parallel to each other;
forming a second conductive material layer covering the first sub-isolation structures and the memory cell material layer;
forming a plurality of second sub-trenches penetrating the second conductive material layer and the memory cell material layer along a direction perpendicular to the substrate; the second sub-grooves extend along the second direction, and the plurality of second sub-grooves are arranged in parallel with the first direction;
filling the second sub-grooves to form second sub-isolation structures; the second sub-isolation structures divide the second conductive material layer into a plurality of second conductive wires parallel to each other; the isolation structure includes the first sub-isolation structure and the second sub-isolation structure.
7. The method of fabricating a phase change memory according to claim 6, wherein forming a plurality of electrically insulating isolation structures through the memory cell material layer comprises:
forming a plurality of trenches through the memory cell material layer;
and filling the component materials of the isolation structure into the groove by using sol-gel spin coating to form the isolation structure.
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| US10374103B1 (en) * | 2018-03-28 | 2019-08-06 | International Business Machines Corporation | Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays |
| US10833269B1 (en) * | 2019-05-07 | 2020-11-10 | International Business Machines Corporation | 3D phase change memory |
| US10872835B1 (en) * | 2019-07-03 | 2020-12-22 | Micron Technology, Inc. | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same |
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| US7709289B2 (en) * | 2005-04-22 | 2010-05-04 | Micron Technology, Inc. | Memory elements having patterned electrodes and method of forming the same |
| US7696503B2 (en) * | 2005-06-17 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
| US20080090400A1 (en) * | 2006-10-17 | 2008-04-17 | Cheek Roger W | Self-aligned in-contact phase change memory device |
| US20180190715A1 (en) * | 2016-04-16 | 2018-07-05 | Chengdu Haicun Ip Technology Llc | Three-Dimensional Vertical Multiple-Time-Programmable Memory with A Thin Memory Layer |
| US10600844B2 (en) * | 2018-09-28 | 2020-03-24 | Intel Corporation | Memory structures having reduced via resistance |
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| US10374103B1 (en) * | 2018-03-28 | 2019-08-06 | International Business Machines Corporation | Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays |
| US10833269B1 (en) * | 2019-05-07 | 2020-11-10 | International Business Machines Corporation | 3D phase change memory |
| US10872835B1 (en) * | 2019-07-03 | 2020-12-22 | Micron Technology, Inc. | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same |
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