CN113161383B - Three-dimensional phase change memory and preparation method thereof - Google Patents
Three-dimensional phase change memory and preparation method thereof Download PDFInfo
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- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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Abstract
The invention discloses a three-dimensional phase change memory and a preparation method thereof, wherein the three-dimensional phase change memory comprises: a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, and a phase change memory element disposed at an intersection of the first conductive line and the second conductive line in a third direction; the third direction is perpendicular to the first direction and the second direction; the phase change memory assembly includes: phase change memory cell and definite value resistance unit, wherein, phase change memory cell includes: sequentially stacking a gating element and a phase change memory element distributed between the first conductive line and the second conductive line along a third direction, wherein the phase change memory element is used for storing data by phase change based on a voltage difference between the first conductive line and the second conductive line, and the gating element is used for controlling conductive connection between the phase change memory element and the first conductive line and the second conductive line; the constant value resistance unit is connected in parallel with the phase change memory element.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a three-dimensional phase change memory applied to deep neural network calculation and a preparation method thereof.
Background
An artificial intelligence neural network is a nonlinear, adaptive information processing system composed of a large number of interconnected processing units. Currently, deep neural networks mostly operate on von neumann architectures. In the von neumann architecture, the computing unit is separated from the storage unit, data in the information processing process is transmitted back and forth between the storage unit and the computing unit, and after the memory capacity is exponentially increased, the data transmission bandwidth between the CPU and the memory becomes a bottleneck. Therefore, a non-von neumann architecture based on Phase Change Memory (PCM) has been developed.
Non-von Neumann architectures do not separate the storage and computation processes and therefore consume less power. The phase-change memory stores data by utilizing the conductivity difference of the phase-change material when the crystalline state and the amorphous state are mutually converted, and has the advantages of high storage speed and high reliability. With the increasing demand of deep neural network technology for integration and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the requirements, which makes a three-dimensional (3D) memory capable of being vertically stacked in a three-dimensional space an important research direction in the field.
Disclosure of Invention
Accordingly, embodiments of the present invention are directed to a three-dimensional phase change memory device that solves at least one of the problems set forth in the background art.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
in the above scheme, the phase change memory element is shaped as a rectangular pillar, and the sidewalls of the rectangular pillar extend in the third direction, the sidewalls include a first group of sidewalls perpendicular to the second direction and a second group of sidewalls perpendicular to the first direction, and the constant value resistance unit includes a first group of constant value resistance elements located outside the first group of sidewalls and a second group of constant value resistance elements located outside the second group of sidewalls.
In the above solution, the upper surface of the first set of constant value resistance elements is in contact with the lower surface of the second conductive line, the second set of constant value resistance elements includes a connection portion extending to the sidewall of the second conductive line, and the second set of constant value resistance elements is in contact with the sidewall of the second conductive line through the connection portion.
In the above scheme, the material of the resistance unit with constant value includes metal nitride.
In the above solution, the metal nitride includes one or more of titanium nitride, tungsten nitride, or tantalum nitride.
In the above scheme, the thickness of the constant value resistance unit in the direction perpendicular to the plane where the side wall is located is 1-10nm.
In the above scheme, the method further comprises: a pad layer, the pad layer including a first set of pad elements located between the first set of sidewalls and the first set of constant value resistance elements and a second set of pad elements located between the second set of sidewalls and the second set of constant value resistance elements, the positions of the upper surfaces of the second set of pad elements being lower than the positions of the upper surfaces of the second conductive lines and not lower than the positions of the upper surfaces of the phase change memory elements.
The embodiment of the invention also provides a preparation method of the three-dimensional phase change memory, which comprises the following steps:
forming a first conductive line extending in a first direction;
forming a phase change memory component, wherein the phase change memory component comprises a phase change memory unit and a constant value resistance unit, and the phase change memory unit comprises a gating element and a phase change memory element which are distributed in a stacking mode in the third direction;
forming a second conductive line extending in a second direction; wherein,
the phase change memory element is for storing data by phase changing based on a voltage difference between the first and second conductive lines; the gating element is used for controlling conductive connection between the phase change storage layer and the first conductive line and the second conductive line; the constant value resistance unit and the phase change memory element are connected in parallel between the second conductive line and the gating element.
In the above solution, the forming a phase change memory device includes:
forming the phase change memory element and a first set of constant value resistive elements, the phase change memory element being in the shape of a rectangular pillar with sidewalls of the rectangular pillar extending in the third direction, the sidewalls including a first set of sidewalls perpendicular to the second direction and a second set of sidewalls perpendicular to the first direction, the first set of constant value resistive elements being located outside the first set of sidewalls;
forming a second set of fixed value resistive elements, the second set of fixed value resistive elements being located outside the second set of sidewalls, the first set of fixed value resistive elements and the second set of fixed value resistive elements constituting the fixed value resistive elements;
forming gating elements, wherein the gating elements and the phase change storage elements are distributed in a stacking mode in the third direction.
In the above scheme, the material of the resistance unit with constant value includes metal nitride.
In the above solution, the metal nitride includes one or more of titanium nitride, tungsten nitride, or tantalum nitride.
In the above scheme, the thickness of the constant value resistance unit along the direction perpendicular to the plane of the side wall of the rectangular column is 1-10nm.
In the above scheme, the method further comprises:
forming a pad layer, wherein the pad layer includes a first set of pad elements located between the first set of sidewalls and the first set of constant value resistance elements and a second set of pad elements located between the second set of sidewalls and the second set of constant value resistance elements, and positions of upper surfaces of the second set of pad elements are lower than positions of upper surfaces of the second conductive lines and not lower than positions of upper surfaces of the phase change memory layers.
The three-dimensional phase change memory provided by the embodiment of the invention comprises: a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, and a phase change memory component disposed in a third direction at an intersection of the first and second conductive lines; the third direction is perpendicular to the first direction and the second direction; the phase change memory component comprises a phase change memory unit and a constant value resistance unit, wherein the phase change memory unit comprises a gating element and a phase change memory element which are distributed in a stacking mode in the third direction, the phase change memory element is used for storing data through phase change based on voltage difference between the first conducting line and the second conducting line, and the gating element is used for controlling conductive connection between the phase change memory element and the first conducting line and the second conducting line; wherein the constant value resistance unit and the phase change memory element are connected in parallel between the second conductive line and the gating element.
Therefore, by adopting the three-dimensional phase change memory structure, low interference signal sensitivity, higher read-write speed and higher storage density can be realized, so that higher-level artificial intelligent neural network calculation is carried; in addition, by adopting the three-dimensional phase change memory structure, the gating element can simultaneously control the phase change memory element and the constant value resistance unit, the constant value resistance unit does not need additional control, and the complex device structure and operation process are avoided.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic structural diagram of a three-dimensional phase change memory according to an embodiment of the invention;
FIGS. 2A-2B are vertical cross-sectional views of a three-dimensional phase change memory according to an embodiment of the present invention along XX 'and YY', respectively;
FIG. 3 is a schematic diagram of a horizontal cross-sectional structure of a three-dimensional phase change memory along ZZ' according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of a method for manufacturing a three-dimensional phase change memory according to an embodiment of the invention;
fig. 5 is a schematic diagram illustrating a specific process flow of a part of steps in a method for manufacturing a three-dimensional phase change memory according to an embodiment of the present invention;
FIG. 6 is a schematic flow chart illustrating a method for fabricating a three-dimensional phase change memory according to another embodiment of the present invention;
FIGS. 7A to 7N are schematic structural diagrams of process links in the method for manufacturing the three-dimensional phase change memory corresponding to FIG. 6;
FIGS. 8A-8D are schematic diagrams illustrating a specific process for forming a first set of pre-layers of pad elements and a first set of pre-layers of constant value resistors;
FIGS. 9A-9B are schematic views illustrating a specific process for forming a pre-layer of a first set of sidewall elements;
FIGS. 10A-10E are schematic diagrams illustrating a specific process for forming a second set of pad elements and a second set of constant value resistor elements;
FIGS. 11A-11B are schematic views illustrating a detailed process for forming a second set of sidewall elements;
fig. 12 is a schematic diagram illustrating an overall architecture of a three-dimensional phase change memory according to an embodiment of the invention.
Part names corresponding to the respective reference numerals:
100 three-dimensional phase change memory, 101 first conductive lines, 102 second conductive lines, 130 phase change memory components, 131 phase change memory cells, 110 gating elements, 120 phase change memory elements, 132 constant value resistance cells, 160 liner layers, 170 sidewall layers, 191 first fill layers, 192 second fill layers.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" \8230; \8230 ";," - \8230;, "\8230"; "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," 8230; \8230 ";," "directly adjacent," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "at 8230," "below," "at 8230," "below," "at 8230," "above," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230; \8230; below" and "at 8230; \8230; below" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As used in the following description, the term "three-dimensional memory" refers to a semiconductor device having the following memory cells: the memory cells are arranged vertically on a laterally oriented substrate such that the number of memory cells increases in the vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.
The artificial intelligence neural network calculation needs to be accurately and quickly calculated aiming at ultra-large data quantity, and is sensitive to interference signal abnormity. The low-frequency interference signals, the resistance fluctuation and the like of the three-dimensional phase change memory below the working frequency of 10E4 Hz limit the application of the three-dimensional phase change memory in artificial intelligence neural network calculation.
An embodiment of the invention provides a three-dimensional phase change memory 100, and fig. 1 is a schematic structural diagram of the three-dimensional phase change memory 100 according to the embodiment of the invention. As shown in fig. 1, the three-dimensional phase change memory 100 includes: a first conductive line 101 extending in a first direction, a second conductive line 102 extending in a second direction intersecting the first direction, and a phase change memory component 130 disposed at an intersection of the first conductive line and the second conductive line in a third direction; the third direction is perpendicular to the first direction and the second direction; the phase change memory component 130 includes a phase change memory cell 131 and a fixed resistance cell 132, the phase change memory cell 131 includes a gating element 110 and a phase change memory element 120 stacked in the third direction, the phase change memory element 120 is configured to store data by performing a phase change based on a voltage difference between the first conductive line 101 and the second conductive line 102, the gating element 110 is configured to control an electrically conductive connection between the phase change memory element 120 and the first conductive line 101 and the second conductive line 102; wherein the constant value resistance unit 132 is connected in parallel with the phase change memory element 120 between the second conductive line 102 and the gating element 110.
In some embodiments, as shown in fig. 1, the phase change memory element 120 includes a phase change memory layer 121, and the phase change memory layer 121 may be heated and quenched to switch between a crystalline phase and an amorphous phase, so as to realize two memory states, i.e., 0 and 1, by using the difference between the resistivities of the amorphous phase and the crystalline phase. The gate element 110 includes a gate layer 112, the gate layer 112 and the phase change memory layer 121 are connected in series in a third direction, and the gate layer 112 is used to control conductive connection between the phase change memory layer 121 and the first and second conductive lines 101 and 102.
The resistance value of the constant value resistance unit 132 is constant during the storage of the three-dimensional memory. In a read operation, a constant value resistance unit 132 connected in parallel across the phase change memory element 120 provides an alternative conductive path to the phase change memory layer in the amorphous state. The influence of resistance fluctuation, low-frequency interference signals and the like of the phase change storage layer on the reading operation can be weakened through the setting, and the calculation requirement of the artificial intelligent neural network is further met.
In some embodiments, as shown in fig. 1, the phase change memory element 120 includes a phase change memory layer 121 and an upper electrode 122 stacked along a third direction, the upper electrode 122 is located between the phase change memory layer 121 and the second conductive line 102, and the upper electrode 122 is used to electrically connect the phase change memory layer 121 and the second conductive line 102. In some embodiments, as shown in fig. 1, the gate element 110 includes a lower electrode 111, a gate layer 112 and an intermediate electrode 113 stacked and distributed along a third direction, and the lower electrode 111 and the intermediate electrode 113 are respectively used for electrically connecting the gate layer 112 and the first conductive line 101 and the gate layer 112 and the phase change storage layer 121.
In practical operation, the material of the phase-change memory layer 121 may be a chalcogenide compound, such as a germanium-antimony-tellurium (Ge-Sb-Te, GST) material or an indium-antimony-tellurium (In-Sb-Te, IST) material, and the like, and specifically, the material of the phase-change memory layer may be Ge, for example 2 Sb 2 Te 5 、Ge 1 Sb 4 Te 7 、In 2 Sb 2 Te 5 Or In 1 Sb 2 Te 4 And so on. The material of the gate layer 112 may be a chalcogenide material, and for example, the material of the gate layer may be Ge-Se, si-Te, C-Te, B-Te, ge-Te, al-Te, ge-Sb-Te, ge-Sb, bi-Te, as-Te, sn-Te, ge-Te-Pb, or Ge-Se-Te, and the like. Each of the upper, middle, and lower electrodes may comprise a conductive material including, but not limited to, W, co, cu, al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the upper, middle, and lower electrodes comprises carbon, such as amorphous carbon (a-C), carbon nanotubes, and the like.
In the above embodiments, the gating elements and the phase change memory elements are stacked in series in the third direction according to the order of the gating elements and the phase change memory elements, it should be understood that the above series manner is only an example of one possible implementation manner, and actually, the gating elements and the phase change memory elements may also be stacked in series in the third direction according to the order of the phase change memory elements and the gating elements.
Fig. 2A and fig. 2B are schematic diagrams of vertical cross-sectional structures of the three-dimensional phase change memory along X-X 'and along Y-Y', respectively (the first filling layer 191 is not shown), and the structure of the three-dimensional phase change memory 100 according to the embodiment of the invention is further described with reference to fig. 2A and fig. 2B. As shown in fig. 2A-2B, the phase change memory element 120 is shaped as a rectangular pillar and the sidewalls of the rectangular pillar extend along the third direction, the sidewalls of the rectangular pillar include a first set of sidewalls 151 (shown in fig. 2A) perpendicular to the second direction and a second set of sidewalls 152 (shown in fig. 2B) perpendicular to the first direction, and the constant value resistance unit 132 includes a first set of constant value resistance elements 132-1 (shown in fig. 2A) located outside the first set of sidewalls 151 and a second set of constant value resistance elements 132-2 (shown in fig. 2B) located outside the second set of sidewalls 152.
In some embodiments, as shown in fig. 2A, an upper surface of the first set of constant value resistive elements 132-1 is in contact with a lower surface of the second conductive line 102, as shown in fig. 2B, the second set of constant value resistive elements 132-2 includes a connection CT extending to a sidewall of the second conductive line 102, and the second set of constant value resistive elements 132-2 is in contact with the sidewall of the second conductive line 102 through the connection CT.
In some embodiments, the material of the constant value resistance unit 132 includes a metal nitride, and in some specific embodiments, the material of the first set of constant value resistance elements 132-1 and/or the second set of constant value resistance elements 132-2 includes a metal nitride. In practical operation, the material of the resistance-fixed unit 132 includes one or more of titanium nitride, tungsten nitride, or tantalum nitride.
In practical operation, if the ratio of the resistance values of the constant value resistance unit and the phase change memory element is too large, the capability of weakening the fluctuation of the resistance value of the phase change memory element and low-frequency interference signals is difficult to meet the requirement of artificial intelligence application, and if the ratio of the constant value resistance unit is too small, the normal memory function is affected, and even the memory function is failed.
The thickness of the constant value resistance unit 132 in the direction perpendicular to the plane of the sidewall of the phase change memory element 120 and the width of the phase change memory element 120 directly affect the magnitude of the parallel equivalent resistance of the phase change memory element 120 and the constant value resistance unit 132. In a preferred embodiment, the phase change memory element 120 is formed by a 20nm line width mask etching, that is, the constant value resistance unit 132 is a rectangular column with a width of 20nm × 20nm, and the thickness of the constant value resistance unit 132 along a direction perpendicular to a plane where sidewalls of the phase change memory element 120 are located is 1-10nm. In a more preferred embodiment, the constant value resistance unit 132 has a thickness of 2-5nm in a direction perpendicular to the plane of the sidewalls of the phase change memory element 120.
In some embodiments, as shown in fig. 1, 2A-2B, the three-dimensional phase change memory 100 further comprises: a pad layer 160, the pad layer 160 comprising a first set of pad elements 160-1 located between the first set of sidewalls 151 and the first set of constant value resistive elements 132-1 and a second set of pad elements 160-2 located between the second set of sidewalls 152 and the second set of constant value resistive elements 132-2, an upper surface of the second set of pad elements 160-2 being located lower than an upper surface of the second conductive line 102 and lower than an upper surface of the phase change memory element 120. In some embodiments, as shown in FIG. 2A, the upper surface of the first set of pad elements 160-1 is flush with the upper surface of the first set of fixed value resistive elements 132-1.
The liner layer 160 is used to electrically isolate the phase change memory element 120 from the fixed value resistance unit 132. Here, the material of the pad layer 160 includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, a polymer material, or the like. In one embodiment, the liner layer comprises a double layer structure (not shown) of silicon dioxide layer/silicon nitride layer (SiO 2/SiN), wherein the silicon dioxide layer is located between the silicon nitride layer and the phase change memory element 120.
In some embodiments, as shown in fig. 1, 2A-2B, the three-dimensional phase change memory 100 further comprises: and the side wall layer 170, wherein the side wall layer 170 comprises a first group of side wall elements 170-1 and a second group of side wall elements 170-2. The first set of sidewall elements 170-1 are located outside the first set of sidewalls 151, and cover sidewalls of the first set of constant resistance elements 132-1 and sidewalls of the gating element 110 perpendicular to the second direction; the second group of sidewall elements 170-2 is located outside the second group of sidewalls 152, and covers the sidewalls of the second group of constant value resistance elements 132-2 and the sidewalls of the gating element 110 perpendicular to the first direction.
The sidewall layer 170 is used to protect the gating element 110 and the resistance unit 132 with a constant value, and avoid the problems of poor device stability and failure caused by material contamination and component damage. In one embodiment, the sidewall layer 170 includes a silicon oxide layer/silicon nitride layer (SiO 2/SiN) double-layer structure (not shown), wherein the silicon oxide layer is disposed between the silicon nitride layer and the first set of constant-value resistor elements 132-1 and the gate element 110.
In some specific embodiments, as shown in fig. 2A-2B, the upper electrode 122 includes a first sub-upper electrode 122-1 and a second sub-upper electrode 122-2 stacked and distributed along a third direction, wherein the material of the first sub-upper electrode 122-1 includes a metal material, and the material of the second sub-upper electrode 122-2 includes a carbon-containing material; the intermediate electrode 113 includes a first sub-intermediate electrode 113-1 and a second sub-intermediate electrode 113-2 stacked and distributed along a third direction, wherein the material of the first sub-intermediate electrode 113-1 includes a carbon-containing material, and the material of the second sub-intermediate electrode 113-2 includes a metal material.
In practical operation, the metal material includes, but is not limited to, tungsten, the carbon-containing material includes, but is not limited to, amorphous carbon, carbon nanotubes, graphene, etc., and for example, in some specific embodiments, the material of the second sub-upper electrode and the first sub-middle electrode is amorphous carbon, and the material of the first sub-upper electrode and the second sub-middle electrode is tungsten. Through the arrangement of the double-layer electrode, on one hand, the second sub upper electrode and the first sub intermediate electrode which comprise the carbon-containing material can seal heat near the phase change memory layer as much as possible, and thermal diffusion and thermal crosstalk brought correspondingly are reduced, and on the other hand, the arrangement of the first sub upper electrode and the second sub intermediate electrode which comprise the metal material can prevent impurities in the second sub upper electrode and the first sub intermediate electrode from diffusing into the phase change memory layer to cause deterioration of device performance.
FIG. 3 is a horizontal cross-sectional view along ZZ' of the three-dimensional phase-change memory 100 according to the embodiment of the present invention (the first filling layer 191 is not shown). As shown in FIG. 3, the second set of constant value resistive elements 132-2 covers a first set of sidewalls 151 of a plurality of phase change memory elements 120 connected to the same second conductive line 102, and the first constant value resistive element 132-1 covers a second set of sidewalls 152 of a single one of the phase change memory elements 120.
Specifically, the second set of constant value resistive elements 132-2 includes two opposing resistive walls extending along the second direction, and the first set of constant value resistive elements 132-1 is located between the two resistive walls of the second set of constant value resistive elements 132-2.
Accordingly, the second set of spacer elements 160-2 includes two opposing spacer walls extending along the second direction, the second set of spacer elements 160-2 covers the second set of sidewalls 152 of the plurality of phase change memory elements 120 connected to the same second conductive line 102, and the first set of spacer elements 160-1 is located between the two spacer walls of the second set of spacer elements 160-2. The second group of side wall elements 170-2 includes two side wall walls that are opposite to each other and extend in the second direction, and the first group of side wall elements 170-1 is located between the two side wall walls.
The embodiment of the invention also provides a preparation method of the three-dimensional phase change memory, and fig. 4 is a schematic flow chart of the preparation method of the three-dimensional phase change memory provided by the embodiment of the invention. As shown in fig. 4, the method includes:
step S401, forming a first conductive line extending along a first direction;
step S402, forming a phase change storage component, wherein the phase change storage component comprises a phase change storage unit and a constant value resistance unit, and the phase change storage unit comprises a gating element and a phase change storage element which are stacked and distributed in the third direction;
step S403, forming a second conductive line extending along a second direction; wherein the phase change memory element is to store data based on a phase change occurring in a voltage difference between the first and second conductive lines; the gating element is to control a conductive connection between the phase change memory element and the first and second conductive lines; the constant value resistance unit and the phase change memory element are connected in parallel between the second conductive line and the gating element.
In some embodiments, as shown in fig. 5, the forming a phase change memory component includes:
step S501, forming a phase change memory element and a first set of resistance constant values, where the phase change memory element is a rectangular pillar and sidewalls of the rectangular pillar extend along the third direction, the sidewalls include a first set of sidewalls perpendicular to the second direction and a second set of sidewalls perpendicular to the first direction, and the first set of resistance constant values is located outside the first set of sidewalls;
step S502, forming a second set of constant value resistance elements, where the second set of constant value resistance elements are located outside the second set of sidewalls, and the first set of constant value resistance elements and the second set of constant value resistance elements constitute the constant value resistance unit;
and S503, forming gating elements, wherein the gating elements and the phase change storage elements are distributed in a stacking mode in the third direction.
It should be understood that the operations illustrated in the methods provided by embodiments of the present invention are not exclusive and that other operations may be performed before, after, or between any of the illustrated operations. Further, some of the operations may be performed concurrently or may be performed in a different order than shown in fig. 4, 5.
For example, in some embodiments, the second conductive line and the phase change memory element and the first set of fixed value resistive elements in the phase change memory component may be formed simultaneously in the same step, the specific process flow of which is shown in fig. 6:
step S601, forming a first conductive line extending along a first direction;
step S602, forming a second conductive line extending along a second direction orthogonal to the first direction, a phase change memory element having a rectangular pillar shape with sidewalls extending along a third direction, the sidewalls including a first set of sidewalls perpendicular to the second direction and a second set of sidewalls perpendicular to the first direction, and a first set of constant-value resistive elements outside the first set of sidewalls;
step S603, forming a second set of constant value resistance elements, where the second set of constant value resistance elements are located outside the second set of sidewalls, and the first set of constant value resistance elements and the second set of constant value resistance elements constitute the constant value resistance unit;
step S604, forming a gating element, wherein the gating element and the phase change storage element are distributed in a stacking manner in the third direction; wherein the constant value resistance unit and the phase change memory element are connected in parallel between the second conductive line and the gating element.
In the above embodiment, the second conductive line is formed simultaneously with the phase change memory element and the first set of resistance elements in the same step, which saves a mask required for forming the second conductive line separately compared to an implementation in which the second conductive line is formed in a separate step. The following will specifically describe the corresponding manufacturing method and related technical effects of fig. 6 with reference to schematic structural diagrams of the three-dimensional phase change memory at various process flow stages shown in fig. 7A to 7L.
First, the method starts at step S601, and as shown in fig. 7A-7D, first conductive lines 101 extending in a first direction are formed.
In an actual process, a substrate Sub may be provided first, and the substrate Sub is located below a process execution surface, so as to provide a supporting function for the process. Here, the substrate includes a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In some embodiments, the substrate Sub includes a semiconductor base and a dielectric layer on the semiconductor base, wherein the dielectric layer includes one or more of silicon dioxide, silicon nitride, TEOS, and the like.
Then, a first conductive line material layer 101', a gate element material layer 110', a phase change memory element material layer 120', and a protective layer material layer 180' are formed on the substrate Sub. In some embodiments, the forming of the gate element material layer 110' includes forming a lower electrode material layer 111', a gate layer material layer 112', and an upper electrode material layer 122' stacked and distributed along the third direction, and the forming of the phase change memory element material layer 120' includes forming a phase change memory layer material layer 121' and an upper electrode material layer 122' stacked and distributed along the third direction. Here, the material of the first conductive line material layer 101' may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The material of the phase-change memory layer 121' includes a chalcogenide compound, which may be, for example, a germanium-antimony-tellurium (Ge-Sb-Te, GST) material or an indium-antimony-tellurium (In-Sb-Te, IST) material, etc., and particularly, for example, a phase-change memoryThe material of the reservoir material layer may be Ge 2 Sb 2 Te 5 、Ge 1 Sb 4 Te 7 、In 2 Sb 2 Te 5 Or In 1 Sb 2 Te 4 And so on. The material of the gate layer material layer may include chalcogenide materials, and for example, the material of the gate layer material layer may be Ge-Se, si-Te, C-Te, B-Te, ge-Te, al-Te, ge-Sb, bi-Te, as-Te, sn-Te, ge-Te-Pb, ge-Se-Te, or the like. The material of the upper electrode material layer, the middle electrode material layer and the lower electrode material layer includes a carbon-containing material, including but not limited to amorphous carbon, carbon nanotube or graphene, etc., and in one embodiment, the carbon-containing material is amorphous carbon, for example. The material of the passivation layer 180' includes a dielectric material, such as silicon nitride, silicon oxynitride, etc.
Next, as shown in fig. 7B, the protective layer 180 and the phase change memory element material layer 120' are etched from top to bottom along the first direction to form a plurality of first phase change structure bodies I extending along the first direction, the phase change memory layer 121' forms a phase change memory pre-layer 121 ″ extending along the first direction, the upper electrode material layer 122' forms an upper electrode pre-layer 122 ″ extending along the first direction, and the protective layer material layer "forms a protective layer pre-layer 180 extending along the first direction". The first phase change structure I comprises a stack of a phase change memory pre-layer 121", an upper electrode pre-layer 122" and a protective layer pre-layer 180 "extending in a first direction.
In practice, a photoresist mask (not shown) may be formed on the protective layer material layer 180', and the photoresist mask may be patterned by exposure and development. The protective layer material layer 180 'and the phase change memory element material layer 120' are etched based on the photoresist mask or the hard mask patterned based on the photoresist mask (the etching method described above may be used for etching other material layers involved in subsequent process steps). In this step, the etching process can be controlled such that the etching stops at the upper surface of the gate element material layer 110'.
Next, as shown in fig. 7C, a first set of spacer element pre-layers 160-1 "and a first set of constant value resistance element pre-layers 132-1" are formed on the sidewalls of the first phase change structure I perpendicular to the second direction, the first set of spacer element pre-layers 160-1 "covers the sidewalls of the first phase change structure I, and the first set of constant value resistance element pre-layers 132-1" covers the sidewalls of the first set of spacer layer pre-layers 160-1".
To illustrate the specific formation of the above steps, FIGS. 8A-8D are schematic cross-sectional views of the steps for forming the first set of pad element pre-layers 160-1 "and the first set of constant resistance element pre-layers 132-1". After the structure shown in FIG. 7B is formed, a first set of spacer element material layers 160-1' is formed, as shown in FIG. 8A, and then, as shown in FIG. 8B, the first set of spacer element material layers 160-1' is etched, leaving only the first set of spacer element material layers 160-1' covering the sidewalls of the first phase change structure I, forming a first set of spacer element pre-layers 160-1". Next, as shown in FIG. 8C, a first set of constant resistance element material layers 132-1 'is formed, and then, as shown in FIG. 8D, the first set of constant resistance element material layers 132-1' is etched, leaving a first set of constant resistance element pre-layers 132-1 "covering the sidewalls of the first set of spacer element pre-layers 160-1".
In practice, the material of the first set of layers of pad member material may be, for example, an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, a polymer material, or the like. In one embodiment, the first set of layers of spacer elements comprises a double layer structure of silicon dioxide/silicon nitride (SiO 2/SiN), wherein a silicon dioxide layer is located between a silicon nitride layer and the first phase change structure I. The material of the first set of layers of constant resistance element material includes a metal nitride, for example, the material of the first set of layers of constant resistance element material may include one or more of titanium nitride, tungsten nitride, or tantalum nitride. (the materials of the second group of spacer element material layers and the second group of constant-value resistance element material layers involved in the subsequent processes may be the types of the materials of the first group of spacer element material layers and the first group of constant-value resistance element material layers, respectively.)
Next, as shown in fig. 7D, the gate element material layer 110' and the first conductive line material layer 101' are etched continuously along the sidewall of the first constant value resistance element pre-layer 132-1 ″ to form a second phase change structure body II extending along the first direction, the first conductive line material layer 101' forms a first conductive line 101 extending along the first direction, and the process is completed to this point, thereby completing the step of forming the first conductive line 101 extending along the first direction. And in the above steps, the gate element material layer 110' forms a gate element pre-layer 110 "extending along the first direction, the gate element pre-layer 110" includes a lower electrode pre-layer 111", a gate layer pre-layer 112" and an intermediate electrode pre-layer 113 "extending along the third direction, and the second phase change structure II includes the first conductive line 101, the gate element pre-layer 110", the phase change memory element pre-layer 120", and the first set of spacer element pre-layers 160-1" and the first set of constant resistance element pre-layers 132-1".
Next, the process proceeds to step S602, and as shown in fig. 7E-7J, a second conductive line 102, a phase change memory element 120, and a first set of constant resistance elements 132-1 are formed, wherein the second conductive line 102 is located on the phase change memory element 120 and extends along a second direction orthogonal to the first direction, the phase change memory element 120 is shaped as a rectangular pillar, and sidewalls 150 of the rectangular pillar extend along a third direction, the sidewalls 150 include a first set of sidewalls 151 perpendicular to the second direction and a second set of sidewalls 152 perpendicular to the first direction, and the first set of constant resistance elements 132-1 are located outside the first set of sidewalls 151.
In some embodiments, as shown in fig. 7E, in order to protect the gate element pre-layer 110 "and the first constant value resistance element pre-layer 132-1" from contamination and damage, a first group of sidewall element pre-layers 170-1 "may be formed on the sidewall of the second phase change structure II. Specifically, as shown in fig. 9A-9B, a first group of side wall element material layers 170-1' may be formed on the basis of the structure shown in fig. 7D, and then the first group of side wall element material layers 170-1' may be etched, and the first group of side wall element material layers 170-1' on the side wall of the second phase change structure II may be remained, so as to obtain a first group of side wall element pre-layers 170-1 ″. In practical operation, the material of the first group of side wall element material layers 170-1' may be, for example, an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, a polymer material, and the like. In one embodiment, the first sidewall element material layer 170-1' includes a silicon dioxide/silicon nitride (SiO 2/SiN) double-layer structure, wherein the silicon dioxide layer is located between the silicon nitride layer and the second phase change structure II.
Next, as shown in fig. 7F, the protective layer pre-layer 180 ″ is removed. In practical operation, the removal of the protective layer pre-layer may be achieved by using a wet or dry etching process.
Next, as shown in fig. 7G, a planarization process is performed on the first set of pad element pre-layers 160-1", the first set of resistance element pre-layers 132-1", and the first set of sidewall element pre-layers 170", so that the upper surfaces of the first set of pad element pre-layers 160-1", the first set of resistance element pre-layers 132-1", and the first set of sidewall element pre-layers 170" are flush with the upper surface of the phase change memory element pre-layers. At this time, the three-dimensional memory structure is formed to include a substrate Sub and a plurality of third phase change structure bodies III extending in the first direction on the substrate Sub. Here, the planarization process may be implemented using, for example, chemical Mechanical Polishing (CMP).
Next, as shown in fig. 7H, in order to increase the structural stability of the three-dimensional phase change memory, the first filling layer 191 may be used to fill the gap between the adjacent third phase change structure bodies III. In some embodiments, the subsequent process may be performed without performing the filling step.
Then, as shown in fig. 7I, a second conductive line material layer 102' is formed on the third phase change structure body III and the first filling layer 191. Here, the material of the second conductive line material layer 102' may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. Next, as shown in fig. 7J, the second conductive line material layer 102', the third phase change structure body III, and the first filling layer 191 are etched along the second direction, the etching may be stopped at the upper surface of the gate element pre-layer 110 ″, and the third phase change structure body III above the upper surface of the gate element pre-layer 110 ″, the second conductive line material layer 102', and the first filling layer 191 are etched into a plurality of fourth phase change structure bodies IV extending along the second direction. Accordingly, the second conductive line material layer 102' becomes the second conductive line 102 extending along the second direction, the phase change memory element pre-layer 120 "becomes the phase change memory element 120, wherein the phase change memory layer pre-layer 121" becomes the phase change memory layer 121, and the upper electrode pre-layer 122 "becomes the upper electrode 122. The first set of pad element pre-layers 160-1", the first set of constant value resistance element pre-layers 132-1" and the first set of sidewall element pre-layers 170-1 "become a first set of pad elements 160-1, a first set of constant value resistance elements 132-1 and a first set of sidewall elements 170-1.
The process steps are performed to this point to complete the fabrication of the second conductive line, the phase change memory element, and the first set of fixed value resistive elements. According to the structure of FIG. 7J, the second conductive line 102 overlies the phase change memory element 120 and extends in a second direction orthogonal to the first direction, the phase change memory element 120 is shaped as a rectangular pillar with sidewalls 150 of the rectangular pillar extending in the third direction, the sidewalls 150 include a first set of sidewalls 151 perpendicular to the second direction and a second set of sidewalls 152 perpendicular to the first direction, the first set of fixed resistance elements 132-1 are located outside of the first set of sidewalls 151.
In the above steps, the second conductive line, the phase change memory element and the first set of constant value resistive elements are formed in the same etching step by using a uniform mask, compared with the technical scheme that the second conductive line is formed at the end of the process separately, the mask required for preparing the second conductive line is saved, the additional alignment step of aligning the second conductive line and the phase change memory element is also avoided, and the process is simplified.
Next, as shown in fig. 7K, the process proceeds to step S603, a second set of constant value resistor elements 132-2 is formed, the second set of constant value resistor elements 132-2 is located outside the second set of sidewalls 152, and the first set of constant value resistor elements 132-1 and the second set of constant value resistor elements 132-2 constitute the constant value resistor unit 132. The specific process is shown in FIGS. 10A-10E, and is described in detail below with reference to FIGS. 10A-10E.
As shown in fig. 10A, on the basis of the structure shown in fig. 7J, a second set of pad member material layers 160-2 'is first formed, the second set of pad member material layers 160-2' covering the sidewalls of the fourth phase change structure IV and the upper surfaces of the third phase change structure III and the first filling layer 191, which are not etched; next, referring to fig. 10B, the second set of spacer element material layers 160-2' are etched, leaving portions on the sidewalls of the fourth phase change structure IV, thereby forming a second set of spacer element pre-layers 160-2". Next, as shown in FIG. 10C, the second set of pad components pre-layer 160-2 'is etched back, the etching process is controlled such that the top surface of the second set of pad components pre-layer 160-2' is lowered to be lower than the top surface of the second conductive line 102 and not lower than the top surface of the phase change memory element 120, thereby forming a second set of pad components 160-2, and the sidewalls of the second conductive line 102 are at least partially exposed to the top of the second set of pad components 160-2. The second set of cushion members 160-2 together with the first set of cushion members 160-1 form a cushion layer 160. Then, as shown in fig. 10D, a second set of constant resistance element material layers 132-2 'is formed, and then, referring to fig. 10E, the second set of constant resistance element material layers 132-2' is etched, leaving portions on sidewalls of the second conductive line 102 and the second set of pad elements 160-2, thereby forming a second set of constant resistance elements 132-2 as shown in fig. 7K. The second set of constant value resistance elements 132-2 has a connection CT at the top end, and the second set of constant value resistance elements 132-2 is in contact with the second conductive line 102 through the connection CT.
The process is performed until the second set of constant value resistive elements 132-2 is completed, and since the first set of constant value resistive elements 132-1 and the second set of constant value resistive elements 132-2 together constitute the constant value resistive unit 132, the process is performed until the constant value resistive element 132 is also completed.
Next, as shown in fig. 7L, the process goes to step S604, forming a gating element 110, wherein the gating element 110 and the phase change memory element 120 are stacked and distributed in the third direction; wherein the constant value resistance unit 132 is connected in parallel with the phase change memory element 120 between the second conductive line 102 and the gating element 110.
Specifically, as shown in fig. 7L, the third phase change structure body III is continuously etched along the sidewall of the second constant value resistance element 132-2, and the etching is stopped on the upper surface of the first conductive line 101 in the third phase change structure body III, so as to form a fifth phase change structure body V extending along the second direction. In this step of etching, the gate element pre-layer 110 ″ becomes the gate element 110, wherein the lower electrode pre-layer 111", the gate layer pre-layer 112", and the intermediate electrode pre-layer 113 ″ become the lower electrode 111, the gate layer 112, and the intermediate electrode 113, respectively. According to the structure of 7L, the gating elements 110 and the phase change memory elements 120 are distributed in a stacked manner in the third direction.
Since the upper surface of the first set of constant value resistance elements 132-1 is in contact with the lower surface of the second conductive line 102, the lower surface of the second constant value resistance element 132-1 is in contact with the upper surface of the gate element 110, the top end of the second constant value resistance element 132-2 is in contact with the sidewall of the second conductive line 102 through the connection part CT, the lower surface of the second constant value resistance element 132-2 is in contact with the upper surface of the gate element 110, and the phase change memory element 120 is electrically isolated from the first and second set of constant value resistance elements 132-1 and 132-2 by the spacer layer 160, the constant value resistance unit 132 and the phase change memory element 120 are connected in parallel between the second conductive line 102 and the gate element 110.
The process is executed to complete the preparation of the gating element and the preparation of the three-dimensional phase change memory according to the embodiment of the invention.
The preparation method of the three-dimensional phase change memory provided by all the embodiments of the present invention combines the preparation of the constant value resistance unit into the sidewall preparation process of the three-dimensional phase change memory, is compatible with the existing process and equipment, and can complete the preparation of the three-dimensional phase change memory provided by the embodiments of the present invention at low cost.
In some embodiments, as shown in fig. 7M, in order to protect the gating element 110 and the constant value resistance unit 132, a second group of sidewall elements 170-2 may be formed on a sidewall of the fifth phase change structure body V, where the second group of sidewall elements 170-2 at least cover the second group of constant value resistance elements 132-2 and a sidewall of the gating element 110 perpendicular to the first direction. In an actual process, as shown in fig. 11A-11B, a second group of side wall element material layers 170-2 'may be formed first, the second group of side wall element material layers 170-2' are etched, and the second group of side wall element material layers on the side walls of the fifth phase change structure V are remained, so as to form a second group of side wall elements 170-2. Here, the material of the second group of spacer element material layers 170-2' may be, for example, an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, a polymer material, etc. In a specific embodiment, the second group of spacer element material layers may include a silicon dioxide/silicon nitride (SiO 2/SiN) double-layer structure, wherein the silicon dioxide layer is located between the silicon nitride layer and the fifth phase-change structure body V.
In some embodiments, to increase the structural stability of the three-dimensional phase change memory, as shown in fig. 7N, the method may further include filling the gaps between the adjacent second sets of sidewall elements 170-2 with a second filling layer 192. In some embodiments, this filling step may not be performed.
Fig. 12 is a schematic view of an overall structure of a three-dimensional phase change memory according to the present invention, and as shown in fig. 12, the three-dimensional phase change memory according to the present invention is a three-dimensional phase change memory with a three-dimensional cross-point architecture. The first conductive line 101 and the second conductive line 102 in the three-dimensional phase change memory of the present invention can be used as word lines (wordlines) or bit lines (bitlines), respectively, and the phase change memory element 130 is located at an intersection of the word lines and the bit lines.
In some embodiments, the material of the constant value resistance unit 132 includes a metal nitride, and in some specific embodiments, the material of the first set of constant value resistance elements 132-1 and/or the second set of constant value resistance elements 132-2 includes a metal nitride. In practical operation, the material of the resistance-fixed unit 132 includes one or more of titanium nitride, tungsten nitride, or tantalum nitride.
In practical operation, if the ratio of the resistance values of the constant value resistance unit and the phase change memory element is too large, the capability of weakening the fluctuation of the resistance value of the phase change memory element and low-frequency interference signals is difficult to meet the requirement of artificial intelligence application, and if the ratio of the constant value resistance unit is too small, the normal memory function is affected, and even the memory function is failed.
The thickness of the constant value resistance unit 132 in the direction perpendicular to the plane of the sidewall of the phase change memory element 120 and the width of the phase change memory element 120 directly affect the resistance values of the phase change memory element 120 and the constant value resistance unit 132. In a preferred embodiment, the phase change memory element 120 is formed by a 20nm line width mask etching, that is, the constant value resistance unit 132 is a rectangular column with a width of 20nm × 20nm, and the thickness of the constant value resistance unit 132 along a direction perpendicular to a plane where sidewalls of the phase change memory element 120 are located is 1-10nm. In a more preferred embodiment, the constant value resistance unit 132 has a thickness of 2-5nm in a direction perpendicular to the plane of the sidewalls of the phase change memory element 120.
It should be understood that the above embodiments are not limited to the phase change memory element and the constant value resistance unit having to be in physical contact with the gating element and the second conductive line, and in fact, may be in electrical contact rather than physical contact.
It should be noted that the embodiment of the three-dimensional phase change memory provided by the invention and the embodiment of the preparation method of the three-dimensional phase change memory belong to the same concept; the technical features described in the embodiments may be arbitrarily combined without conflict.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (13)
1. A three-dimensional phase change memory, comprising:
a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, and a phase change memory component disposed in a third direction at an intersection of the first and second conductive lines; the third direction is perpendicular to the first direction and the second direction;
the phase change memory assembly includes: the phase change memory cell comprises a phase change memory cell and a constant value resistance unit, wherein the phase change memory cell comprises: sequentially stacking a gating element and a phase change memory element distributed along the third direction between the first conductive line and the second conductive line, wherein the phase change memory element is used for storing data by phase change based on a voltage difference between the first conductive line and the second conductive line, and the gating element is used for controlling conductive connection between the phase change memory element and the first conductive line and the second conductive line; the resistance-fixed unit includes at least a second set of resistance-fixed elements including a connection extending to a sidewall of the second conductive line, the second set of resistance-fixed elements being in contact with the sidewall of the second conductive line through the connection; wherein,
the constant value resistance unit is connected in parallel with the phase change memory element.
2. The three-dimensional phase change memory of claim 1, wherein the phase change memory element is in the shape of a rectangular pillar and sidewalls of the rectangular pillar extend in the third direction, the sidewalls including a first set of sidewalls perpendicular to the second direction and a second set of sidewalls perpendicular to the first direction, the constant value resistance unit further including a first set of constant value resistance elements, the first set of constant value resistance elements being located outside the first set of sidewalls, the second set of constant value resistance elements being located outside the second set of sidewalls.
3. The three-dimensional phase change memory of claim 2, wherein an upper surface of the first set of constant value resistance elements is in contact with a lower surface of the second conductive line.
4. The three-dimensional phase-change memory according to claim 1, wherein the material of the resistance-fixed cell comprises a metal nitride.
5. The three-dimensional phase change memory according to claim 4, wherein the metal nitride comprises one or more of titanium nitride, tungsten nitride, or tantalum nitride.
6. The three-dimensional phase-change memory according to claim 2, wherein the constant value resistance unit has a thickness of 1-10nm in a direction perpendicular to a plane of the sidewall.
7. The three-dimensional phase change memory according to claim 2, further comprising: a pad layer, the pad layer including a first set of pad elements located between the first set of sidewalls and the first set of constant value resistance elements and a second set of pad elements located between the second set of sidewalls and the second set of constant value resistance elements, the positions of the upper surfaces of the second set of pad elements being lower than the positions of the upper surfaces of the second conductive lines and not lower than the positions of the upper surfaces of the phase change memory elements.
8. A preparation method of a three-dimensional phase change memory is characterized by comprising the following steps:
forming a first conductive line extending in a first direction;
forming a phase change memory component, wherein the phase change memory component comprises a phase change memory unit and a constant value resistance unit, and the phase change memory unit comprises a gating element and a phase change memory element which are distributed in a stacking mode in the third direction;
forming a second conductive line extending in a second direction; wherein the constant value resistance unit includes at least a second set of constant value resistance elements including a connection part extending to a sidewall of the second conductive line, the second set of constant value resistance elements being in contact with the sidewall of the second conductive line through the connection part;
the phase change memory element is to store data by changing phase based on a voltage difference between the first and second conductive lines; the gating element is to control a conductive connection between the phase change memory element and the first and second conductive lines; the constant value resistance unit and the phase change memory element are connected in parallel between the second conductive line and the gating element.
9. The method of claim 8, wherein forming the phase change memory component comprises:
forming the phase change memory element in the shape of a rectangular pillar having sidewalls extending in the third direction, the sidewalls including a first set of sidewalls perpendicular to the second direction and a second set of sidewalls perpendicular to the first direction, and a first set of constant value resistive elements outside the first set of sidewalls;
forming a second set of fixed value resistive elements, the second set of fixed value resistive elements being located outside the second set of sidewalls, the first set of fixed value resistive elements and the second set of fixed value resistive elements constituting the fixed value resistive elements;
forming a gating element, the gating element and the phase change storage element being distributed in a stacked manner in the third direction.
10. The method of claim 8, wherein the material of the resistance unit of constant value comprises a metal nitride.
11. The method of claim 10, wherein the metal nitride comprises one or more of titanium nitride, tungsten nitride, or tantalum nitride.
12. The method of claim 9, wherein the constant value resistance unit has a thickness of 1-10nm in a direction perpendicular to a plane of the side wall of the rectangular pillar.
13. The method of claim 9, further comprising:
forming a pad layer, the pad layer including a first set of pad elements located between the first set of sidewalls and the first set of constant value resistance elements and a second set of pad elements located between the second set of sidewalls and the second set of constant value resistance elements, the second set of pad elements having upper surfaces at a position lower than the position of the upper surface of the second conductive line and not lower than the position of the upper surface of the phase change memory element.
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