CN112234140B

CN112234140B - Phase change memory and manufacturing method and reading method thereof

Info

Publication number: CN112234140B
Application number: CN202011436707.9A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2021-03-16
Anticipated expiration: 2040-12-11
Also published as: CN112234140A

Abstract

The application discloses a phase change memory, a manufacturing method and a reading method thereof, wherein the phase change memory comprises a first conductive wire extending along a first direction, a second conductive wire extending along a second direction and a phase change memory unit arranged between the first conductive wire and the second conductive wire along a third direction, the phase change memory unit comprises a phase change element, and the first direction, the second direction and the third direction are mutually vertical; the phase change memory provided by the embodiment of the application has the advantages that a plane perpendicular to the third direction is taken as a cross section, and the area of any end face of the phase change element along the third direction is larger than the sectional area of at least one position between the two end faces of the phase change element along the third direction.

Description

Phase change memory and manufacturing method and reading method thereof

Technical Field

The present disclosure relates to the field of semiconductor memory technologies, and in particular, to a phase change memory, and a manufacturing method and a reading method thereof.

Background

The phase change memory is a nonvolatile memory, stores data by using the difference of conductivity of a compound after conversion between a crystalline state and an amorphous state, has the characteristics of high memory density, high reliability, no-power data retention and the like, and generally can only store two data in the phase change memory in the prior art.

Disclosure of Invention

In view of the above, embodiments of the present application provide a phase change memory, a method for manufacturing the same, and a method for reading the same to solve at least one problem in the background art.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

an aspect of an embodiment of the present application provides a phase change memory, including:

a first conductive line extending in a first direction, a second conductive line extending in a second direction, and a phase change memory cell disposed between the first conductive line and the second conductive line in a third direction, the phase change memory cell comprising a phase change element, wherein the first direction, the second direction, and the third direction are perpendicular to one another;

and taking a plane perpendicular to the third direction as a cross section, wherein the area of any end surface of the phase change element along the third direction is larger than the cross section area of at least one position between the two end surfaces of the phase change element along the third direction.

In some embodiments, the cross-sectional area of the phase change element decreases from the two ends to the middle in a plane perpendicular to the third direction.

In some embodiments, at least one side surface of the phase change element connecting the two end surfaces is a concave arc surface.

In some embodiments, all side surfaces of the phase change element connecting the two end surfaces are formed together as a single-sheet hyperboloid.

In some embodiments, the phase change memory cell further includes a gating element stacked with the phase change element in the third direction; the size of the phase change element in the first direction and/or the second direction is smaller than the size of the gating element in the corresponding direction.

In some embodiments, the phase change memory cell further includes a first electrode, a second electrode, and a third electrode stacked in the third direction; wherein the first electrode is disposed between the phase change element and the second conductive line; the second electrode is disposed between the phase change element and the gate element, and the third electrode is disposed between the gate element and the first conductive line;

the dimension of the first electrode in the first direction and/or the second direction is smaller than the dimension of the second electrode and the third electrode in the corresponding direction.

In some embodiments, the phase change memory further includes a first encapsulation layer covering the second conductive line, the first electrode, and a side of the phase change element, and a second encapsulation layer covering a surface of the first encapsulation layer, the second electrode, the gate element, the third electrode, and a side of the first conductive line.

In some embodiments, the first conductive lines are plural in number, the second conductive lines are plural in number, the phase change memory cells are plural in number, the first conductive lines are spaced apart along the second direction, the second conductive lines are spaced apart along the first direction, and the phase change memory cells are disposed at intersections of each of the first conductive lines and the second conductive lines.

In some embodiments, the number of the first conductive lines is plural, the number of the second conductive lines is plural, the number of the phase change memory cells is plural, the plurality of first conductive lines are disposed in parallel in the same plane to form a first conductive layer, the plurality of second conductive lines are disposed in parallel in the same plane to form a second conductive layer, the first conductive layer and the second conductive layer are alternately arranged along the third direction, and the plurality of phase change memory cells are disposed between the adjacent first conductive layers and the adjacent second conductive layers.

Another aspect of the present invention provides a method for manufacturing a phase change memory, including:

forming a first conductive line extending in a first direction;

forming a phase change memory cell stacked on the first conductive line in a third direction, the phase change memory cell including a phase change element having a cross section taken in a plane perpendicular to the third direction, an area of either end surface of the phase change element in the third direction being larger than a cross-sectional area of the phase change element at least at one position between both end surfaces of the phase change element in the third direction;

forming a second conductive line overlying the phase change memory cell in the third direction, the second conductive line extending in a second direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

In some embodiments, the forming a phase change memory cell stacked on the first conductive line in a third direction includes:

depositing a phase change material layer along the third direction;

etching the phase change material layer from top to bottom along the third direction to form a plurality of independent first phase change structure bodies arrayed along the first direction and/or the second direction;

and for each first phase change structure body, etching at least one side surface of the phase change material layer in the first phase change structure body along the arrangement direction into a concave cambered surface to form the phase change element.

In some embodiments, the phase change material layer is etched on all sides in the first and second directions to be formed into a single-sheet hyperboloid.

In some embodiments, the method for etching at least one side surface of the phase change material layer in the first phase change structure body along the arrangement direction into a concave arc surface includes dry etching or wet etching.

In some embodiments, the etching material that etches at least one side of the phase change material layer in the first phase change structure along the arrangement direction into a concave arc surface includes ammonia water and/or hydrogen peroxide.

In some embodiments, the method of manufacturing further comprises:

depositing a layer of gating element material overlying the layer of phase change material in the third direction;

after forming the phase change material layer into the phase change element, etching the gating element material layer from top to bottom in the third direction to form a gating element; wherein,

the size of the phase change element in the first direction and/or the second direction is smaller than the size of the gating element in the corresponding direction.

In some embodiments, the method of manufacturing further comprises:

forming a first electrode, a second electrode, and a third electrode stacked in the third direction; wherein the first electrode is disposed on the phase change material layer; the second electrode is arranged between the phase change material layer and the gating element material layer, and the third electrode is arranged below the gating element material layer;

correspondingly, before the phase change material layer is formed into the phase change element, etching a first electrode layer from top to bottom along the third direction to form the first electrode; etching a second electrode layer and a third electrode layer from top to bottom in the third direction while forming the gate element material layer as the gate element to form the second electrode and the third electrode, respectively;

In some embodiments, the method of manufacturing further comprises:

forming a first encapsulation layer covering the second conductive line, the first electrode, and a side of the phase change element;

forming a second encapsulation layer covering a surface of the first encapsulation layer, the second electrode, the gating element, the third electrode, and a side of the first conductive line.

In some embodiments, the method of manufacturing further comprises:

sequentially and alternately arranging a first conductive layer and a second conductive layer along the third direction, wherein a plurality of first conductive lines are arranged in parallel on the same plane to form the first conductive layer, and a plurality of second guide lines are arranged in parallel on the same plane to form the second conductive layer;

and arranging the phase change memory cell between the adjacent first conductive layer and the second conductive layer.

Another aspect of the embodiments of the present application further provides a reading method, used in any one of the above phase change memories, where the phase change memory has N resistance states, and the N resistance states respectively correspond to a 1 st threshold voltage, a 2 nd threshold voltage, and an nth threshold voltage, where N is a positive integer greater than or equal to 3, where the N is sequentially increased in number, and the method includes:

applying an Mth reading voltage to the phase change memory to obtain a corresponding Mth reading result, wherein the Mth reading voltage is greater than the Mth threshold voltage and less than the Mth +1 threshold voltage, and M is a positive integer less than or equal to N-1;

and comparing the Mth reading result with a corresponding preset value, and determining the resistance state of the phase change memory according to the comparison result.

In some embodiments, if M is equal to 1 and the comparison result is that the 1 st read result is greater than the corresponding preset value, it is determined that the phase change memory is in the 1 st resistance state;

and if the comparison result is that the 1 st reading result is smaller than the corresponding preset value, determining that the resistance state of the phase change memory is higher than the 1 st resistance state.

In some embodiments, if M is equal to N-1 and the comparison result is that the N-1 reading result is smaller than the corresponding preset value, the phase change memory is determined to be in the N-th resistance state;

and if the comparison result is that the N-1 reading result is greater than the corresponding preset value, determining that the resistance state of the phase change memory is lower than the N resistance state.

In some embodiments, corresponding to M being greater than 1 and less than N-1, and the comparison result being that the Mth read result is greater than a corresponding preset value, an M-1 th read voltage is applied to the phase change memory, the M-1 th read voltage being greater than an M-1 th threshold voltage and less than the Mth threshold voltage, and a corresponding M-1 th read result is obtained; if the corresponding M-1 reading result is smaller than the corresponding preset value, determining that the phase change memory is in the M resistance state; if the M-1 reading result is larger than the corresponding preset value, determining that the resistance state of the phase change memory is lower than the M resistance state;

applying an M +1 th reading voltage to the phase change memory corresponding to the condition that M is larger than 1 and smaller than N-1 and the comparison result is that the Mth reading result is smaller than a corresponding preset value, wherein the M +1 th reading voltage is larger than the M +1 th threshold voltage and smaller than the M +2 th threshold voltage, and acquiring a corresponding M +1 th reading result; if the reading result corresponding to the M +1 th reading result is larger than the corresponding preset value, determining that the phase change memory is in an M +1 th resistance state; and if the M +1 th reading result is smaller than the corresponding preset value, determining that the resistance state of the phase change memory is higher than the M +1 th resistance state.

In the phase change memory provided by the embodiment of the application, the phase change memory cell is responsive to the electrical signals from the first and second conductive lines to realize a programming process or a reading process, and since the area of any end surface of the phase change element along the third direction is larger than the cross-sectional area of at least one position between the end surfaces of the phase change element along the third direction by taking a plane perpendicular to the third direction as a cross-section, when a programming current flows through the phase change element, the position with the smaller cross-sectional area of the phase change element has a larger programming current density relative to other positions of the phase change element, while the phase change of the phase change element is related to joule heat, which is in turn positively related to the programming current density, and at the position with the smallest cross-sectional area of the phase change element, a smallest programming current is required to change the phase state of the phase change element, for example; while the phase change material near the two ends requires the maximum programming current to change the phase state of the phase change element, e.g., from a crystalline state to an amorphous state; in this way, providing different programming currents to the phase change element causes the phase change at different positions of the phase change element, that is, providing different programming currents to the phase change element controls the phase change condition of the phase change element, for example, providing different programming currents, the phase change material of different volume sizes of the phase change element undergoes phase change, so that the phase change element has multiple resistance states, and the phase change element has multiple corresponding threshold switches, thereby implementing multi-state storage, so as to be able to store multiple data.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

FIG. 1 is a schematic diagram of a phase change memory in the prior art;

FIG. 2 is a graph illustrating the characteristics of program voltages corresponding to the phase change memory of FIG. 1;

fig. 3 is a schematic structural diagram of a phase change memory according to an embodiment of the present disclosure, wherein amorphous regions corresponding to four resistance states of the phase change memory are shown;

FIG. 4 is a graph illustrating the characteristics of programming voltages for four resistance states of the phase change memory of FIG. 3;

FIG. 5 is a schematic structural diagram of another phase change memory according to an embodiment of the present disclosure;

fig. 6 is a flowchart illustrating a method for manufacturing a phase change memory according to an embodiment of the present disclosure;

FIGS. 7 through 13 are cross-sectional views of a phase change memory in some embodiments, wherein the cross-section is taken along a plane perpendicular to the extending direction of the first conductive lines;

FIGS. 14 through 18 are cross-sectional views of a phase change memory in some embodiments, wherein the cross-section is taken along a plane perpendicular to the direction in which the second conductive lines extend;

fig. 19 is a flowchart of a reading method according to an embodiment of the present application.

Description of the reference numerals

Bit line 1; a word line 2; a phase change memory structure 3; a phase change section 301;

a first conductive line 10; a second electrically conductive line 20; a phase change memory cell 30; a phase change element 31; a gating element 32; a first electrode 33; a second electrode 34; a third electrode 35; a first encapsulation layer 40; an inner layer 41; an intermediate layer 42; a second encapsulation layer 50; an outer layer 51; a filler layer 52; a substrate 1000; a first mask layer 100 a; the first phase change structure 200 a; the second phase change structure 300 a; a first conductive line material layer 10 a; a second conductive line material layer 20 a; the phase change material layer 31 a; a gating element material layer 32 a; the first electrode material layer 33 a; the second electrode material layer 34 a; the third electrode material layer 35 a.

Detailed Description

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions. And should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Referring to fig. 1 and 2, in fig. 2, Vth, set is a threshold voltage during setting of logic "1", i.e., set, Vth, reset is a threshold voltage during setting of logic "0", i.e., reset, an abscissa Vcell is a programming voltage of a Phase Change Memory of the related art, and an ordinate Icell is a corresponding programming current, the Phase Change Memory (PCM) of the related art includes a Bit Line (BL) 1 extending in a first direction, a Word Line (WL) 2 extending in a second direction, and a Phase Change Memory structure 3 disposed between the Word Line 2 and the Bit Line 1 in a third direction, the Phase Change Memory structure 3 includes a Phase Change portion 301, the Phase Change Memory structure 3 is a self-aligned pillar structure, wherein the first direction, the second direction and the third direction are perpendicular to each other, the Word Line 2 and the Bit Line 1 are used for carrying an electrical signal to the corresponding Phase Change portion 301, illustratively, selecting a word line 2 and a bit line 1, that is, selecting a phase change portion 301 located between the word line 2 and the bit line 1, conducting between the word line 2, the bit line 1 and the corresponding phase change portion 301, and implementing a programming process or a reading process by applying different electrical signals to the conducting word line 2, the conducting bit line 1 and the corresponding phase change portion 301, the phase change memory of the prior art generally stores two data, one is to implement setting logic "1" (see set curve in fig. 2): the phase change material is gradually crystallized by applying a wide and weak programming current to the phase change part 301 in the process of changing the phase change material from an amorphous state to a crystalline state, so that the phase change material is in a lower resistance state, and the logic '1' is set; the other is to implement a reset logic "0" (see reset curve in fig. 2): the phase change material is a process of changing the phase change material from a crystalline state to an amorphous state, a narrow and strong programming current is instantly applied to the phase change part 301 to melt the phase change part 301, and then the phase change material is rapidly cooled to change the phase change material from the crystalline state to the amorphous state, so that the phase change material is in a higher resistance state to realize a reset logic '0'; taking a plane perpendicular to the third direction as a cross section, the cross sectional area size at any position of the prior art cylindrical phase change memory structure 3 is consistent, and it is difficult for the phase change portion 301 to realize a plurality of resistance states, and thus, it is difficult to store a plurality of data.

Referring to fig. 3 to 5, an embodiment of the present invention provides a phase change memory, which includes a first conductive line 10 extending along a first direction, a second conductive line 20 extending along a second direction, and a phase change memory cell 30 disposed between the first conductive line 10 and the second conductive line 20 along a third direction, wherein the phase change memory cell 30 includes a phase change element 31, and the first direction, the second direction, and the third direction are perpendicular to each other; the area of any one end face of the phase change element 31 in the third direction is larger than the sectional area of at least one position between both end faces of the phase change element 31 in the third direction, taking a plane perpendicular to the third direction as a section.

In the phase change memory provided in the embodiment of the present application, the phase change memory cell 30 implements a programming process or a reading process in response to the electrical signals from the first conductive line 10 and the second conductive line 20, for example, a programming current or a programming voltage is applied to reversibly change the resistance state of the phase change element 31 to implement the programming process; for example, applying a read current or a read voltage to read the resistance state of the element to obtain the stored data of the phase change memory cell 30; since the area of any end surface of the phase change element 31 in the third direction is larger than the cross-sectional area of at least one position between the end surfaces of the phase change element 31 in the third direction when the plane perpendicular to the third direction is taken as a cross-section, when a programming current flows through the phase change element 31, the position where the cross-sectional area of the phase change element 31 is smaller has a larger programming current density relative to other positions of the phase change element 31, while the phase change of the phase change element 31 is related to joule heat, which is in turn positively related to the programming current density, and the minimum programming current is required at the position where the cross-sectional area of the phase change element 31 is minimum to change the phase state of the phase change element 31, for example, the phase change element 31 is converted from the; while the phase change material near the two ends requires the maximum programming current to change the phase state of the phase change element 31, e.g., from a crystalline state to an amorphous state; in this manner, providing different programming currents to the phase change element 31 causes the phase change at different positions of the phase change element 31, that is, providing different programming currents to the phase change element 31 controls the phase change of the phase change element 31, and providing different programming currents, for example, phase change materials of different volume sizes of the phase change element 31 undergo phase change, so that the phase change element 31 has a plurality of resistance states, and the phase change element 31 has a plurality of corresponding threshold switches, thereby implementing multi-state storage, so that a plurality of data can be stored.

It should be noted that, in the embodiments of the present application, the number of the plurality of.

It is understood that, in the embodiment of the present application, the first conductive line 10 and the second conductive line 20 may also be referred to as a word line and a bit line, and for example, in an embodiment, the first conductive line 10 is a word line, and the second conductive line 20 is a bit line; in another embodiment, the second conductive line 20 is a word line, and the first conductive line 10 is a bit line, which is only the difference between the first conductive line 10 and the second conductive line 20.

For example, in one embodiment, the phase change memory has 4 resistance states, each resistance state corresponds to a threshold voltage, and the 4 resistance states correspond to 4 threshold voltages, and the phase change element is made to be in a corresponding amorphous state by controlling the programming voltage to be at the corresponding threshold voltage, so that the phase change memory is in different resistance states, as shown in fig. 3 and 4, where the black filled portion in fig. 3 is an amorphous region of the phase change element 31, and as shown in fig. 3, in the resistance state 1, the phase change element 31 is fully in the crystalline state, which corresponds to the characteristic curve of the resistance state 1 in fig. 4; in the 2 nd resistance state, a small middle portion of the phase change element 31 is in an amorphous state, which corresponds to the characteristic curve of the 2 nd resistance state in fig. 4; in the 3 rd resistance state, the amorphous region of the phase change element 31 expands from the middle to both ends, and the volume of the amorphous region in the 3 rd resistance state is larger than that of the amorphous region in the 2 nd resistance state, corresponding to the characteristic curve of the 3 rd resistance state in fig. 4; in the 4 th resistance state, the phase change element 31 is in an entirely amorphous state, corresponding to the characteristic curve of the 4 th resistance state in FIG. 4.

In one embodiment, referring to fig. 3 and 5, the cross-sectional area of the phase change element 31 is gradually decreased from two ends to the middle by taking a plane perpendicular to the third direction as a cross-section. Since the phase change occurs first at the position where the cross-sectional area of the phase change element 31 is smaller (see fig. 3), the cross-sectional area is smallest at the middle position of the phase change element 31, and for example, the programming current is smallest when the amorphous region is limited to the middle position of the phase change element 31; when the amorphous region is expanded to the whole phase change element 31, the programming current is the largest, the programming current is gradually increased from small to large, the amorphous region of the phase change element 31 is gradually expanded from the middle position to two ends, so that the phase change element 31 has a plurality of resistance states, and as the phase change element 31 is firstly changed in the middle position, the phase change memory has higher reliability and more stable performance.

In one embodiment, referring to fig. 3 and 5, at least one side surface of the phase change element 31 connecting the two end surfaces is a concave arc surface. In this way, the cross-sectional area of any position between the two end surfaces of the phase change element 31 in the third direction is smaller than the area of any end surface of the phase change element 31 in the third direction, so that the phase change element 31 has a plurality of resistance states, and any position between the two ends of the phase change element 31 is changed in phase first, so that the phase change memory has higher reliability and more stable performance.

Illustratively, the phase change element 31 has four sides, and in a specific embodiment, one side of the phase change element 31 is a concave arc; in another embodiment, two side surfaces of the phase change element 31 are concave arc surfaces; in another embodiment, three sides of the phase change element 31 are concave arc surfaces; in another embodiment, referring to fig. 3 and 5, four side surfaces of the phase change element 31 are concave arc surfaces.

In one embodiment, all side surfaces of the phase change element 31 connecting the two end surfaces are formed together as a single-sheet hyperboloid. In this way, the cross-sectional area of any position between the two end surfaces of the phase change element 31 in the third direction is smaller than the area of any end surface of the phase change element 31 in the third direction, so that the phase change element 31 has a plurality of resistance states, and any position between the two ends of the phase change element 31 is changed in phase first, so that the phase change memory has higher reliability and more stable performance.

Referring to fig. 3 and 5, the phase change memory cell 30 further includes a gate element 32 stacked with the phase change element 31 along a third direction, in one embodiment, the size of the phase change element 31 in the first direction is smaller than the size of the gate element 32 in the first direction; in another embodiment, the size of the phase change element 31 in the second direction is smaller than the size of the gate element 32 in the second direction; in yet another embodiment, the size of the phase change element 31 in the first and second directions is smaller than the size of the gate element 32 in the first and second directions; therefore, a plane perpendicular to the third direction is taken as a cross section, the cross section area of the phase change element 31 is smaller than that of the gating element 32, and as the cross section area of the programming current passing through the phase change element 31 is smaller, the programming current density of the programming current passing through the phase change element 31 is smaller, the power consumption of the phase change memory is smaller, and the current density requirement of the gating element 32 can be lower, the phase change memory provided by the embodiment of the application has smaller programming current and smaller power consumption, and the time length of a programming process can be reduced; on the other hand, the smaller size of the phase change elements 31 in the first direction and/or the second direction causes the distance between the phase change elements 31 of two adjacent phase change memory cells 30 to be relatively increased, and thus, the thermal crosstalk between the phase change elements 31 of two adjacent phase change memory cells 30 is smaller.

Referring to fig. 3 and 5, the phase change memory cell 30 further includes a first electrode 33, a second electrode 34, and a third electrode 35 stacked along a third direction; wherein the first electrode 33 is disposed between the phase change element 31 and the second conductive line 20; the second electrode 34 is disposed between the phase change element 31 and the gate element 32, and the third electrode 35 is disposed between the gate element 32 and the first conductive line 10; in one embodiment, the size of the first electrode 33 in the first direction is smaller than the size of the second electrode 34 and the size of the third electrode 35 in the first direction, that is, the size of the first electrode 33 in the first direction is smaller than the size of the second electrode 34 in the first direction, and the size of the first electrode 33 in the first direction is smaller than the size of the third electrode 35 in the first direction; in another embodiment, the dimension of the first electrode 33 in the second direction is smaller than the dimensions of the second electrode 34 and the third electrode 35 in the second direction; in yet another embodiment, the dimensions of the first electrode 33 in the first and second directions are smaller than the dimensions of the second electrode 34 and the third electrode 35 in the first and second directions. In this way, the sectional area of the first electrode 33 is smaller than the sectional areas of the second electrode 34 and the third electrode 35 with respect to a plane perpendicular to the third direction as a cross section, and power consumption of the phase change memory is smaller. On the other hand, the second electrode 34 can isolate the phase change element 31 and the gate element 32, thereby preventing the phase change element 31 material and the gate element 32 material from diffusing and contaminating each other and changing the performance.

In one embodiment, referring to fig. 3 and 5, the first electrode 33, the phase change element 31, the second electrode 34, the gate element 32, and the third electrode 35 are sequentially stacked from top to bottom along a third direction, one of the first electrode 33 and the third electrode 35 is in contact with the first conductive line 10, the other of the first electrode 33 and the third electrode 35 is in contact with the second conductive line 20, a plane perpendicular to the third direction is taken as a cross section, a cross sectional area of the second electrode 34, a cross sectional area of the gate element 32, and a cross sectional area of the third electrode 35 are substantially the same, and the cross sectional area of the first electrode 33 is smaller than the cross sectional area of the second electrode 34. The etching steps of the first electrode 33 and the phase change element 31 are different from the etching steps of the second electrode 34, the gate element 32 and the third electrode 35, so that the cross contamination of the materials of the phase change element 31 and the gate element 32 can be avoided.

In some embodiments, the end of the phase change element 31 facing away from the second electrode 34 is not provided with the first electrode 33. In other embodiments, no second electrode 34 may be disposed between the phase change element 31 and the gate element 32. In still other embodiments, no third electrode 35 is disposed on the end of the gating element 32 facing away from the second electrode 34.

In one embodiment, referring to fig. 5, 10 and 11, the phase change memory further includes a first packaging layer 40 and a second packaging layer 50, the first packaging layer 40 covers the second conductive line 20, the first electrode 33 and the side of the phase change element 31, that is, the first packaging layer 40 covers the side of the second conductive line 20, the side of the first electrode 33 and the side of the phase change element 31, in one embodiment, the first packaging layer 40 covers all sides of the second conductive line 20, all sides of the first electrode 33 and all sides of the phase change element 31; the second encapsulation layer 50 covers the surface of the first encapsulation layer 40, the second electrode 34, the gate element 32, the third electrode 35, and the side of the first conductive line 10, that is, the second encapsulation layer 50 covers the surface of the first encapsulation layer 40, the side of the second electrode 34, the side of the gate element 32, the side of the third electrode 35, and the side of the first conductive line 10, and in a specific embodiment, the second encapsulation layer 50 covers the surface of the first encapsulation layer 40, all the sides of the second electrode 34, all the sides of the gate element 32, all the sides of the third electrode 35, and all the sides of the first conductive line 10. The first encapsulation layer 40 can protect the side of the second conductive line 20, the side of the first electrode 33, and the side of the phase change element 31, prevent contamination and performance change caused by diffusion of the phase change element 31 material and the gate element 32 material, and reduce thermal crosstalk between two adjacent phase change memory cells 30. The second encapsulation layer 50 can protect the surface of the first encapsulation layer 40, the side of the second electrode 34, the side of the gate element 32, the side of the third electrode 35, and the side of the first conductive line 10, further avoid contamination and performance change caused by diffusion of the phase change element 31 material and the gate element 32 material, and further reduce thermal crosstalk between two adjacent phase change memory cells 30.

In one embodiment, referring to fig. 5, 10 and 11, the first packaging layer 40 includes an inner layer 41 adjacent to the side of the phase change element 31 and an intermediate layer 42 covering the side of the inner layer 41, and the inner layer 41 and the intermediate layer 42 are of a double-layer structure to better protect the side of the phase change element 31.

Illustratively, inner layer 41 may be a thermally insulating material, and inner layer 41 includes, but is not limited to, a thermally insulating nitride, for example, inner layer 41 is silicon nitride. Intermediate layer 42 may be a thermally insulating material, with intermediate layer 42 including, but not limited to, a thermally insulating oxide, for example, with intermediate layer 42 being silicon oxide.

In one embodiment, referring to fig. 5, 10 and 11, the second encapsulation layer 50 includes an outer layer 51 covering the sides of the intermediate layer 42 and the sides of the gating element 32, and a filling layer 52 covering the outer layer 51. In this way, the gate element 32 and the phase change element 31 can be better protected.

Illustratively, the outer layer 51 may be a thermally insulating material, the outer layer 51 including, but not limited to, a thermally insulating nitride, for example, the outer layer 51 being silicon nitride. The fill layer 52 may be a thermally insulating material, and the fill layer 52 includes, but is not limited to, a thermally insulating oxide, for example, the fill layer 52 is silicon oxide. The gap between the outer layers 51 of two adjacent phase change memory cells 30 may be filled with a filling material by atomic layer deposition, chemical vapor deposition, Spin On Dielectric (SOD), or the like to form a filling layer 52. The filler layer 52 may have air gaps therein. In one embodiment, at least one air gap is formed during the process of filling the gap between the outer layers 51 of two adjacent phase change memory cells 30 with the filling material, and air or other gas is filled in the air gap, so that the air gap is utilized to form a better thermal insulation effect.

In one embodiment, the gating element 32 may be a two-terminal device, and the gating element 32 includes, but is not limited to, a diode or an Ovonic Threshold Switch (OTS), etc.

Specifically, the bidirectional threshold switch controls the on or off of the bidirectional threshold switch by using a gating electrical signal, when the applied gating electrical signal is higher than the threshold voltage of the gating element 32, the material of the gating element 32 is converted from a high resistance state to a low resistance state, and at the moment, the bidirectional threshold switch is in an on state; when the gating electrical signal is removed, the gating element 32 material transitions from a low resistance state to a high resistance state again, with the device in an off state.

In one embodiment, referring to fig. 3 and 5, the phase-change memory cell 30 is a self-aligned pillar structure, and has a cross-section taken along a plane perpendicular to the third direction, the cross-section of the first electrode 33 is substantially quadrilateral, the cross-section of the second electrode 34 is substantially quadrilateral, the cross-section of the gate element 32 is substantially quadrilateral, and the cross-section of the third electrode 35 is substantially quadrilateral.

In one embodiment, the first electrode 33 is a conductive material, for example, the first electrode 33 can be amorphous carbon, tungsten, aluminum, copper, titanium, or the like. Preferably, the first electrode 33 may also be made of a conductive material with low thermal conductivity, so as to avoid too fast heat conduction of the phase change element 31, and reduce power consumption of the phase change memory.

In one embodiment, the second electrode 34 is a conductive material, for example, the second electrode 34 can be amorphous carbon, tungsten, aluminum, copper, titanium, or the like. Preferably, the second electrode 34 may also be made of a conductive material with low thermal conductivity, so as to avoid too fast heat conduction of the phase change element 31, which can reduce the power consumption of the phase change memory.

In one embodiment, the third electrode 35 is a conductive material, for example, the third electrode 35 can be amorphous carbon, tungsten, aluminum, copper, titanium, or the like.

In one embodiment, phase change element 31 may be a chalcogenide compound, for example, phase change element 31 may be a germanium-antimony-tellurium (Ge-Sb-Te, GST) material, an indium-antimony-tellurium (In-Sb-Te, IST) material, or the like, for example, phase change element 31 may be Ge₂Sb₂Te₅、Ge₁Sb₄Te₇、In₂Sb₂Te₅Or In₁Sb₂Te₄And so on.

In one embodiment, the gating elements 32 may be chalcogenide compounds, and the gating elements 32 may be Ge-Se, Ge-Te-Pb, Ge-Se-Te, or the like.

In one embodiment, the first conductive line 10 may be a conductive material, and the conductive material may be a metal material, which has a relatively high conductivity and a relatively good conductivity, and for example, the material of the first conductive line 10 includes, but is not limited to, tungsten, aluminum, copper, titanium, or the like.

In one embodiment, the second conductive line 20 may be a conductive material, and the conductive material may be a metal material, which has a larger conductivity and a better conductivity, and the material of the second conductive line 20 includes, but is not limited to, tungsten, aluminum, copper, or titanium, for example.

In one embodiment, referring to fig. 5, the number of the first conductive lines 10 is plural, the number of the second conductive lines 20 is plural, the number of the phase change memory cells 30 is plural, the plurality of first conductive lines 10 are disposed at intervals along the second direction, the plurality of second conductive lines 20 are disposed at intervals along the first direction, and the phase change memory cell 30 is disposed at the intersection of each of the first conductive lines 10 and the second conductive lines 20. That is, the plurality of phase change memory cells 30 may be arranged in a two-dimensional array. In this way, the phase change memory includes a large number of phase change memory cells 30, and the storage capacity of the phase change memory can be increased, so that more data can be stored.

In one embodiment, referring to fig. 5, the number of the first conductive lines 10 is multiple, the number of the second conductive lines 20 is multiple, the number of the phase change memory cells 30 is multiple, the multiple first conductive lines 10 are disposed in parallel in the same plane to form a first conductive layer, the multiple second guide lines 20 are disposed in parallel in the same plane to form a second conductive layer, that is, the first conductive lines 10 in the first conductive layer are arranged in one dimension, the second conductive lines 20 in the second conductive layer are arranged in one dimension, the first conductive layers and the second conductive layers are alternately arranged in a third direction, and the multiple phase change memory cells 30 are disposed between adjacent first conductive layers and adjacent second conductive layers. In this way, in a limited space, the phase change memory may have more phase change memory cells 30 to form a three-dimensional phase change memory cell 30 stacked structure, specifically, the phase change memory is a three-dimensional cross-point (3D-Xpoint) phase change memory, so as to improve the storage capacity of the phase change memory, for example, a first conductive layer of a first layer, a plurality of phase change memory cells 30, a second conductive layer of the first layer, a plurality of phase change memory cells 30, a first conductive layer of a second layer, a plurality of phase change memory cells 30, a second conductive layer of the second layer, a plurality of phase change memory cells 30, a first conductive layer of a third layer, a plurality of phase change memory cells 30, and a second conductive layer of the third layer may be sequentially stacked from bottom to top along a third direction, so as to form a three-layer stacked structure. The above is merely an example, the phase change memory provided in the embodiments of the present application includes, but is not limited to, a two-layer stacked structure, a four-layer stacked structure, a five-layer stacked structure, or a six-layer stacked structure, and the like, and a person skilled in the art can implement a three-dimensional stacked structure with two layers and more than two layers according to the technical solutions disclosed in the present application, and details are not repeated here.

Referring to fig. 6, another aspect of the present disclosure provides a method for manufacturing a phase change memory, the method comprising:

s110: forming a first conductive line extending in a first direction;

s120: forming a phase change memory cell stacked on the first conductive line in a third direction, the phase change memory cell including a phase change element having a cross section taken in a plane perpendicular to the third direction, an area of either end surface of the phase change element in the third direction being larger than a cross-sectional area of the phase change element at least at one position between both end surfaces of the phase change element in the third direction;

s130: forming a second conductive line overlying the phase change memory cell in the third direction, the second conductive line extending in a second direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

In the phase change memory formed by the manufacturing method according to the embodiment of the present application, since a plane perpendicular to the third direction is taken as a cross section, referring to fig. 3 and 5, an area of any end surface of the phase change element 31 along the third direction is larger than a cross section area of at least one position between two end surfaces of the phase change element 31 along the third direction, when a programming current flows through the phase change element 31, a position with a smaller cross section area of the phase change element 31 has a larger programming current density relative to other positions of the phase change element 31, and a position with a smallest cross section area of the phase change element 31 requires a smallest programming current to change a phase state of the phase change element 31, for example, the phase change element 31 is converted from a crystalline state to an amorphous; while the phase change material near the two ends requires the maximum programming current to change the phase state of the phase change element 31, e.g., from a crystalline state to an amorphous state; in this manner, providing different programming currents to the phase change element 31 causes the phase change at different positions of the phase change element 31, that is, providing different programming currents to the phase change element 31 controls the phase change of the phase change element 31, and providing different programming currents, for example, phase change materials of different volume sizes of the phase change element 31 undergo phase change, so that the phase change element 31 has a plurality of resistance states, and the phase change element 31 has a plurality of corresponding threshold switches, thereby implementing multi-state storage, so that a plurality of data can be stored.

In one embodiment, the forming a phase change memory cell stacked on the first conductive line in a third direction includes:

s121: depositing a phase change material layer along the third direction;

s122: etching the phase change material layer from top to bottom along the third direction to form a plurality of independent first phase change structure bodies arrayed along the first direction and/or the second direction;

s123: and for each first phase change structure body, etching at least one side surface of the phase change material layer in the first phase change structure body along the arrangement direction into a concave cambered surface to form the phase change element.

Referring to fig. 8 and 9, in an exemplary embodiment, a plurality of first phase change structure bodies 200a are arranged along a first direction, and one side surface of the phase change material layer 31a of each first phase change structure body 200a along the first direction is etched to be a concave arc surface. In another embodiment, the plurality of first phase change structure bodies 200a are arranged along the first direction, and both side surfaces of the phase change material layer 31a of each first phase change structure body 200a along the first direction are etched into concave arc surfaces.

In another embodiment, the plurality of first phase change structure bodies 200a are arranged along the second direction, and one side surface of the phase change material layer 31a of each first phase change structure body 200a along the second direction is etched to be a concave arc surface. In another embodiment, the plurality of first phase change structure bodies 200a are arranged along the second direction, and two side surfaces of the phase change material layer 31a of each first phase change structure body 200a along the second direction are etched to be concave arc surfaces.

In an embodiment, which is not shown, a plurality of independent first phase change structure bodies 200a are arranged along a first direction and a second direction, the first phase change structure bodies 200a are columnar structures, and at least one side surface of the phase change material layer 31a of each first phase change structure body 200a along the first direction and/or the second direction is etched into a concave arc surface.

In an embodiment, referring to fig. 7 and 8, a first mask layer 100a may be deposited on the phase change material layer 31a, and a pattern of the first mask is transferred onto the first mask layer 100a by a photolithography process, so that the first mask layer 100a has a first predetermined pattern. Based on the first predetermined pattern of the first mask layer 100a, the phase change material layer 31a is etched from top to bottom until a plurality of independent first phase change structure bodies 200a arranged along the first direction or the second direction are formed, at this time, the first phase change structure bodies 200a extend along a direction perpendicular to the arrangement direction thereof, each first phase change structure body 200a includes the phase change material layer 31a, and each phase change material layer 31a extends along a direction perpendicular to the arrangement direction of the first phase change structure bodies 200a (see fig. 14). Illustratively, the plurality of first phase change structure bodies 200a are arranged in the first direction, and each of the first phase change structure bodies 200a includes the phase change material layer 31a extending in the second direction. Referring to fig. 9 to 16, for each first phase change structure 200a, at least one side surface of the phase change material layer 31a in the first phase change structure 200a along the arrangement direction is etched into a concave arc surface, and the phase change element 31 formed by the above etching method can make the cross-sectional area of any position between two end surfaces of the phase change element 31 along the third direction smaller than the area of any end surface of the phase change element 31 along the third direction, so that the phase change element 31 has a plurality of resistance states, and at least one position between two ends of the phase change element 31 changes phase first, and thus the phase change memory has higher reliability and more stable performance.

Referring to fig. 15, in an embodiment, the first phase change structure 200a extends along a direction perpendicular to the arrangement direction thereof, and each of the first phase change structure 200a is etched from top to bottom along a third direction based on the second predetermined pattern of the second mask layer to form a plurality of trenches on each of the first phase change structure 200 a; at least one side surface of each phase change material layer 31a corresponding to the groove is etched into a concave arc surface. The second preset pattern of the second mask plate may be transferred onto the second mask layer through a photolithography process, so that the second mask layer has the second preset pattern, and each of the first phase change structure bodies 200a is etched from top to bottom along the third direction, so that a plurality of trenches are formed on each of the first phase change structure bodies 200a at intervals along the extending direction thereof, so that each of the first phase change structure bodies 200a has a specific size in the extending direction thereof. In another embodiment, each of the first phase change structure bodies 200a is etched from top to bottom along the third direction based on the second preset pattern of the second mask plate, so as to form a plurality of trenches on each of the first phase change structure bodies 200a at intervals along the extending direction thereof. That is, the second mask layer may not be formed on the first phase change structure 200a, and the etching may be performed directly using the second mask plate as a mask.

Illustratively, in an embodiment, each of the first phase change structure bodies 200a extends along the second direction, and each of the first phase change structure bodies 200a is etched from top to bottom along the third direction based on the second predetermined pattern of the second mask layer to form a plurality of trenches spaced along the second direction on each of the first phase change structure bodies 200a, and each of the first phase change structure bodies 200a has a specific size along the second direction. In another embodiment, each of the first phase change structure bodies 200a extends along the first direction, and each of the first phase change structure bodies 200a is etched from top to bottom along the third direction to form a plurality of trenches spaced along the first direction on each of the first phase change structure bodies 200a, and each of the first phase change structure bodies 200a has a specific size along the first direction.

It is understood that the first mask layer 100a needs to be removed before the second mask layer is disposed, and for example, referring to fig. 12, in one embodiment, the first mask layer 100a may be planarized by Chemical Mechanical Polishing (CMP) along the third direction until the removal of the first mask layer 100a stops.

Referring to fig. 16, in an exemplary embodiment, each of the first phase change structure bodies 200a forms a plurality of trenches spaced apart along the second direction, such that each of the first phase change structure bodies 200a forms a plurality of independent phase change material layers 31a with specific dimensions, each of the independent phase change material layers 31a with specific dimensions has two sides along the second direction, that is, each of the phase change material layers 31a has two sides along the second direction corresponding to the trench, wherein, in some embodiments, one side along the second direction of each of the independent phase change material layers 31a with specific dimensions is etched to be a concave arc surface; in other embodiments, both sides of each independent phase change material layer 31a having a specific size in the second direction are etched into concave arc surfaces.

In another embodiment, each of the first phase change structure bodies 200a is formed by forming a plurality of grooves at intervals along the first direction, and etching one side surface of each of the independent phase change material layers 31a having a specific size along the first direction into a concave arc surface. In another embodiment, a plurality of grooves are formed in each first phase change structure 200a at intervals along the first direction, and two sides of each independent phase change material layer 31a with a specific size along the first direction are etched to be concave arc surfaces.

It should be noted that, in the embodiment of the present application, the third direction is an up-down direction, that is, the third direction and the up-down direction are the same direction, and are used herein for convenience of description to describe the relationship between the element or the feature and other elements or features in the embodiment of the present application, when the structure of the phase change memory is understood, if the phase change memory is turned upside down, the upper side in the embodiment of the present application is referred to as the corresponding lower side, and it should be understood by those skilled in the art that the relationship between the element or the feature and other elements or features is not changed by the change of the direction.

In one embodiment, S1231: the phase change material layer is etched on all sides in the first and second directions to be formed into a single-sheet hyperboloid.

In some embodiments, S1231: the phase change material layer is etched along all side surfaces of the first direction and the second direction to form a single-sheet hyperboloid, and the method specifically comprises the following steps: a phase change material layer 31a having a cylindrical shape with four side surfaces is formed first, and all of the four side surfaces of the phase change material layer 31a having a cylindrical shape are etched to be formed into a single-sheet hyperboloid.

In an embodiment, the method for etching at least one side surface of the phase change material layer in the first phase change structure along the arrangement direction into a concave arc surface includes dry etching or wet etching.

In some embodiments, for each first phase change structure 200a, the two side surfaces of the phase change material layer 31a in the first phase change structure 200a along the arrangement direction are etched into concave arc surfaces by using dry etching or wet etching. In some embodiments, dry etching or wet etching is adopted to etch two side surfaces of each phase change material layer 31a corresponding to the trench into concave arc surfaces. In still other embodiments, the phase change material layer 31a is etched on all sides in the first and second directions to be formed as a single-sheet hyperboloid using dry etching or wet etching.

In an embodiment, the etching material for etching at least one side surface of the phase change material layer in the first phase change structure along the arrangement direction into a concave arc surface includes ammonia water and/or hydrogen peroxide.

In some embodiments, the etching material that etches at least one side of the phase change material layer 31a in the first phase change structure 200a into a concave arc surface includes ammonia water. In other embodiments, the etching material for etching at least one side surface of the phase change material layer 31a in the first phase change structure 200a into a concave arc surface includes hydrogen peroxide. In still other embodiments, the etching material that etches at least one side of the phase change material layer 31a in the first phase change structure 200a into a concave arc surface includes ammonia water and hydrogen peroxide.

In one embodiment, the method of manufacturing further comprises:

s210: depositing a layer of gating element material overlying the layer of phase change material in the third direction;

referring to fig. 7, the gate element material layer 32a may be deposited in the third direction, and then the phase change material layer 31a may be deposited.

S220: after forming the phase change material layer into the phase change element, etching the gating element material layer from top to bottom in the third direction to form a gating element; wherein,

For example, in an embodiment, referring to fig. 11 to 14, a third preset pattern of a third mask plate may be transferred onto the third mask layer through a photolithography process, so that the third mask layer has the third preset pattern, and the gate element material layer 32a is etched from top to bottom along a third direction based on the third preset pattern of the third mask layer, so as to form a plurality of independent second phase change structures 300a arranged in the same direction as the arrangement direction of the first phase change structures 200a, wherein the second phase change structures 300a extend along a direction perpendicular to the arrangement direction; in another embodiment, a third mask layer may not be formed on the second phase change structure 300a, and the third mask plate may be directly used as a mask for etching; referring to fig. 17, a fourth preset pattern of the fourth mask may be transferred onto the fourth mask layer through a photolithography process, so that the fourth mask layer has the fourth preset pattern, and based on the fourth preset pattern of the fourth mask layer, the gating element material layer 32a of each second phase change structure 300a is etched from top to bottom along the third direction corresponding to the position of the trench of the first phase change structure 200a, so as to form a gating element, specifically, the gating element 32 has a pillar-shaped structure. Since the etching step of forming the phase change element 31 is separated from the etching step of forming the gate element 32, the size of the phase change element 31 in the first direction and/or the second direction may be smaller than the size of the gate element 32 in the corresponding direction, and the cross-sectional area of the gate element 32 may be larger than the cross-sectional area of the phase change element 31 with a plane perpendicular to the third direction as a cross-section. On the other hand, since the phase change material layer 31a and the gate element material layer 32a are separately etched, cross contamination of the phase change material layer 31a and the gate element material layer 32a can be prevented. In another embodiment, the fourth mask layer may not be formed on the second phase change structure 300a, and the fourth mask plate may be directly used as a mask to perform etching.

Referring to fig. 14, each of the second phase change structures 300a includes a gate element material layer 32a extending in a direction perpendicular to an arrangement direction of the second phase change structures 300a, and for example, the first phase change structures 200a are arranged in the first direction, so that the second phase change structures 300a are also arranged in the first direction, and the second phase change structures 300a include a gate element material layer 32a extending in the second direction.

It will be appreciated that the first mask layer 100a needs to be removed before the third mask layer is provided. The third mask layer needs to be removed before the fourth mask layer is provided.

In one embodiment, the method of manufacturing further comprises:

s310: forming a first electrode, a second electrode, and a third electrode stacked in the third direction; wherein the first electrode is disposed on the phase change material layer; the second electrode is arranged between the phase change material layer and the gating element material layer, and the third electrode is arranged below the gating element material layer;

For example, referring to fig. 7, in an embodiment, the third electrode material layer 35a, the gate element material layer 32a, the second electrode material layer 34a, the phase change material layer 31a, and the first electrode material layer 33a may be sequentially deposited along a third direction. Referring to fig. 8, based on the first predetermined pattern of the first mask layer 100a, the first electrode material layer 33a and the phase change material layer 31a are etched from top to bottom along the third direction to form a plurality of first phase change structure bodies 200a, wherein the first phase change structure bodies 200a extend along a direction perpendicular to the arrangement direction thereof, that is, each of the first phase change structure bodies 200a includes the first electrode material layer 33a and the phase change material layer 31 a.

Referring to fig. 11, based on the third predetermined pattern of the third mask layer, the second electrode material layer 34a, the gate element material layer 32a, and the first electrode material layer 33a are etched from top to bottom along the third direction to form a plurality of second phase change structures 300a, that is, each of the second phase change structures 300a includes the second electrode material layer 34a, the gate element material layer 32a, and the first electrode material layer 33 a.

Based on the second preset pattern of the second mask layer, the first electrode material layer of each first phase change structure body 200a is etched from top to bottom along the third direction to form a first electrode. Referring to fig. 14 and 15, the first electrode 33 is formed in a substantially cylindrical structure.

It will be appreciated that the third masking layer needs to be removed before the second masking layer is provided.

Based on the fourth preset pattern of the fourth mask layer, the second electrode material layer and the third electrode material layer of each second phase change structure 300a are etched from top to bottom along the third direction corresponding to the position of the trench of the first phase change structure 200a, so as to form a second electrode and a third electrode respectively. Referring to fig. 16 to 18, the second electrode 34 and the third electrode 35 are both formed in a substantially cylindrical structure.

Since the etching step for forming the first electrode 33 is separated from the etching step for forming the second electrode 34 and the third electrode 35, the dimension of the first electrode 33 in the first direction and/or the second direction may be smaller than the dimensions of the second electrode 34 and the third electrode 35 in the corresponding directions, and the cross-sectional area of the first electrode 33 is smaller than the cross-sectional areas of the second electrode 34 and the third electrode 35 with respect to a plane perpendicular to the third direction.

In one embodiment, the method of manufacturing further comprises:

s410: forming a first encapsulation layer covering the second conductive line, the first electrode, and a side of the phase change element;

s420: forming a second encapsulation layer covering a surface of the first encapsulation layer, the second electrode, the gating element, the third electrode, and a side of the first conductive line.

In one embodiment, referring to fig. 10, the first phase change structure bodies 200a extend along a direction perpendicular to the arrangement direction thereof, and each of the first phase change structure bodies 200a includes a phase change material layer 31a and a first electrode layer 33 a; for each first phase change structure body 200a, after etching at least one side surface of the phase change material layer 31a in the first phase change structure body 200a along the arrangement direction into a concave arc surface, depositing a first packaging material on the side surface of the second conductive line 20 and around the first phase change structure body 200 a;

after etching the second electrode material layer 34a, the gate element material layer 32a and the first electrode material layer 33a from top to bottom along the third direction to form a plurality of independent second phase change structures 300a, depositing a second packaging material on the surface of the first packaging material and the side surfaces of the second phase change structures 300 a;

etching each first phase change structure 200a from top to bottom along the third direction to form a plurality of grooves in the direction perpendicular to the arrangement direction of each first phase change structure 200a, and then depositing a first packaging material on the side walls of the grooves of the first phase change structures 200a, so that the first packaging material can cover the side surfaces of the second conductive lines 20, the side surfaces of the first electrodes 33 and the side surfaces of the phase change elements 31 to form the first packaging layer 40;

after the second electrode material layer 34a, the gating element material layer 32a, and the third electrode material layer 35a of each second phase change structure 300a are etched from top to bottom along the third direction corresponding to the position of the trench of the first phase change structure 200a to form the second electrode 34, the gating element 32, and the third electrode 35, respectively, the second packaging material covers the surface of the first packaging material deposited on the sidewall of the trench, the side surface corresponding to the second electrode 34, the side surface corresponding to the gating element 32, and the side surface corresponding to the third electrode 35, so as to form the second packaging layer 50.

The structure of the first encapsulation layer 40 may be any one of the structures of the first encapsulation layer 40 provided in the embodiments of the present application, and the detailed structure of the first encapsulation layer 40 is not described herein again. Referring to fig. 11, the structure of the second encapsulation layer 50 may be any structure of the second encapsulation layer 50 provided in the embodiments of the present application, and the detailed structure of the second encapsulation layer 50 is not described herein again.

Referring to fig. 7 and 11, in an embodiment, forming the first conductive line 10 extending along the first direction includes: the first conductive line material layer 10a is deposited before the third electrode 35 is deposited, and the first conductive line material layer 10a is etched from top to bottom along the third direction based on the third predetermined pattern of the third mask layer to form a plurality of independent first conductive lines 10.

In particular, the first conductive line material layer 10a may be deposited on the substrate 1000, the substrate 1000 being used to carry the phase change memory.

Referring to fig. 13, 14 and 15, in an embodiment, forming the second conductive line 20 stacked on the phase change memory cell 30 along the third direction includes: depositing a second conductive line material layer 20a on the deposited first phase change structure 200a, and etching the second conductive line material layer 20a from top to bottom along the third direction based on the second preset pattern of the second mask layer to form a plurality of independent second conductive lines 20.

In one embodiment, the method of manufacturing further comprises:

s100: sequentially and alternately arranging a first conductive layer and a second conductive layer along the third direction, wherein a plurality of first conductive lines are arranged in parallel on the same plane to form the first conductive layer, and a plurality of second guide lines are arranged in parallel on the same plane to form the second conductive layer;

s200: and arranging the phase change memory cell between the adjacent first conductive layer and the second conductive layer.

Referring to fig. 5, in an embodiment, a first conductive line material layer 10a is formed on a substrate 1000, and the first conductive line material layer 10a is etched from top to bottom along a third direction to form a plurality of independent first conductive lines 10, such that a lower first conductive layer is formed in a plane of the substrate 1000, a plurality of phase change memory cells 30 stacked on the lower first conductive layer along the third direction are formed according to a manufacturing method provided in any embodiment of the present application, and each phase change memory cell 30 may include a third electrode 35, a gate element 32, a second electrode 34, a phase change element 31, and a first electrode 33 sequentially stacked from bottom to top along the third direction; the second conductive line material layer 20a is stacked on the phase change memory cell 30, the second conductive line material layer 20a is etched from top to bottom along the third direction to form a plurality of second conductive lines 20 respectively, so as to form a lower second conductive layer, the manufacturing method according to any embodiment of the present application forms a plurality of phase change memory cells 30 stacked on the lower second conductive layer along the third direction, and an upper first conductive layer is stacked on the plurality of phase change memory cells 30 along the third direction, so that a two-layer stacked structure is formed, so that the phase change memory can have more phase change memory cells 30 in a limited space, and particularly, the phase change memory is a three-dimensional cross-point (3D-Xpoint) phase change memory, thereby improving the storage capacity of the phase change memory. In some embodiments, a plurality of phase change memory cells 30 and an upper second conductive layer may be sequentially stacked from bottom to top along a third direction on the upper first conductive layer to form a three-layer stacked structure. The phase change memory provided in the embodiments of the present application includes, but is not limited to, a four-layer stacked structure, a five-layer stacked structure, or a six-layer stacked structure, and the like, and a person skilled in the art can implement a three-dimensional stacked structure with two or more layers according to the technical solution disclosed in the present application, and details thereof are not repeated herein.

In the embodiments of the present application, if not specifically indicated, the Deposition process includes, but is not limited to, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or the like; the etching process includes, but is not limited to, dry etching or wet etching, etc.

Referring to fig. 19, another aspect of the present application further provides a reading method for a phase change memory in any one of the above embodiments, where the phase change memory has N resistance states, and the N resistance states respectively correspond to a 1 st threshold voltage, a 2 nd threshold voltage, and an nth threshold voltage, where N is a positive integer greater than or equal to 3, and the method includes:

s1100: applying an Mth reading voltage to the phase change memory to obtain a corresponding Mth reading result, wherein the Mth reading voltage is greater than the Mth threshold voltage and less than the Mth +1 threshold voltage, and M is a positive integer less than or equal to N-1;

s1200: and comparing the Mth reading result with a corresponding preset value, and determining the resistance state of the phase change memory according to the comparison result.

The phase change memory is provided with N resistance states, each resistance state corresponds to one threshold voltage, and a corresponding reading voltage is set between two adjacent threshold voltages so as to divide N-1 reading areas.

The read result includes, but is not limited to, a read voltage or a read current.

In one embodiment, if M is equal to 1 and the comparison result is that the 1 st read result is greater than the corresponding preset value, the phase change memory is determined to be in the 1 st resistance state;

Therefore, whether the phase change memory is in the 1 st resistance state or not can be judged quickly and accurately.

In one embodiment, if M is equal to N-1 and the comparison result is that the N-1 reading result is smaller than the corresponding preset value, the phase change memory is determined to be in the N resistance state;

Therefore, whether the phase change memory is in the Nth resistance state or not can be judged quickly and accurately.

In one embodiment, corresponding to M being greater than 1 and less than N-1, and the comparison result being that the Mth reading result is greater than a corresponding preset value, an M-1 th reading voltage is applied to the phase change memory, the M-1 th reading voltage being greater than an M-1 th threshold voltage and less than the Mth threshold voltage, and a corresponding M-1 th reading result is obtained; if the corresponding M-1 reading result is smaller than the corresponding preset value, determining that the phase change memory is in the M resistance state; if the M-1 reading result is larger than the corresponding preset value, determining that the resistance state of the phase change memory is lower than the M resistance state;

Therefore, the phase change memory can be rapidly and accurately judged to be in any resistance state from the 1 st resistance state to the N resistance state.

For example, the phase change memory has 4 resistance states, where the 4 resistance states respectively correspond to a 1 st threshold voltage, a 2 nd threshold voltage, a 3 rd threshold voltage, and a 4 th threshold voltage that are sequentially increased in 4 numbers, please refer to fig. 3 and 4, in fig. 4, Vr1 is the 1 st read voltage, Vr2 is the 2 nd read voltage, Vr3 is the 3 rd read voltage, Vth, s1 is the 1 st threshold voltage, Vth, s2 is the 2 nd threshold voltage, Vth, s3 is the 3 rd threshold voltage, Vth, s4 is the 4 th threshold voltage, an abscissa Vcell is a programming voltage of the phase change memory according to the embodiment of the present application, and an ordinate Icell is a corresponding programming current;

in one embodiment, the reading method includes: a 2 nd reading voltage can be applied to the phase change memory to obtain a corresponding 2 nd reading result, wherein the 2 nd reading voltage is greater than a 2 nd threshold voltage and less than a 3 rd threshold voltage;

if the 2 nd reading result is larger than the corresponding preset value, continuing to apply the 1 st reading voltage to the phase change memory to obtain a corresponding 1 st reading result;

and if the 1 st reading result is larger than the corresponding preset value, the phase change memory is in the 1 st resistance state, and the reading process is ended.

And if the 1 st reading result is smaller than the corresponding preset value, the phase change memory is in the 2 nd resistance state, and the reading process is ended.

If the 2 nd reading result is smaller than the corresponding preset value, continuing to apply a 3 rd reading voltage to the phase change memory to obtain a corresponding 3 rd reading result;

and if the 3 rd reading result is larger than the corresponding preset value, the phase change memory is in a 3 rd resistance state, and the reading process is ended.

And if the 3 rd reading result is smaller than the corresponding preset value, the phase change memory is in a 4 th resistance state, and the reading process is ended.

In another embodiment, the reading method includes: a 1 st reading voltage can be applied to the phase change memory to obtain a corresponding 1 st reading result, wherein the 1 st reading voltage is greater than a 1 st threshold voltage and less than a 2 nd threshold voltage;

If the 1 st reading result is smaller than the corresponding preset value, the resistance state of the phase change memory is higher than the 1 st resistance state, the read voltage higher than the 1 st read voltage can be continuously applied to the phase change memory, for example, the 2 nd read voltage is sequentially applied to the phase change memory, and in the applying process:

if the 2 nd reading result is larger than the corresponding preset value, determining that the phase change memory is in the 2 nd resistance state, and ending the reading process;

if the 2 nd reading result is smaller than the corresponding preset value, continuing to apply the 3 rd reading voltage, and if the reading result corresponding to the 3 rd reading result is larger than the corresponding preset value, determining that the phase change memory is in a 3 rd resistance state, and ending the reading process;

and if the 3 rd reading result is smaller than the corresponding preset value, determining that the phase change memory is in a 4 th resistance state, and ending the reading process.

It is understood that, in another embodiment, the 3 rd read voltage may be applied to the phase change memory at the beginning, the resistance state of the phase change memory is determined according to the read method provided in the embodiment of the present application, and the read process is ended if the resistance state of the phase change memory can be determined.

The above is only an example of the reading method provided in the embodiment of the present application, and the reading method provided in the embodiment of the present application is not limited.

The embodiment of the present application further provides an integrated circuit, which includes at least one phase change memory in any embodiment of the present application. The embodiment of the present application further provides a terminal, where the terminal includes at least one phase change memory in any embodiment of the present application. The terminal in the embodiment of the application can be a mobile terminal or a fixed terminal, wherein the mobile terminal includes but is not limited to a mobile phone, a tablet computer or a notebook computer; fixed terminals include, but are not limited to, desktop computers. The method can be applied to any device capable of running a computer program and capable of displaying. The integrated circuit and the terminal described in any of the embodiments provided in the present application have the same advantageous effects as the phase change memory according to any of the embodiments in the present application.

The above description is only exemplary of the present application and should not be taken as limiting the scope of the present application, as any modifications, equivalents, improvements, etc. made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A phase change memory, comprising:

taking a plane perpendicular to the third direction as a cross section, wherein the area of any end face of the phase change element along the third direction is larger than the cross section area of at least one position between the two end faces of the phase change element along the third direction;

the phase change memory cell further includes a gating element stacked with the phase change element in the third direction; the size of the phase change element in the first direction and/or the second direction is smaller than the size of the gating element in the corresponding direction.

2. The phase-change memory according to claim 1, wherein a cross-sectional area of the phase-change element is gradually reduced from both ends to the middle with respect to a plane perpendicular to the third direction.

3. The phase change memory according to claim 1, wherein at least one side surface of the phase change element connecting the two end surfaces is a concave arc surface.

4. The phase change memory according to claim 3, wherein all side surfaces of the phase change element connecting the two end surfaces are formed together as a single-sheet hyperboloid.

5. The phase-change memory according to claim 1, wherein the phase-change memory cell further comprises a first electrode, a second electrode, and a third electrode stacked in the third direction; wherein the first electrode is disposed between the phase change element and the second conductive line; the second electrode is disposed between the phase change element and the gate element, and the third electrode is disposed between the gate element and the first conductive line;

6. The phase change memory according to claim 5, further comprising a first encapsulation layer covering the second conductive line, the first electrode, and a side of the phase change element, and a second encapsulation layer covering a surface of the first encapsulation layer, the second electrode, the gate element, the third electrode, and a side of the first conductive line.

7. The phase change memory according to any one of claims 1 to 6, wherein the number of the first conductive lines is plural, the number of the second conductive lines is plural, the number of the phase change memory cells is plural, the plurality of first conductive lines are arranged at intervals along the second direction, the plurality of second conductive lines are arranged at intervals along the first direction, and the phase change memory cell is arranged at an intersection of each of the first conductive lines and the second conductive lines.

8. The phase change memory according to any one of claims 1 to 6, wherein the number of the first conductive lines is plural, the number of the second conductive lines is plural, the number of the phase change memory cells is plural, the plural first conductive lines are arranged in parallel in the same plane to form a first conductive layer, the plural second conductive lines are arranged in parallel in the same plane to form a second conductive layer, the first conductive layers and the second conductive layers are alternately arranged in the third direction, and the plural phase change memory cells are arranged between the adjacent first conductive layers and the second conductive layers.

9. A method of manufacturing a phase change memory, comprising:

forming a first conductive line extending in a first direction;

forming a phase change memory cell stacked on the first conductive line in a third direction, the phase change memory cell including a phase change element having a cross section taken in a plane perpendicular to the third direction, an area of either end surface of the phase change element in the third direction being larger than a cross-sectional area of the phase change element at least at one position between both end surfaces of the phase change element in the third direction; the phase change memory cell further includes a gating element stacked with the phase change element in the third direction; wherein a dimension of the phase change element in a first direction and/or a second direction is smaller than a dimension of the gate element in a corresponding direction;

forming a second conductive line overlying the phase change memory cell in the third direction, the second conductive line extending in the second direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

10. The method of manufacturing according to claim 9, wherein the forming the phase-change memory cell stacked on the first conductive line in the third direction comprises:

depositing a phase change material layer along the third direction;

11. The manufacturing method according to claim 10, wherein the phase change material layer is etched on all sides in the first direction and the second direction to be formed into a single-sheet hyperboloid.

12. The manufacturing method according to claim 10, wherein the method of etching at least one side surface of the phase change material layer in the first phase change structure body in the arrangement direction into a concave arc surface comprises dry etching or wet etching.

13. The manufacturing method according to claim 10, wherein the etching material for etching at least one side surface of the phase change material layer in the first phase change structure along the arrangement direction into a concave arc surface comprises ammonia water and/or hydrogen peroxide.

14. The method of manufacturing of claim 10, wherein the forming of the phase change memory cell stacked on the first conductive line in a third direction further comprises:

after forming the phase change material layer into the phase change element, etching the gating element material layer in the third direction from top to bottom to form the gating element.

15. The manufacturing method according to claim 14, further comprising:

16. The manufacturing method according to claim 15, further comprising:

17. The manufacturing method according to any one of claims 9 to 16, characterized by further comprising:

18. A reading method for the phase change memory according to any one of claims 1 to 8, wherein the phase change memory has N resistance states, and the N resistance states respectively correspond to a 1 st threshold voltage, a 2 nd threshold voltage and an nth threshold voltage which are sequentially increased in number by N, where N is a positive integer greater than or equal to 3, and the method includes:

19. The reading method according to claim 18,

if M is equal to 1 and the comparison result is that the 1 st reading result is greater than the corresponding preset value, determining that the phase change memory is in the 1 st resistance state;

20. The reading method according to claim 18,

if the comparison result is that the N-1 reading result is smaller than the corresponding preset value, determining that the phase change memory is in the N resistance state;

21. The reading method according to claim 18,

applying an M-1 reading voltage to the phase change memory corresponding to the condition that M is larger than 1 and smaller than N-1 and the comparison result is that the Mth reading result is larger than a corresponding preset value, wherein the M-1 reading voltage is larger than the M-1 threshold voltage and smaller than the Mth threshold voltage, and acquiring a corresponding M-1 reading result; if the corresponding M-1 reading result is smaller than the corresponding preset value, determining that the phase change memory is in the M resistance state; if the M-1 reading result is larger than the corresponding preset value, determining that the resistance state of the phase change memory is lower than the M resistance state;