EP2891182B1 - Three dimensional memory array architecture - Google Patents

Three dimensional memory array architecture Download PDF

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Publication number
EP2891182B1
EP2891182B1 EP13833302.6A EP13833302A EP2891182B1 EP 2891182 B1 EP2891182 B1 EP 2891182B1 EP 13833302 A EP13833302 A EP 13833302A EP 2891182 B1 EP2891182 B1 EP 2891182B1
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material
conductive
conductive lines
plurality
lines
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German (de)
French (fr)
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EP2891182A1 (en
EP2891182A4 (en
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Federico Pio
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Micron Technology Inc
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Micron Technology Inc
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Priority to US13/600,699 priority Critical patent/US8841649B2/en
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Priority to PCT/US2013/057657 priority patent/WO2014036480A1/en
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    • HELECTRICITY
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    • H01L27/2409Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes
    • H01L27/2427Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes of the Ovonic threshold switching type
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    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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    • H01L27/22Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
    • H01L27/222Magnetic non-volatile memory structures, e.g. MRAM
    • H01L27/224Magnetic non-volatile memory structures, e.g. MRAM comprising two-terminal components, e.g. diodes, MIM elements
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    • H01L27/2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
    • H01L27/2481Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout
    • H01L27/249Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout the switching components being connected to a common vertical conductor
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1666Patterning of the switching material
    • H01L45/1683Patterning of the switching material by filling of openings, e.g. damascene method
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    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/06Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1226Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/1253Electrodes
    • H01L45/126Electrodes adapted for resistive heating
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H01L45/144Tellurides, e.g. GeSbTe

Description

    Technical Field
  • The present disclosure relates generally to semiconductor devices, and more particularly to three dimensional memory array architectures and methods of forming same.
  • Background
  • Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistance variable memory, and flash memory, among others. Types of resistance variable memory include phase change material (PCM) memory, programmable conductor memory, and resistive random access memory (RRAM), among others.
  • Memory devices are utilized as non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and data retention without power. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices.
  • Constant challenges related to memory device fabrication are to decrease the size of a memory device, increase the storage density of a memory device, and/or limit memory device cost. Some memory devices include memory cells arranged in a two dimensional array, in which memory cells are all arranged in a same plane. In contrast, various memory devices include memory cells arranged into a three dimensional (3D) array having multiple levels of memory cells.
  • Three-dimensional memory arrays are described in the references discussed below.
  • United States Patent Application Publication No. US 2011/272663 A1 to An et al., describes a nonvolatile three-dimensional memory device that includes a conductive pillar which extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer.
  • Japanese Patent Application Publication No. JP 2011 253941 A describes a three-dimensional memory device comprising a substrate including peripheral circuits, and a chain cell constructed on the substrate. The chain cell includes a chain memory cell group in which a plurality of memory cells each having a transistor and a recording material connected in parallel are connected in a thickness direction of the substrate in series, and a polysilicon diode connected in series with the chain memory cell group and functioning as a selection element of the chain memory cell group. The recording material is formed such that three kinds of phase change materials having resistant values different from each other are coaxially stacked.
  • United States Patent Application Publication No. US 2010/270529 A1 to Hsiang-Lan describes a three-dimensional phase change memory device that is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable phase change memory element and a threshold switching element. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension.
  • United States Patent Application Publication No. US 2010/0276743 A1 to Kuniya describes a method of manufacturing a three-dimensional flash memory array by first alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. A through hole extending in the lamination direction is formed in the laminated body. A selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. A high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole.
  • The three dimensional memory array which is disclosed by the above reference comprises: a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material; at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension passes through a portion of each of the plurality of first conductive lines; a plurality of second conductive lines wherein each second conductive line of the plurality of second conductive lines is formed over the plurality of first conductive lines and the at least one conductive extension, and wherein the at least one conductive extension is coupled to a respective one of the plurality of second conductive lines; storage element material formed around the at least one conductive extension; and cell select material formed around the at least one conductive extension.
  • Summary of the Invention
  • The present invention is defined in the appended independent claims 1 and 8 to which reference should be made. Advantageous features are set out in the appended dependent claims.
  • Brief Description of the Drawings
    • Figure 1 illustrates a prior art two dimensional memory array.
    • Figure 2 illustrates a prior art three dimensional memory array.
    • Figure 3 illustrates a three dimensional memory array.
    • Figure 4 illustrates a method for biasing of a three dimensional memory array.
    • Figure 5 illustrates concentric memory cells located within a plurality of conductive.
    • Figure 6A illustrates location of concentric memory cells within a grid of conductive.
    • Figure 6B illustrates location of concentric memory cells partially within a grid of conductive.
    • Figure 6C illustrates location of concentric memory cells having concentric heater material within a grid of conductive lines in accordance with a number of embodiments of the present disclosure.
    • Figure 6D illustrates location of concentric memory cells having concentric heater material partially within a grid of conductive lines in accordance with a number of embodiments of the present disclosure.
    • Figures 7A-C illustrate a simplified process flow for forming a three dimensional memory array of concentric memory cells.
    • Figures 8A-C illustrate a simplified process flow for forming a three dimensional memory array of concentric memory cells.
    • Figures 9A-D illustrate a simplified process flow for forming a three dimensional memory array of concentric memory cells having heater material in accordance with a number of embodiments of the present disclosure.
    Detailed Description
  • Three dimension (3D) memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.
  • Examples of the present disclosure implement a vertical integration of phase change material (PCM) memory cell. The disclosed three dimensional memory array is denser than conventional two dimensional memory arrays. Furthermore, the fabrication process can be less complex and less expensive than other approaches, e.g., by reducing a mask count associated with forming a 3D array, to fabricating three dimensional memory array architectures in that a quantity of mask count is reduced. Therefore, the fabrication process of the present disclosure can be less expensive than that of previous approaches.
  • The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 102 may reference element "02" in Figure 1, and a similar element may be referenced as 202 in Figure 2. Also, as used herein, "a number of' a particular element and/or feature can refer to one or more of such elements and/or features.
  • As used herein, the term "substantially" intends that the modified characteristic needs not be absolute, but is close enough so as to achieve the advantages of the characteristic. For example, "substantially parallel" is not limited to absolute parallelism, and can include orientations that are at least closer to a parallel orientation than a perpendicular orientation. Similarly, "substantially orthogonal" is not limited to absolute orthogonalism, and can include orientations that are at least closer to a perpendicular orientation than a parallel orientation.
  • Figure 1 illustrates a prior art two dimensional memory array 100. Various memory devices can include a memory array 100. The memory array 100 can include a plurality of word lines 102, and a number of bit lines 104. The word lines 102 are arranged substantially parallel one another at one level, and the bit lines 104 are arranged substantially parallel one another at a different level. The word lines 102 and bit lines 104 are further arranged substantially perpendicular, e.g., orthogonal, to one another. The indices shown for each word line 102 and bit line 104 indicate the ordering of the respective lines within a particular level.
  • In such architectures, the memory cells 106 can be arranged in a matrix of rows and columns. The memory cells 106 can be located at the crossings of the word lines 102 and the bit lines 104. That is, the memory cells 106 are arranged in a cross point architecture. The memory cells 106 are located where word lines 102 and the bit lines 104 pass near one another, e.g., cross, overlap, etc. The word lines 102 and the bit lines 104 do not intersect one another since the word lines 102 and the bit lines 104 are formed at different levels.
  • Figure 2 illustrates a prior art three dimensional memory array 208. The memory array 208 can include a plurality of word lines 210, 212, and a number of bit lines 214. Word lines 210 are arranged substantially parallel one another at one level and word lines 212 are arranged substantially parallel one another at a different level. As shown in Figure 2, bit lines 214 are arranged substantially parallel one another at a level different than either of the levels at which word lines 210 and 212 are located, e.g., between the levels at which word lines 210 and 212 are located. The bit lines 214 are further arranged substantially perpendicular, e.g., orthogonal, to word lines 210, 212.
  • Memory cells 216, 218 are shown in Figure 2 arranged in a cross point architecture at the crossings of the word lines 210, 212 and the bit lines 214. Memory cells 216 are arranged between word lines 210 and bit lines 214, and memory cells 218 are arranged between word lines 212 and bit lines 214. As such, the memory cells are arranged in multiple levels, each level having memory cells organized in a cross point architecture. The levels are formed at different levels from one another, thereby being vertically stacked. Memory cells are formed at levels between levels at which word lines 212 and bit lines 214 are formed.
  • The three dimensional memory array 208 shown in Figure 2 includes memory cells 216, 218 having a common a bit line 214, but separate word lines 210, 212. That is, compared to memory array 100 shown in Figure 1, the additional level of memory cells in the memory array 208 necessitates addition of another level of word lines, e.g., word lines 212 above memory cells 218. Bit line 214 is common to those memory cells, 216 and 218, that are located vertically adjacent the bit line 214, e.g., directly above and directly below bit line 214. Such adjacency limits bit line 214 being common to at most two memory cells. More generally, a three dimensional memory array may have more stacked levels, e.g., configured as shown in Figure 2, than are shown in Figure 2. However, the addition of more levels of memory cells, such as by stacking a plurality of memory arrays 208 atop one another, necessitates defining additional word lines for each additional level of memory cells, and defining additional bit lines for each new level (or at most, pair of levels) of additional memory cells.
  • The indices shown for each word line 210, 212 indicate the level and the ordering of the word lines within a particular level. For example, word line 210 (WL3,0) is shown being located at position 3 within level 0, and word line 212 (WL3,1) is shown being located at position 3 within level 1. As such, memory cell 216 is shown in Figure 2 being located between bit line 214, i.e., BL0, and the word line below bit line 214, i.e., WL2,0, and memory cell 218 is shown in Figure 2 being located between bit line 214, i.e., BL0, and the word line above bit line 214, i.e., WL2,1.
  • Figure 3 illustrates a three dimensional memory array 320. In a number of examples, access lines, which may be referred to as word lines (WLs), are disposed on a plurality of levels, e.g., elevations, decks, planes. For example, word lines can be disposed on N levels. Insulation material, e.g., dielectric material, separates the levels of word lines. As such, the levels of word lines separated by insulation material form a stack of WL/insulation materials. Data lines, which may be referred to as bit lines (BLs), are arranged substantially perpendicular to the word lines, and located at a level above the N levels of word lines, e.g., at the N+1 level. Each bit line can have a number of conductive extensions, e.g., vertical extensions, in proximity to the word lines, with a memory cell formed between the vertical extension and the word line.
  • The memory array 320 can include a plurality of conductive lines 322, e.g., access lines, which may be referred to herein as word lines, and conductive lines 324, e.g., data lines, which may be referred to herein as bit lines. Word lines 322 can be arranged into a number of levels. Word lines 322 are shown being arranged into four levels in Figure 3. However, the quantity of levels into which the word lines 322 can be arranged are not limited to this quantity, and word line 322 can be arranged into more, or fewer, levels. Word lines 322 are arranged substantially parallel one another within a particular level. The word lines 322 can be aligned vertically in a stack. That is, word lines 322 in each of the multiple levels can be located at a same relative location within each level so as to be aligned with word lines 322 directly above and/or below. Insulation material (not shown in Figure 3) can be located between the levels at which word lines 322 are formed and between word lines 322 at a particular level.
  • As shown in Figure 3, bit lines 324 can be arranged substantially parallel one another at a level different than the levels at which word lines 322 are located, e.g., above the levels at which word lines 322 are located. That is, the bit lines can be located at the top of the memory array 320. The bit lines 324 can be further arranged substantially perpendicular, e.g., orthogonal, to word lines 322 so as to have overlappings, e.g., crossings at different levels, therebetween. However, examples are not limited to a strictly parallel/orthogonal configuration.
  • The indices shown for each word line 322 in Figure 3 indicate the position, e.g., ordering, of the word lines within a particular level and the level. For example, word line WL2,0 is shown being located at position 2 within level 0 (a word line at the bottom of a stack of word lines located at position 2), and word line WL2,3 is shown being located at position 2 within level 3 (a word line at the top of a stack of word lines located at position 2). The quantity of levels into which the word lines 322 can be arranged, and the quantity of word lines 322 at each level can be more, or fewer, than the quantities shown in Figure 3.
  • At each overlapping of a bit line 324 and a stack of word lines 322, a conductive extension 326 of the bit line 324 is oriented substantially perpendicular to the bit line 324 and the word lines 322, so as to intersect a portion of each word line 322 in the stack of word lines. For example, the conductive extension 326 of the bit line 324 can be arranged to extend vertically from the bit line 324 to intersect a portion the respective word lines 322 therebelow, as shown in Figure 3. As shown, the conductive extension 326 can pass through a word line 322, so as to be surrounded entirely by the word line 322. According to a number of examples, the conductive extension 326 can pass near the word line 322, e.g., adjacent, such that a memory cell can be formed between the conductive extension 326 and the word line 322.
  • Memory cells 328 are shown in Figure 3 arranged in a cross point architecture near the location of where the conductive extension 326 of a bit line 324 and the word lines 322 are in proximity to one another at different levels. In a number of examples, the memory cells 328 are located between the conductive extension 326 and the word lines 322. For example, where a conductive extension 326 passes through a portion of a word line 322, a memory cell 328 can be located between the conductive extension 326 and the word line 322.
  • As such, the memory cells 328 can be arranged in multiple levels, each level having memory cells organized in a cross point architecture. The levels of memory cells 328 can be formed at different levels from one another, thereby being vertically stacked. The three dimensional memory array 320 shown in Figure 3 can include memory cells 328 having a common a bit line 324, but separate word lines 322. Although four levels of word lines 322 (and four corresponding levels of memory cells 328) are shown in Figure 3, examples of the present disclosure are not so limited and can include more, or fewer, levels of word lines 322 (and corresponding levels of memory cells 328). Memory cells may be formed substantially at the same levels as word lines are formed.
  • According to a number of examples of the present disclosure, the memory cells 328 can be a resistance variable memory cell. For example, the memory cell 328 can include a phase change material (PCM), e.g., chalcogenide. Each memory cells 328 can also include a switch, e.g., a MOS transistor, a BJT, a diode, an ovonic threshold switch (OTS), among other types of switches. An OTS can comprise chalcogenide material, such as a chalcogenide material different than that used for the memory element.
  • According to examples, a memory cell 328 can include a storage element connected in series with a respective cell select device, e.g., cell access device, each formed concentrically around the conductive extension 326 as explained in further detail with respect to Figure 5 below. A number of examples include a three dimension memory array of phase change material (PCM) and switch memory cells, which can be referred to as a 3D PCMS array. For simplicity, Figure 3 shows a memory cell 328 located at an intersection of an extension 326 and a word line 322. However, examples of the present disclosure are not so limited and a memory cell 328 can be located near a crossing of an extension 326 and a word line 322.
  • Figure 4 illustrates a method for biasing of a three dimensional memory array in accordance with a number of examples of the present disclosure. Figure 4 shows a memory array 430, which can be a portion of memory array 320 described with respect to Figure 3. The memory array 430 can include a plurality of word lines 422, orthogonally-oriented bit lines 424, and conductive extensions 436 coupled to and arranged to extend vertically down from the bit lines 424, perpendicular to both the word lines 422 and bit lines 424.
  • To access, e.g., program or read, memory array 430, a balanced biasing scheme is adopted. The addressed word line 422, i.e., word lines at the addressed position on the addressed level, and the addressed bit line are biased so that the voltage difference across them exceeds the threshold voltage of the respective cell select device. Unaddressed word lines 422 and unaddressed bit lines 424 are biased so that the voltage difference across any other pair of addressed and/or unaddressed word lines 422 and bit lines 424, does not exceed the threshold voltage of the respective cell select device. For example, all other word lines 422 (including different word lines 422 located in a same level and word lines 422 located at different levels) and other bit lines 424 can be biased at an intermediate voltage, e.g., a reference voltage (VREF) such as a mid-point voltage between addressed bit line and word line voltages.
  • The addressed bit line 424 is shown in Figure 4 as BLADDR, and the unaddressed bit line 424 is shown as BLNOTADDR. The indices shown for each word line 422 in Figure 4 correspond to the position of the word lines within a particular level and the level. The word lines 422 shown in Figure 4 are annotated with ADDR for an addressed level or position within a level, and NOTADDR for an unaddressed level or different word line position within a level. Therefore, the addressed word line 422 is shown in Figure 4 as WLADDR, ADDR. Unaddressed word lines 422 shown in Figure 4 as one of WLNOTADDR, NOTADDR, WLNOTADDR, ADDR, or WLADDR, NOTADDR, to indicate that the unaddressed word line 422 is located at a position and/or a level that is not addressed.
  • According to a number of examples, the unaddressed word lines 422 and unaddressed bit lines 424 can be biased to an intermediate voltage to reduce the maximum voltage drop with respect to either the addressed word line 422 or the addressed bit line 424. For example, the intermediate voltage can be chosen to be at a mid-point between the unaddressed word lines 422 and unaddressed bit lines. However, the intermediate voltage can be selected to be different than a mid-point voltage to minimize the disturb on the word lines 422 and bit lines 424.
  • Figure 4 shows memory cell 442 between the addressed word line 422 and the addressed bit line 424 fully shaded to indicate the voltage difference across memory cell 442 exceeding the threshold voltage, V, of the associated cell select device. Figure 4 shows undisturbed memory cells 438 between unaddressed word lines 422 and unaddressed bit lines 424 without any shading to indicate the voltage difference across memory cell 438 is insignificant, e.g., null, zero. Figure 4 also shows disturbed memory cells 440 between unaddressed word lines 422 and the addressed bit line 424, and disturbed memory cell 441 between the addressed word line 422 and the unaddressed bit lines 424, as being partially shaded to indicate the voltage difference thereacross is some intermediate voltage that is less than the threshold voltage of the respective cell select device, e.g., V/2. It can be beneficial to bias unaddressed word lines 422 and unaddressed bit lines 424 to a same voltage.
  • The memory array structure has some similarities to three dimensional vertical channel NAND memories. However, accessing a memory cell involves passing current (which also flows in the addressed bit line 424 and/or addressed word line 422) through the memory cell, e.g., a resistance variable memory cell. The balanced biasing scheme of the present disclosure allows a voltage drop above threshold to be obtained only on an addressed cell, i.e., on addressed word line, level, and bit line, while only disturbing cells along the addressed word line and bit line, at not-addressed bit lines and word lines, respectively, e.g., at most a minimum leakage current flows through the not addressed cells.
  • Figure 5 illustrates concentric memory cells located within a plurality of conductive lines.
  • Within this disclosure, "concentric" refers to structures substantially surrounding each other, and is not limited to exactly or quasi-exactly circular shapes or footprints, e.g., oval, square, or rectangular concentric memory cells may be formed. Figure 5 shows a portion of a memory array, such as memory array 320 illustrated in Figure 3. Figure 5 shows a stack 544 comprising a plurality of conductive lines 522, e.g., word lines, at a number of levels separated from one another by at least an insulation material (not shown but located between conductive lines 522 at 548). A conductive extension 554 is arranged to extend perpendicular to the plurality of conductive lines 522. The conductive extension 554 is communicatively coupled at one end to a bit line (not shown in Figure 5).
  • Figure 5 shows the conductive extension 554 passing through each of the conductive lines 522 such that a cross section of the conductive extension 554 is completely surrounded by a respective conductive line 522. However, the
    conductive extension 554 can be arranged so as to intersect a portion of a respective conductive line 522 such that the conductive extension 554 is not completely surrounded by the conductive line 522, which is described further with respect to Figure 6B. The conductive extension 554 may pass in proximity to a respective conductive line 522 rather than through it.
  • Figure 5 further shows storage element material 552, e.g., phase change material (PCM), and cell select device material 550, e.g., ovonic threshold switch (OTS) material, concentrically arranged around the conductive extension 554. Although Figure 5 shows the PCM 552 is arranged adjacent to the conductive extension 554, and the OTS material 550 is arranged concentric to the PCM 552, in an alternative arrangement, the OTS material 550 may be arranged adjacent to the conductive extension 554, and the PCM 552 may be arranged concentric to the OTS material 550.
  • Although not shown in Figure 5 for clarity, additional materials may be concentrically formed between the conductive extension 554 and a respective conductive line 522, such as a heater material discussed further with respect to Figure 6C. Another example is a material formed between the storage element material 552 and the cell select device material 550 to separate and/or provide protection between the storage element material 552 and the cell select device material 550, to mitigate composition mixing, for instance.
  • Where the conductive extension 554, concentric PCM 552, and concentric OTS material 550 passes in proximity to a respective conductive line 522, a concentric memory cell, including a storage element connected in series with a respective cell select device, is formed between the conductive extension 554 and the conductive line 522. Concentric memory cells may be formed substantially at the same levels as word lines are formed, such that a concentric memory cell is substantially co-planar with a conductive line 522.
  • The storage element can be a resistance variable storage element. The resistance variable storage element may include a PCM, for instance, among other resistance variable storage element materials. In examples in which the resistance variable storage element comprises a PCM, the phase change material can be a chalcogenide alloy such as an indium(In)-antimony(Sb)-tellurium(Te) (IST) material, e.g., In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc., or a germanium(Ge)-antimony(Sb)-tellurium(Te) (GST) material, e.g., Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, or etc., among other phase change materials. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. Other phase change materials can include Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn-Pt, for example. Other examples of resistance variable materials include transition metal oxide materials or alloys including two or more metals, e.g., transition metals, alkaline earth metals, and/or rare earth metals. Examples are not limited to a particular resistive variable material or materials associated with the storage elements of the memory cells. For instance, other examples of resistive variable materials that can be used to form storage elements include binary metal oxide materials, colossal magnetoresistive materials, and/or various polymer based resistance variable materials, among others.
  • The memory cells comprising a cell select device in series with a phase change material, can be referred to as phase change material and switch (PCMS) memory cells. In a number of examples, the concentrically arranged cell select device functions as a two-terminal OTS, for instance. The OTS material can include, for example, a chalcogenide material that is responsive to an applied voltage across the OTS. For an applied voltage that is less than a threshold voltage, the OTS remains in an "off' state, e.g., an electrically nonconductive state. Alternatively, responsive to an applied voltage across the OTS that is greater than the threshold voltage, the OTS enters an "on" state, e.g., an electrically conductive state. Responsive to an applied voltage near a threshold voltage, the voltage across the OTS may "snapback" to a holding voltage.
  • The concentrically-formed storage element can function as two-terminal phase change storage element. Examples herein are not limited to PCMS cross-point arrays or a particular cell select switch. For instance, the methods and apparatuses of the present disclosure can be applied to other cross-point arrays such as arrays utilizing resistive random access memory (RRAM) cells, conductive bridging random access memory (CBRAM) cells, and/or spin transfer torque random access memory (STT-RAM) cells, among other types of memory cells, for example.
  • The resistance variable storage element material can comprise one or more of the same material(s) as the cell select device material. However, the resistance variable storage element material and the cell select device material can comprise different materials.
  • The materials described herein may be formed by various thin film techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD) such as low pressure CVD, plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), thermal decomposition, and/or thermal growth, among others. Alternatively, materials may be grown in situ. While the materials described and illustrated herein may be formed as layers, the materials are not limited thereto and may be formed in other three-dimensional configurations. Fabrication techniques are discussed further with respect to Figure 7A - 9C.
  • Figure 6A illustrates location of concentric memory cells within a grid of conductive lines in accordance with a number of embodiments of the present disclosure. Figure 6A shows a top view of a portion of a memory array 656. The memory array 656 includes a plurality of first conductive lines 622, e.g., word lines, and a plurality of second conductive lines 624, e.g., bit lines, arranged perpendicular to the first conductive lines 622.
  • For example, the first conductive lines 622 and second conductive lines 624 can be formed of a metallic material, a polysilicon material, e.g., doped polysilicon material, among others. Other levels of first conductive lines 622, e.g., other levels of word lines, can be present below the word lines in level j shown in Figure 6A. The first conductive lines 622 and second conductive lines 624 overlap and thereby form a grid of conductive lines.
  • The first conductive lines 622 at a number of elevations can be formed, for example, by patterning a first stack alternating conductive materials and insulating materials into a number of discrete stacks. That is, the alternating conductive materials and insulating materials can be etched to form trenches (laterally) between a number of stacks of conducting/insulating materials defining a footprint of first conductive lines. The trenches between the number of stacks so formed can be filled with insulating materials, e.g., dielectric, in order to separate first conductive lines at a particular elevation from one another.
  • Each stack can comprise a plurality of first conductive lines 622 (vertically) separated from one another by insulating material, and (laterally) separated from other first conductive lines 622, e.g., in other stacks, by the insulating material used to fill the trenches. A profile view of one such stack is shown, for example, with respect to Figure 7A, among others.
  • Second conductive lines 624 can be similarly formed by patterning, etching, and forming insulating materials between respective second conductive lines. However, as second conductive lines may be formed at only one elevation (at a time), so that such formation may not involve a stack of alternating conductive and insulating materials. As used herein, a "footprint" of a conductive line refers to the outline of a particular conductive line when formed, e.g., the outline of a stack comprising first conductive lines. Vias may be formed through portions of the first and second conductive lines in subsequent processing, which may change the resulting boundary of a conductive line; however, the term "footprint" is used herein in referring to the original boundaries of the first conductive line, e.g., immediately prior to the formation of a via therethrough.
  • As shown in Figure 6A, concentric memory cells 649, such as those described with respect to Figure 5, can be formed at location where the first conductive lines 622 and second conductive lines 624 overlap. That is, the concentric memory cells 649 can be formed where the first conductive lines 622 and second conductive lines 624 appear to intersect. Because the first conductive lines 622 and second conductive lines 624 are formed at different levels, they do not actually intersect one another. One memory cell 649 is formed at each word line - bit line overlap, e.g., at each level of the plurality of conductive line levels (indicated by j in Figure 6A).
  • Conductive extension 654 is substantially orthogonal to first conductive lines 622 and second conductive lines 624, e.g., it extends through the page in Figure 6A. Figure 6A shows in cross section (in a plane parallel to conductive lines 622) a conductive extension 654 passing through each first conductive line 622, for example, passing through a center line of a respective first conductive line 622. A storage element material 652, e.g., phase change material (PCM), and cell select device material 650, e.g., ovonic threshold switch (OTS) material, can be concentrically arranged around the conductive extension 654. Although Figure 6A shows the storage element material 652 is arranged adjacent to the conductive extension 654, and the cell select device material 650 is arranged concentric to the storage element material 652, embodiments of the present disclosure are not so limited, and the cell select device material 650 can be arranged to be adjacent to the conductive extension 654 with the storage element material 652 arranged concentric to the cell select device material 650.
  • As shown in Figure 6A, the conductive extension 654 can also be arranged to extend from a location on the center line of the second conductive lines 624. Alternatively the conductive extension 654 can be coupled to a respective second conductive line 624 offset from a center line location while still passing through a center line of the first conductive line, e.g., by varying slightly in horizontal positioning from that shown in Figure 6A.
  • Figure 6A shows the concentric memory cells 649 are located within a footprint, e.g., inside the outline of the structure, of the first conductive lines 622 at each level where first conductive lines 622 are formed in the stack of materials. That is, a cross-section of the conductive extension 654, the storage element material 652, and the cell select device material 650 is wholly located within a footprint of the first conductive line 622 as these concentrically-arranged materials pass through a first conductive line 622 formed at each of a plurality of levels. The cut line A-A shown in Figure 6A provides a reference for the views shown in Figures 7A - 7C.
  • Figure 6B illustrates location of concentric memory cells partially with a grid of conductive lines. Figure 6B shows a top view of a portion of a memory array 670. The memory array 670 includes a plurality of first conductive lines 622, e.g., word lines, and a plurality of second conductive lines 624, e.g., bit lines, arranged perpendicular to the first conductive lines 622. Other levels of first conductive lines 622, e.g., other levels of word lines, can be present below the word lines in level j shown in Figure 6B. The first conductive lines 622 and second conductive lines 624 overlap and thereby form a grid of conductive lines.
  • As shown in Figure 6B, concentric memory cells 672, similar in structure but different in location with respect to the first conductive lines 622 to those described with respect to Figure 5, can be formed at location in proximity to where the first conductive lines 622 and second conductive lines 624 overlap. That is, the concentric memory cells 672 can be formed near where the first conductive lines 622 and second conductive lines 624 appear to intersect (the first conductive lines 622 and second conductive lines 624 are formed at different levels such that they do not actually intersect one another). One concentric memory cell 672 can be formed in proximity of each word line - bit line overlap, e.g., at each level of the plurality of conductive line levels (indicated by j in Figure 6B).
  • A storage element material 652 and cell select device material 650 can be concentrically arranged around the conductive extension 654. Although Figure 6B shows the storage element material 652 is arranged adjacent to the conductive extension 654, and the cell select device material 650 is arranged concentric to the storage element material 652, embodiments of the present disclosure are not so limited, and the cell select device material 650 can be arranged to be adjacent to the conductive extension 654 with the storage element material 652 arranged concentric to the cell select device material 650.
  • Conductive extension 654 is substantially orthogonal to first conductive lines 622 and second conductive lines 624, e.g., it extends through the page in Figure 6B. Figure 6B shows in cross section (in a plane parallel to conductive lines 622) a conductive extension 654, the storage element material 652, and the cell select device material 650 passing through a portion of each first conductive line 622, such that these concentrically-arranged materials are not completely surrounded, e.g., enclosed at the level of each first conductive line 622, by the first conductive line 622. As such, only a portion of the circumference of the storage element material 652 and/or cell select device material 650 are in contact with the first conductive line 622 (at the level of the first conductive line 622). In this manner, the volume of the storage element material 652 involved in a phase change is less than when the storage element material 652 and/or cell select device material 650 passes wholly through the first conductive line 622.
  • For example as shown in Figure 6B, materials comprising the concentric memory cell 672 can be arranged such that a centerline of the concentric memory cell 672 is aligned with an edge, e.g., along a longest dimension, of a respective first conductive line 622. That is, materials comprising the concentric memory cell 672 can be located one-half within and one-half outside a footprint of a respective first conductive line 622. Alternatively, materials comprising the concentric memory cell 672 can be located so as to have some portion located within and a remaining portion located outside a footprint of a respective first conductive line 622.
  • By this arrangement, only a portion of the materials comprising the concentric memory cell 672 are located between conductive extension 654 and the first conductive line 622. As such, a reduced volume of storage element material 652 is effectively used in storing information. Accordingly, less energy can be required to program and/or erase the reduced volume of storage element material 652, such as in forming an amorphous region in the PCM. Also, the useful section for first conductive line 622 sinking current is increased with respect to a same width of first conductive line 622 in the case where the conductive extension 654 passes through, e.g., a center of, and is fully surrounded by the first conductive lines 622, such as is shown in Figure 6A. Alternatively, a reduced effective memory cell size is obtained by using a smaller first conductive line 622 width for a given resistivity per unit length; however, such an approach is more sensitive to misalignment between the concentric memory cell 672 and the first conductive line 622.
  • Figure 6C illustrates location of concentric memory cells 647 having concentric heater material within a grid of conductive lines in accordance with a number of embodiments of the present disclosure. Figure 6C shows a top view of a portion of a memory array 657. The memory array 657 includes a plurality of first conductive lines 622, e.g., word lines, and a plurality of second conductive lines 624, e.g., bit lines, arranged perpendicular to the first conductive lines 622. Other levels of first conductive lines 622, e.g., other levels of word lines, can be present below the word lines in level j shown in Figure 6C. The first conductive lines 622 and second conductive lines 624 overlap and thereby form a grid of conductive lines.
  • As shown in Figure 6C, concentric memory cells 647, of similar structure to those described with respect to Figure 5 but with an additional concentric material, can be formed at location where the first conductive lines 622 and second conductive lines 624 overlap. That is, the concentric memory cells 647 can be formed where the first conductive lines 622 and second conductive lines 624 appear to intersect. However, the first conductive lines 622 and second conductive lines 624 are formed at different levels so they do not actually intersect one another. One concentric memory cell 647 can be formed in proximity of each word line - bit line overlap, e.g., at each level of the plurality of conductive line levels (indicated by j in Figure 6C).
  • Figure 6C shows in cross section a conductive extension 654 passing through each first conductive line 622, for example, passing through a center line of a respective first conductive line 622. A storage element material 652, e.g., phase change material (PCM), and cell select device material 650, e.g., ovonic threshold switch (OTS) material, can be concentrically arranged around the conductive extension 654. A heater material 645 can be concentrically arranged around the conductive extension 654, storage element material 652 and/or cell select device material 650 such that the heater material 645 is adjacent to the storage element material 652, as shown in one configuration in Figure 6C. It should be noted that the relative positioning of the storage element material 652 and cell select device material 650 is reverse in Figure 6C from that shown in Figure 6A (so that the storage element material 652 is positioned adjacent the heater material 645), e.g., an alternate configuration as discussed with respect to Figure 6A.
  • The structure of a concentric memory cell that includes only a PCM memory element and an OTS, e.g., concentric memory cell 649 shown in Figure 6A, can require a relatively high amount of current in order to completely form an amorphous region at the entire interface between the OTS and the PCM. For a circular footprint of the concentric memory cell 649, the active volume is about 2π r*tGST*tWL where 2π r is the circumference of the vertical conductive extension 654, tGST is the thickness of PCM material 652, and tWL is the thickness of first conductive line 622. The active volume can be reduced by making the first conductive line 622 thinner, at the expense of increased resistance for the first conductive line 622.
  • According to a number of embodiments of the present disclosure, the effective thickness of the first conductive line 622 can be reduced while substantially maintaining overall resistance of the majority of the first conductive lines 622 to acceptable magnitudes by forming, e.g., depositing, a thin heater material 645 (thin relative to the thickness of the first conductive line 622 material) adjacent a thick first conductive line 622 material (thick relative to the thickness of the heater material 645).
  • The concentric memory cell 647 can be configured such that only the thin heater material 645 is in contact with the storage element material 652 and/or cell select device material 650, which serves to funnel current passing through the first conductive lines 622 into a smaller cross-section, thereby increasing localized current flow in the storage element material 652. The relatively thicker profile of the first conductive lines 622 provides a lower resistance of the first conductive lines 622, and the relatively thinner heater material 645 near the storage element material 652 decreases the effective cross-sectional area of the first conductive lines 622 at the concentric memory cells 647 so as to concentrate current flow. As such, the thin heater material 645 effectively reduces the active volume being subjected to phase change (because of the relatively thinner heater material 645 thickness) and may act as a heater that can heat-up by a Joule effect, therefore providing more concentrated energy and increased temperature to the adjacent storage element material 652. Although the term "heater material" is used in this disclosure to distinguish from other materials and structures, embodiments of the present disclosure are not limited to heater material that itself increases in temperature. That is, "heater material" is intended to designate a material and/or structure that can concentrate current flow so as to confine a volume of the storage element material 652 involved in a phase change, and which such current concentration can increase localize temperature in a particular volume of the storage element material 652.
  • The effective size of a concentric memory cell, e.g., 649 shown in Figure 6A, 672 shown in Figure 6B, and 647 shown in Figure 6C, of the present disclosure can be large compared to other memory cell configurations due to the coaxial arrangement and volumes of the storage element material 652 and/or cell select device material 650. As such, a single concentric memory cell may not be a minimum size for a given technology node. However, the fabrication process allows for stacking several levels of memory cells without increasing the array mask count proportionally since it is not necessary to define first conductive lines 622, e.g., word lines, and second conductive lines 624, e.g., bit lines, for each additional level.
  • Although Figure 6C shows the cell select device material 650 is arranged adjacent to the conductive extension 654, and the storage element material 652 is arranged concentric to the storage element material 652, embodiments of the present disclosure are not so limited, and the cell select device material 650, the storage element material 652, and the heater material 645 can be arranged, for example, in a reversed order.
  • As shown in Figure 6C, the conductive extension 654 can also be arranged to extend vertically through a location on the center line of the second conductive lines 624. However, embodiments are not so limited, and the conductive extension 654 can be coupled to a respective second conductive line 624 offset from a center line location while still passing through a center line of the first conductive line, e.g., by varying slightly in horizontal positioning from that shown in Figure 6C.
  • Figure 6C shows the concentric memory cells 647 are located within a footprint of the first conductive lines 622 at each level where first conductive lines 622 are formed in the stack of materials. That is, a cross-section of the conductive extension 654, the cell select device material 650, the storage element material 652, and the heater material 645 is wholly located within a footprint of the first conductive line 622 as these concentrically-arranged materials pass through a first conductive line 622 formed at each of a plurality of levels.
  • According to a number of embodiments, to improve conductivity of the first conductive lines 622 and minimize misalignment problems of the materials forming the concentric memory cells 647 passing through the first conductive line 622 so as to have a cross-section completely surrounded by material of the first conductive line 622 at some level, the first conductive lines 622 can be formed having dimensions greater than a possible minimum size since the storage element material 652 and the cell select device material 650 are more resistive than the first conductive lines 622 material.
  • The cut line B-B shown in Figure 6C provides a reference for the views shown in Figures 9A - 9C.
  • Figure 6D illustrates location of concentric memory cells 673 having concentric heater material partially within a grid of conductive lines in accordance with a number of embodiments of the present disclosure. Figure 6D shows a top view of a portion of a memory array 671. Concentric memory cells having concentric heater material are described above with respect to Figure 6C. The misalignment of the concentric memory cells with the overlaps of the first conductive lines 622 and second conductive lines 624 are described above with respect to Figure 6B, such that the concentric memory cells intersect the first conductive lines 622 in a manner that less than all of the concentric memory cells are surrounded by a particular first conductive line 622. These features can be combined, as illustrated with respect to concentric memory cells 673 in Figure 6D. In this manner, the first conductive line 622 conductivity improvement and reduced programming energy requirements associated with a reduced active volume can be simultaneously obtained.
  • Figures 7A-C illustrate a simplified process flow for forming a three dimensional memory array 760 of concentric memory cells, e.g., concentric memory cells 649 shown in Figure 6A. The view shown in Figures 7A-C is along cut line A-A shown in Figure 6A. Figure 7A shows formation, e.g., deposit, of a number of alternating insulating materials 748, e.g., dielectric, and conductive materials 722 (from which first conductive lines are formed) over an etch stop material 762, e.g., substrate material.
  • Vias 764, e.g., holes, can be formed, e.g., etched, through the alternating insulating materials 748 and conductive materials 722, for example stopping at the etch-stop material 762. By formation of vias a portion of conductive materials 722 can be removed such that the resulting area of the first conductive materials 722 may exclude the area removed in forming the via. However as previously discussed, the term "footprint" of the first conductive materials 722 refers to the boundary of the first conductive materials 722 just prior to forming a via therethrough, e.g., a via may pass, in whole or in part, through the footprint of the first conductive materials 722.
  • Figure 7B shows that vias 764 can be filled by subsequently forming, e.g., depositing, a cell select device material 750, e.g., ovonic threshold switch (OTS) material, a storage element material 752, e.g., phase change material (PCM), and a conductive extension material 754, e.g., metallic material, such that the result is the cell select device material 750 and storage element material 752 are concentric around the conductive extension material 754, e.g., shown in Figure 7B. As described above, other materials may be formed, e.g., deposited, before, after, and/or between cell device select material 750, storage element material 752, and/or conductive extension material 754, for example to form adhesion layers or barriers against interdiffusion of materials.
  • Figure 7C shows that cell select device material 750, storage element material 752, and conductive extension material 754 can be removed above the upper, e.g., last, insulating material 748, such as by etching and/or chemical-mechanical polishing (CMP) to isolate individual concentric memory cells 749 from one another. The second conductive lines 724, e.g., bit lines, can be formed over the filled vias, such that the second conductive lines 724 are communicatively coupled to the conductive extension material 754.
  • The second conductive lines 724 can be alternatively formed using a self-aligning etch leaving the cell select device material 750 and a storage element material 752 in-place above the upper insulating material 748 and below the second conductive lines 724, e.g., by directly patterning and etching the conductive extension material 754. According to another embodiment, a damascene process can be used for forming the second conductive lines 724.
  • Figures 8A-C illustrate a simplified process flow for forming a three dimensional memory array 866 of concentric memory cells with separated switching devices. It can be seen in Figure 7C that the cell select device material 750 deposited at the outermost radial position of the concentric memory cell is contiguous vertically between different levels of first conductive lines 722. The process flow shown in Figures 8A-C results in the cell select device material associated with discrete memory cells, and deposited at the outermost radial position of the concentric memory cell, to be separated between different levels (corresponding to different first conductive lines).
  • The view shown in Figures 8A-C is along cut line A-A shown in Figure 6A. Although the separation between different concentric memory cells is described here with respect to the cell select device material, the relative radial locations of cell select device material and storage element material can be swapped such that the storage element material is located at the outermost radial position of the concentric memory cell, and the storage element material is separated between different concentric memory cells.
  • Figure 8A shows deposit of a number of alternating insulating materials 848, e.g., dielectric, and conductive materials 822 over a etch stop material 862. By formation of vias a portion of conductive materials 822 can be removed such that the resulting area of the first conductive materials 822 may exclude the area removed in forming the via. However as previously discussed, the term "footprint" of the first conductive materials 822 refers to the boundary of the first conductive materials 822 just prior to forming a via therethrough, e.g., a via may pass, in whole or in part, through the footprint of the first conductive materials 822. Vias, e.g., holes, can be etched through the alternating insulating materials 848 and conductive materials 822, for example stopping at the etch stop material 862 (similar to that shown in Figure 7A for vias 764). During or after via formation the conductive materials 822 are recessed to result in the configuration of via 868 illustrated in Figure 8A. The recesses 869 in the conductive materials 822 can be formed with a selective etch of an exposed region of the conductive materials 822 in the via 868 such as by a non-directional etch, e.g., wet etch.
  • Figure 8B shows cell select device material 855 deposited into via 868, onto the sidewalls thereof, which fills the areas left by the recessed conductive materials 822 comprising the first conductive lines, as shown.
  • Figure 8C shows cell select device material 855 removed from the top surface, i.e., above the upper insulating material 848, and removed from the sidewalls of the vias, such as by a directional etch, e.g., dry etch. This leaves the cell select device material 855 only in the discrete areas left by the recessed conductive materials 822. Thereafter, storage element material 852, e.g., PCM, and conductive extension 854, e.g., metallic vertical bit line extension, material can be formed in the via as shown. According to the process illustrated with respect to Figure 8A-C, the cell select device material 855 is formed only as a plurality of discrete ring structures around the conductive extension 854 of the second conductive lines and storage element material 852 at the crossing of the first conductive lines 822, thereby reducing electrical leakage and interference between vertically adjacent concentric memory cells 867. The storage element material 852 and conductive extension 854 material can be further processed, and second conductive lines, e.g., bit lines, formed thereover, as described with respect to Figure 7C.
  • Figures 9A-C illustrate a simplified process flow for forming a three dimensional memory array 980 of concentric memory cells 994 having heater material in accordance with a number of embodiments of the present disclosure. The formation process shown and described with respect to Figure 9A-C is similar to that shown and described with respect to Figure 8A-C, with the exception that an additional heater material is included. The view shown in Figures 9A-C is along cut line B-B shown in Figure 6C. As discussed with respect to Figure 6C, configurations of the concentric memory cells 994 include the storage element material 952 and heater material 945 being adjacent in order to achieve reduced programming energy requirements associated with a reduced active volume.
  • Figure 9A shows deposit of a number of alternating insulating materials 948, e.g., dielectric, heater material 945, and conductive materials 922 over a etch stop material 982. By formation of vias a portion of conductive materials 922 can be removed such that the resulting area of the first conductive materials 922 may exclude the area removed in forming the via. However as previously discussed, the term "footprint" of the first conductive materials 922 refers to the boundary of the first conductive materials 922 just prior to forming a via therethrough, e.g., a via may pass, in whole or in part, through the footprint of the first conductive materials 922. Vias 990 can be etched through the alternating insulating materials 948, heater material 945, and conductive materials 922, for example stopping at the etch stop material 982.
  • During or after via 990 formation (similar to that shown in Figure 8A for via 868), the conductive materials 922 can be recessed to result in the configuration illustrated in Figure 9A. The recesses 969 in the conductive materials 922 can be formed with a selective etch of an exposed region of the conductive materials 922 in the via such as non-directional etch, e.g., wet etch. The non-directional etch can be specific to the conductive materials 922 but not (or less so) the heater material 945, which can be a different material than the conductive materials 922.
  • Insulating material 992 can be deposited into via 990, including onto the sidewalls thereof, filling the recesses 969, e.g., areas left by the recessed conductive materials 922 (comprising the first conductive lines). Note this is different than depositing the cell select device material 855 into the recesses 869 as shown in Figure 8B. The insulating material 992 can be removed from the top surface, i.e., above the upper insulating material 948, and removed from the sidewalls of the vias 990, such as by a directional etch, e.g., dry etch, which can leave the insulating material 992 only in the recesses 969, e.g., discrete areas left by the recessed conductive materials 922, while exposing a portion of heater material 988 at the sidewall of vias 990, as shown in Figure 9B.
  • According to a number of alternative embodiments, rather than form recesses 969 in the conductive materials 922, depositing insulating material 992 and etching to remove all but the insulating material 992 in the recesses 969, the conductive materials 922 can be selectively oxidized (with or without forming the recesses 969) to form insulating material 992.
  • Figure 9C shows that vias 990 can be filled by subsequently forming, e.g., depositing, a storage element material 952, e.g., phase change material (PCM) (corresponding to storage element material 652 shown in Figure 6C), a cell select device material 950, e.g., ovonic threshold switch (OTS) material (corresponding to cell select device material 650 shown in Figure 6C), and a conductive extension material 954, e.g., metallic material, (corresponding to conductive extension 654 shown in Figure 6C) such that the result is the cell select device material 952 and storage element material 950 are concentric around the conductive extension material 954 within the via 990, with the storage element material 952 being adjacent the heater material 945.
  • Because the area left by recessing the first conductive line material 922 is filled with insulating material 992, current flowing in the first conductive lines 922 is routed all to the heater material 945, with a relatively smaller cross-sectional area, in the vicinity of the concentric memory cell, thereby concentrating the current toward a smaller volume of storage element material 952 involved in phase changes, as indicated in Figure 9C at 999. As discussed in detail above with respect to Figure 6C, the use of heater material 945 effectively reduces first conductive line 922 thickness in the vicinity of the storage element material 952, thereby involving a smaller active volume in phase changes, and also increases current density in the heater material 945, which heats-up due to the Joule effect and transfers energy, i.e., raises temperature, to the storage element material 950. As such, the heater material 945 is so named since it may act as a heater.
  • The cell select device material 950, storage element material 952, and conductive extension material 954 can be further processed, and second conductive lines, e.g., bit lines, formed thereover, as described with respect to Figure 7C.
  • Figure 9D illustrates the result of a process flow for forming a three dimensional memory array 981 of concentric memory cells 993 having first conductive lines, e.g., word lines, with an interceding heater material in accordance with a number of embodiments of the present disclosure. After considering Figure 9A-C with respect to one process for forming heater materials adjacent the concentric memory cell, an alternative process for forming the heater material interceding to the first conductive lines will be understood by considering the configuration shown in Figure 9D in comparison to the configuration shown in Figure 9C.
  • The configuration of memory array 981 shown in Figure 9D can be formed by depositing a number of instances of insulating materials 948, e.g., dielectric, conductive material 985, heater material 945, and conductive material 985 over a etch stop material 982. The two conductive materials 985 comprise the first conductive lines, e.g., word lines, which have a heater material 945 disposed therebetween, e.g., interceding to the first conductive line.
  • Vias 990 can be etched through the number of instances of insulating materials 948 and first conductive lines having the interceding heater material, e.g., conductive material 985, heater material 945, and conductive material 985 (similar to that shown in Figure 8A for via 868). The conductive materials 985 can be each recessed with a non-directional etch, e.g., wet etch, similar to the result illustrated in Figure 9A except that each heater material 945 can have a recess 969 in the adjacent conductive materials 985 above and below the heater material 945. The non-directional etch can be specific to the conductive materials 985 but not (or less so) the heater material 945, which can be a different material than the conductive materials 985.
  • Insulating material 991 can be deposited into the via, including onto the sidewalls thereof, filling the areas left by the recessed conductive materials 985 above and below the heater material 945 that extends beyond the ends of the conductive materials 985. The insulating material 991 can be removed from the top surface, i.e., above the upper insulating material 948, and removed from the sidewalls of the vias, such as by a directional etch, e.g., dry etch, which can leave the insulating material 991 only in the discrete areas left by the recessed conductive materials 985, immediately above and below the heater materials 945.
  • The resulting vias can be filled by subsequently forming, e.g., depositing, a storage element material 952, e.g., phase change material (PCM), a cell select device material 950, e.g., ovonic threshold switch (OTS) material, and a conductive extension material 954, e.g., metallic material, such that the result is the cell select device material 950 and storage element material 952 are concentric around the conductive extension material 954, as shown in Figure 9D. As discussed in detail above with respect to Figure 6C, the use of heater material 945 effectively reduces first conductive line 922 thickness in the vicinity of the storage element material 952, thereby involving a smaller active volume in phase changes, and also increases current density in the heater material 945, which heats-up due to the Joule effect and transfers energy, i.e., raises temperature, to the storage element material 952. As such, the heater material 945 is so named since it may act as a heater.
  • During operation, current flowing in the first conductive lines, i.e., conductive materials 985, is routed all to the heater material 945, with a relatively smaller cross-sectional area, in the vicinity of the concentric memory cell, thereby concentrating the current toward a smaller volume of storage element material 952 involved in phase changes, as indicated in Figure 9C at 997. The cell select device material 950, storage element material 952, and conductive extension material 954 can be further processed, and second conductive lines, e.g., bit lines, formed thereover, as described with respect to Figure 7C.
  • It should be noted that the use of heater material, as described with respect to Figure 9A-D can be applied to vias formed to intersect and be fully surrounded by first conductive lines within overlaps of first and second conductive lines, e.g., locations illustrated in Figure 6C, or applied to vias formed to intersect only a portion (and not be fully surrounded by) first conductive lines, e.g., locations illustrated in Figure 6D, among others.
  • The example embodiment with a "misaligned" vertical conductive extension, e.g., not intersecting a first conductive line so as to be entirely surrounded by the first conductive line, effectively reduces active volume since only a portion of the circumference, e.g., semi-circumference, of the via interacts with a given first conductive line, e.g., word line. An embodiment having a "misaligned" vertical conductive extension can also reduce memory cell space since the first conductive line width can be relatively more narrow since a smaller portion of its width is impacted by formation of the via.
  • Although the amount of surface area between the cell select device material, e.g., OTS, and the storage element material, e.g., PCM, is decreased, a relatively large current between these two materials may be used to amorphize the entire volume of the storage element material. The active volume is about 2πr*tGST*tWL where 2πr is the (portion) of the circumference of the storage element material at the interface with adjacent material (which can be further adjusted for configurations where only a portion of the circumference interacts with the storage element material), tGST is the active storage element material thickness, and tWL is the effective first conductive line, e.g., word line, thickness. Effective first conductive line thickness can be reduced to a thickness of a heater material 945, tH, while maintaining overall first conductive line resistance acceptable, pursuant to the embodiments illustrated with respect to Figure 9A-D.
  • According to some embodiments, for each deck a thin layer of storage element material, e.g., PCM such as GST, can be flat-deposited so as to be communicatively coupled with the first conductive line material, e.g., in direct contact with the first conductive line material similar to the heater material configuration shown in Figure 9C, or sandwiched between two layers of the first conductive line material similar to the heater material configuration shown in Figure 9D. The first conductive line material ends at the sidewalls of a via can be recessed and insulated by selective etch or oxidation (as previously described with respect to Figures 9A-D but with the storage element material extending to the vertical conductive extension material, e.g., 954 in Figure 9D), through the cell select device material. For clarity, the resulting structures are similar to those represented in Figure 9C and 9D and described above, with the modification that the storage element material would be represented by portions corresponding to reference number 945 in Figures 9C and 9D, and portions corresponding to reference number 952 would not be present.
  • According to some embodiments, a three dimension memory array can include a stack comprising a plurality of first conductive lines adjacent storage element material at a number of levels separated from one another by at least an insulation material. The storage element material forms a protrusion with respect to each of the plurality of first conductive lines, such as at an edge thereof. At least one conductive extension can be arranged to extend substantially perpendicular to the plurality of first conductive lines and adjacent storage element material. The cell select material can be formed within the via between the storage element material protrusion and the at least one conductive extension.
  • This embodiment can reduce the overall cell dimensions since only two materials are in the vertical BL portion, e.g., the cell select material and the conductive extension material. This embodiment also confines the active storage element material volume of a memory cell to between the first conductive line and the vertical conductive extension, reducing active storage element material volume to 2πr *tGST*EXTWL where 2πr is the (portion) of the circumference of the storage element material at the interface with adjacent material (which can be further adjusted for configurations where only a portion of the circumference interacts with the storage element material), tGST is the active storage element material thickness, and EXTWL is the extension of thin storage element material, e.g., GST, from the relatively thicker low-resistance first conductive line material.

Claims (11)

  1. A three-dimensional memory array (657; 671; 980; 981), comprising:
    a stack (544) comprising a plurality of first conductive lines (622; 922), at a number of levels separated from one another by at least an insulation material (948), wherein the plurality of first conductive lines (622; 922) comprise word lines;
    at least one conductive extension (654; 954) arranged to extend substantially perpendicular to the plurality of first conductive lines (622; 922), such that the at least one conductive extension (654; 954) passes through a portion of each of the plurality of first conductive lines (622; 922);
    a plurality of second conductive lines (624) wherein each second conductive line (624) of the plurality of second conductive lines is formed over the plurality of first conductive lines (622; 922) and the at least one conductive extension (654; 954), and wherein the at least one conductive extension (654; 954) is coupled to a respective one of the plurality of second conductive lines (624); and
    storage element material (652; 952) and cell select material (650; 950) arranged one around the other and around the at least one conductive extension (654; 954;
    a heater material (645; 945), adjacent to, and communicatively coupled with, each of the plurality of first conductive lines (622; 922), the heater material (645; 945) having a cross-sectional area smaller than that of at least one of the plurality of first conductive lines (622,922), the heater material (645; 945) being arranged in series between a respective one of the plurality of first conductive lines (622; 922) and the storage element material (652; 952), and characterized in that the heater material (645; 945) is a different material than the plurality of first conductive lines (622;922) and in that the heater is configured to concentrate current flow so as to confine volume of storage material (652,952) involved in a phase change.
  2. The memory array of claim 1, wherein the heater material (945) is sandwiched between two layers (985) of said first conductive lines (922), each of the two layers (985) of said first conductive lines (922) being adjacent to upper and lower surfaces of the heater material (945), respectively.
  3. The memory array of claim 1, wherein the cell select material (650; 950) is concentrically formed around the storage element material (652; 952).
  4. The memory array of claim 1, wherein the plurality of second conductive lines (624) is formed to extend substantially perpendicular to the plurality of first conductive lines (622; 922) at a different level than the number of levels, and is arranged to extend substantially perpendicular to the at least one conductive extension (654; 954).
  5. The memory array of claim 1, wherein the storage element material (652; 952) is phase change material "PCM", and the cell select material is ovonic threshold switch "OTS" material.
  6. The memory array of claim 1, wherein the plurality of second conductive lines (624) are arranged to extend substantially perpendicular to the plurality of first conductive lines (622; 922) at a level above the plurality of first conductive lines (622; 922).
  7. The memory array of claim 6, wherein the at least one conductive extension (654; 954) is arranged to extend vertically from the second conductive line (624) to pass through multiple ones of the plurality of first conductive lines (622; 922).
  8. A method of forming a memory array (657; 671; 980; 981), comprising:
    forming a stack (544) comprising a plurality of first conductive lines (622; 922), separated from one another by insulation material (948), said first conductive lines (622; 922) being adjacent to, and communicatively coupled with, heater material (645; 945), wherein the plurality of first conductive lines (622; 922) comprise word lines;
    forming a via (990) through the stack (544) such that at least a portion of the via (990) passes through each of the plurality of first conductive lines (622; 922) and through the adjacent heater material (645; 945);
    forming a storage element material (652; 952) and cell select material (650; 950), one over the other, within the via (990);
    forming a conductive extension (654; 954) over the storage element material (652; 952) and cell select material (650; 950) within the via, such that the cell select material and the storage element material (652; 952) surround the conductive extension (654, 954); and
    forming a plurality of second conductive lines (624) over the plurality of first conductive lines (622; 922) and the conductive extension (654; 954) so as to be substantially perpendicular to the first conductive lines (622; 922) and the conductive extension (654; 954), the conductive extension (654; 954) being communicatively coupled to a respective one of the plurality of second conductive lines (624) as an extension thereof; whereby
    the first conductive lines (622; 922) are offset from the adjacent material, either the storage element material (652; 952) or cell select material (650; 950), by insulating material (991; 992) formed in recessed portions of the conductive lines (622; 922);
    the heater material (645; 945) has a cross-sectional area smaller than that of at least one of the plurality of first conductive lines (622; 922) and is configured to concentrate current flow so as to confine a volume of the storage element material (652; 952) involved in a phase change; and
    the heater material (645; 945) is arranged in series between a respective one of the plurality of first conductive lines (622; 922) and the storage element material (652; 952) and the heater material (645; 945) being a different material than the plurality of first conductive lines (622; 922).
  9. The method of claim 8, wherein, prior to forming the storage element material (652; 952) and the cell select material (650; 950), forming the via (990) is followed by forming a plurality of recesses (969), each one of the plurality of recesses formed at an exposed region of each of the first conductive lines (622; 922) in a wall of the via (990) by a non-directional etch that is more selective to the first conductive lines (622; 922) than the insulation material (748; 848; 948); and depositing insulating material (991; 992) to fill each of the recesses for offsetting the first conductive lines (622; 922) from the storage element material (652; 952) or cell select material (650; 950) which is later formed within the via (990).
  10. The method of claim 8, wherein, prior to forming the storage element material (652; 952) and the cell select material (650; 950), forming the via (990) is followed by selective oxidation of the first conductive lines (622; 922) to form the insulating material for offsetting the first conductive lines (622; 922) from the storage element material (652; 952) or cell select material (650; 950) which is later formed within the via (990).
  11. The method of any preceding claim 8-10, wherein forming the via through the stack (544) comprises forming a via that is not entirely surrounded by a first conductive line (322; 522; 622; 722; 822; 922) and adjacent heater material (645; 945) of the plurality of first conductive lines (322; 522; 622; 722; 822; 922) and adjacent heater material (645; 945).
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Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8841649B2 (en) * 2012-08-31 2014-09-23 Micron Technology, Inc. Three dimensional memory array architecture
US8729523B2 (en) 2012-08-31 2014-05-20 Micron Technology, Inc. Three dimensional memory array architecture
KR101956794B1 (en) * 2012-09-20 2019-03-13 에스케이하이닉스 주식회사 Resistance variable memory device and method for fabricating the same
KR20140054975A (en) * 2012-10-30 2014-05-09 에스케이하이닉스 주식회사 Variable resistance memory device
US9099637B2 (en) * 2013-03-28 2015-08-04 Intellectual Discovery Co., Ltd. Phase change memory and method of fabricating the phase change memory
US9728584B2 (en) 2013-06-11 2017-08-08 Micron Technology, Inc. Three dimensional memory array with select device
EP2887396B1 (en) * 2013-12-20 2017-03-08 Imec Three-dimensional resistive memory array
US9305932B2 (en) * 2014-06-30 2016-04-05 Sandisk Technologies Inc. Methods of making three dimensional NAND devices
TWI584442B (en) * 2014-09-09 2017-05-21 旺宏電子股份有限公司 Semiconductor device
TWI550682B (en) * 2014-12-31 2016-09-21 旺宏電子股份有限公司 Memory device and method for fabricating the same
US9595669B2 (en) 2015-06-30 2017-03-14 Western Digital Technologies, Inc. Electroplated phase change switch
KR20170004602A (en) 2015-07-03 2017-01-11 에스케이하이닉스 주식회사 Electronic device
US9564585B1 (en) 2015-09-03 2017-02-07 HGST Netherlands B.V. Multi-level phase change device
US10134470B2 (en) 2015-11-04 2018-11-20 Micron Technology, Inc. Apparatuses and methods including memory and operation of same
US9978810B2 (en) 2015-11-04 2018-05-22 Micron Technology, Inc. Three-dimensional memory apparatuses and methods of use
US9825098B2 (en) 2016-03-04 2017-11-21 Toshiba Memory Corporation Semiconductor memory device
US9728585B1 (en) 2016-03-11 2017-08-08 Kabushiki Kaisha Toshiba Semiconductor memory device
US9741768B1 (en) * 2016-03-31 2017-08-22 Sandisk Technologies Llc Controlling memory cell size in three dimensional nonvolatile memory
US9947721B2 (en) * 2016-04-01 2018-04-17 Micron Technology, Inc. Thermal insulation for three-dimensional memory arrays
US9837471B2 (en) 2016-04-14 2017-12-05 Western Digital Technologies, Inc. Dual OTS memory cell selection means and method
US9741769B1 (en) * 2016-04-19 2017-08-22 Western Digital Technologies, Inc. Vertical memory structure with array interconnects and method for producing the same
US10446226B2 (en) 2016-08-08 2019-10-15 Micron Technology, Inc. Apparatuses including multi-level memory cells and methods of operation of same
US10062653B2 (en) * 2016-09-29 2018-08-28 Toshiba Memory Corporation Semiconductor device and method for manufacturing same
US10276555B2 (en) * 2016-10-01 2019-04-30 Samsung Electronics Co., Ltd. Method and system for providing a magnetic cell usable in spin transfer torque applications and including a switchable shunting layer
US10157670B2 (en) 2016-10-28 2018-12-18 Micron Technology, Inc. Apparatuses including memory cells and methods of operation of same
KR20180064842A (en) 2016-12-06 2018-06-15 삼성전자주식회사 Semiconductor devices
US10096655B1 (en) * 2017-04-07 2018-10-09 Micron Technology, Inc. Three dimensional memory array
US10157653B1 (en) 2017-06-19 2018-12-18 Sandisk Technologies Llc Vertical selector for three-dimensional memory with planar memory cells
US10263039B2 (en) 2017-06-26 2019-04-16 Micron Technology, Inc. Memory cells having resistors and formation of the same
US10424728B2 (en) * 2017-08-25 2019-09-24 Micron Technology, Inc. Self-selecting memory cell with dielectric barrier
US10461125B2 (en) 2017-08-29 2019-10-29 Micron Technology, Inc. Three dimensional memory arrays
US10490602B2 (en) * 2017-09-21 2019-11-26 Micron Technology, Inc. Three dimensional memory arrays
US10374014B2 (en) 2017-10-16 2019-08-06 Sandisk Technologies Llc Multi-state phase change memory device with vertical cross-point structure
US10381411B2 (en) * 2017-12-15 2019-08-13 Sandisk Technologies Llc Three-dimensional memory device containing conformal wrap around phase change material and method of manufacturing the same
US10475995B2 (en) * 2017-12-22 2019-11-12 Intel Corporation Tip-contact controlled three dimensional (3D) vertical self select memory
US10381559B1 (en) 2018-06-07 2019-08-13 Sandisk Technologies Llc Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same
US10381409B1 (en) 2018-06-07 2019-08-13 Sandisk Technologies Llc Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same
WO2019236162A1 (en) * 2018-06-07 2019-12-12 Sandisk Technologies Llc Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100276743A1 (en) * 2007-12-27 2010-11-04 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566700B2 (en) 2001-10-11 2003-05-20 Ovonyx, Inc. Carbon-containing interfacial layer for phase-change memory
US7767993B2 (en) * 2002-04-04 2010-08-03 Kabushiki Kaisha Toshiba Resistance change memory device
US7989789B2 (en) 2002-04-04 2011-08-02 Kabushiki Kaisha Toshiba Phase-change memory device that stores information in a non-volatile manner by changing states of a memory material
US6906940B1 (en) 2004-02-12 2005-06-14 Macronix International Co., Ltd. Plane decoding method and device for three dimensional memories
US7687830B2 (en) * 2004-09-17 2010-03-30 Ovonyx, Inc. Phase change memory with ovonic threshold switch
US7608503B2 (en) * 2004-11-22 2009-10-27 Macronix International Co., Ltd. Side wall active pin memory and manufacturing method
US20070045606A1 (en) 2005-08-30 2007-03-01 Michele Magistretti Shaping a phase change layer in a phase change memory cell
US8188454B2 (en) * 2005-10-28 2012-05-29 Ovonyx, Inc. Forming a phase change memory with an ovonic threshold switch
US7345899B2 (en) 2006-04-07 2008-03-18 Infineon Technologies Ag Memory having storage locations within a common volume of phase change material
JP5091491B2 (en) 2007-01-23 2012-12-05 株式会社東芝 Nonvolatile semiconductor memory device
US7382647B1 (en) * 2007-02-27 2008-06-03 International Business Machines Corporation Rectifying element for a crosspoint based memory array architecture
JP2008277543A (en) * 2007-04-27 2008-11-13 Toshiba Corp Nonvolatile semiconductor memory device
JP2009081251A (en) * 2007-09-26 2009-04-16 Panasonic Corp Resistance change element, production method thereof, and resistance change memory
US7729162B2 (en) * 2007-10-09 2010-06-01 Ovonyx, Inc. Semiconductor phase change memory using multiple phase change layers
KR20090037690A (en) * 2007-10-12 2009-04-16 삼성전자주식회사 Non-volatile memory device, method of operating the same and method of fabricating the same
JP5142692B2 (en) 2007-12-11 2013-02-13 株式会社東芝 Nonvolatile semiconductor memory device
US8194433B2 (en) 2008-02-20 2012-06-05 Ovonyx, Inc. Method and apparatus for accessing a bidirectional memory
US7839673B2 (en) * 2008-06-06 2010-11-23 Ovonyx, Inc. Thin-film memory system having thin-film peripheral circuit and memory controller for interfacing with a standalone thin-film memory
KR20100001260A (en) * 2008-06-26 2010-01-06 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
US7888668B2 (en) 2008-07-17 2011-02-15 United Microelectronics Corp. Phase change memory
KR101585620B1 (en) 2008-07-24 2016-01-14 가부시키가이샤 알박 Action monitoring system for treating device
US7943515B2 (en) 2008-09-09 2011-05-17 Sandisk 3D Llc Shared masks for x-lines and shared masks for y-lines for fabrication of 3D memory arrays
US8148707B2 (en) * 2008-12-30 2012-04-03 Stmicroelectronics S.R.L. Ovonic threshold switch film composition for TSLAGS material
JP4956598B2 (en) 2009-02-27 2012-06-20 シャープ株式会社 Nonvolatile semiconductor memory device and manufacturing method thereof
TWI433302B (en) 2009-03-03 2014-04-01 Macronix Int Co Ltd Integrated circuit self aligned 3d memory array and manufacturing method
KR20100111165A (en) 2009-04-06 2010-10-14 삼성전자주식회사 Three dimensional memory device
US8829646B2 (en) 2009-04-27 2014-09-09 Macronix International Co., Ltd. Integrated circuit 3D memory array and manufacturing method
US8173987B2 (en) * 2009-04-27 2012-05-08 Macronix International Co., Ltd. Integrated circuit 3D phase change memory array and manufacturing method
JP5180913B2 (en) 2009-06-02 2013-04-10 シャープ株式会社 Nonvolatile semiconductor memory device
KR101028993B1 (en) 2009-06-30 2011-04-12 주식회사 하이닉스반도체 3d-nonvolatile memory device and method for fabricating the same
JP5406782B2 (en) 2009-09-25 2014-02-05 シャープ株式会社 Nonvolatile semiconductor memory device
US8654560B2 (en) * 2009-10-28 2014-02-18 Intermolecular, Inc. Variable resistance memory with a select device
JP5558090B2 (en) * 2009-12-16 2014-07-23 株式会社東芝 Resistance variable memory cell array
KR101069724B1 (en) 2009-12-22 2011-10-04 주식회사 하이닉스반도체 Phase Change Memory Having 3 Dimension Stack Structure and Method of Manufacturing the Same
JP5144698B2 (en) 2010-03-05 2013-02-13 株式会社東芝 Semiconductor memory device and manufacturing method thereof
KR20110123005A (en) 2010-05-06 2011-11-14 삼성전자주식회사 Nonvolatile memory device using variable resistive element and fabricating method thereof
JP5503416B2 (en) * 2010-06-02 2014-05-28 株式会社日立製作所 Semiconductor memory device
US8289763B2 (en) * 2010-06-07 2012-10-16 Micron Technology, Inc. Memory arrays
JP5508944B2 (en) 2010-06-08 2014-06-04 株式会社東芝 Semiconductor memory device
US8547720B2 (en) * 2010-06-08 2013-10-01 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
US8803214B2 (en) * 2010-06-28 2014-08-12 Micron Technology, Inc. Three dimensional memory and methods of forming the same
KR101811308B1 (en) * 2010-11-10 2017-12-27 삼성전자주식회사 Non-volatile memory device having resistance changeable element and method of forming the same
US8426306B1 (en) * 2010-12-31 2013-04-23 Crossbar, Inc. Three dimension programmable resistive random accessed memory array with shared bitline and method
KR20120094339A (en) 2011-02-16 2012-08-24 에스케이하이닉스 주식회사 3d-nonvolatile memory device and method for manufacturing the same
JP5662237B2 (en) 2011-05-10 2015-01-28 株式会社日立製作所 Semiconductor memory device
US9343672B2 (en) * 2011-06-07 2016-05-17 Samsung Electronics Co., Ltd. Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices
US9627443B2 (en) * 2011-06-30 2017-04-18 Crossbar, Inc. Three-dimensional oblique two-terminal memory with enhanced electric field
US8841649B2 (en) * 2012-08-31 2014-09-23 Micron Technology, Inc. Three dimensional memory array architecture
US8729523B2 (en) 2012-08-31 2014-05-20 Micron Technology, Inc. Three dimensional memory array architecture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100276743A1 (en) * 2007-12-27 2010-11-04 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same

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