JP2012074542A - Nonvolatile storage device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile storage device capable of improving reliability of a memory using a resistance change material, and to provide a method of manufacturing the same.SOLUTION: A plurality of metal wiring layers 2 are formed above a substrate for forming a semiconductor element so as to extend in a first direction. A plurality of metal wiring layers 3 are formed above the metal wiring layer 2 so as to extend in a second direction perpendicular to the first direction. Memory cells are provided in respective spaces in which the metal wiring layers 2 and the metal wiring layers 3 are crossed. Each memory cell has a configuration in which a selection element and a phase change material layer 7 are connected in parallel. The selection element is processed such that the length in the first direction is longer than that in the first direction of the phase change material layer 7.

Description

  The present invention relates to a nonvolatile memory device and a method for manufacturing the same, and more particularly to an electrically rewritable phase change memory and a technique effective when applied to the manufacturing thereof.

  In recent years, a resistance change type memory has been studied as a nonvolatile memory device replacing a flash memory that is approaching the limit of miniaturization. As an example, phase change memory using chalcogenide as a memory element has been actively studied. In this memory element, a phase change material (for example, chalcogenide) is disposed between metal electrodes.

The resistance value of chalcogenides such as Ge ₂ Sb ₂ Te ₅ can be changed between an amorphous state and a crystalline state by Joule heat generated by an applied current. Chalcogenide has a high resistance value in the amorphous state and a low resistance value in the crystalline state. These resistance values correspond to the stored information of the phase change memory.

  The basic memory cell structure of the phase change memory is a structure in which a storage element (phase change material layer) and a selection element are combined.

  In addition, phase change memory is non-volatile, and write / read operations are expected to be as fast as DRAM (Dynamic Random Access Memory), and the cell area can be reduced to the same level as flash memory. Therefore, it is regarded as a promising next-generation nonvolatile memory.

  In the rewrite operation of the phase change memory, the applied current is controlled according to the stored information. In a reset (erase) operation, that is, an operation of writing information “0”, a large current is passed through the phase change material for a short time to dissolve the phase change material, and then the current is rapidly decreased. By such control, the phase change material is rapidly cooled to change the phase change material into a high-resistance amorphous state. On the other hand, in the set (write) operation, that is, the write operation of information “1”, the phase change material is made to be a low-resistance crystal by flowing a current sufficient to maintain the crystallization temperature of the phase change material for a long time. Change to state. In the read operation of the phase change memory, the resistance state of the element is determined by applying a constant potential difference across the element and measuring the current flowing through the element.

  When the phase change memory is further miniaturized, a current required for changing the state of the chalcogenide becomes small. For this reason, it is suitable for miniaturization in principle. As a method for highly integrating a phase change memory, Patent Document 1 (Japanese Patent Application Laid-Open No. 2008-160004) discloses a plurality of layers in which a plurality of gate electrode materials and insulating films are alternately stacked, and all layers of the stacked structure are penetrated. Are formed by batch processing, and a gate insulating film, a channel layer, and a phase change film are sequentially formed inside the through holes and processed.

JP 2008-160004 A

  Prior to the present application, the present inventors examined a selection operation of a unit cell using a chalcogenide material and a diode as described in FIG. In particular, a selection operation in a reset (erase) operation in which a large current is applied was examined. FIG. 44 shows an equivalent circuit diagram of a unit cell having a structure similar to the unit cell structure shown in FIG. 19C of Patent Document 1 as a comparative example.

  The unit cell of the comparative example shown in FIG. 44 is formed between a bit line BL and a source line SL formed on a semiconductor substrate (not shown). This unit cell has a structure in which a vertical transistor TRe and four memory cells MCj (j = 1 to 4) are connected in series. The vertical transistor TRe is formed on a wiring layer forming a source line, and the memory cells MCj (j = 1 to 4) are sequentially stacked on the vertical transistor TRe. Each of the memory cells MCj (j = 1 to 4) includes a transistor TRk and a resistance change element HRk ((j, k) = (1, a), (2, b), (3, c, (4, d)). ) Are connected in parallel.

  Here, it is assumed that the first to third memory cells MC1 to MC3 from the bottom of FIG. 44 are in a non-selected state, and the fourth memory cell MC4 from the bottom is in a selected state. The element characteristic requirements of the memory cell MC3 and the fourth-stage memory cell MC4 will be described.

  First, in the fourth-stage memory cell MC4 in the selected state, it is desirable to flow the reset current IRST supplied via the bit line BL into the resistance change element HRd without waste. For this purpose, the transistor TRd needs to be cut off sufficiently, but actually, a leakage current ILK_TRd flows through the transistor TRd. Accordingly, the cutoff characteristic of the transistor TRd is such that the current IRST_HRd (= reset current IRST−leakage current ILK_TRd) flowing through the resistance change element HRd is larger than the reset current IRST necessary for increasing the resistance of the resistance change element HRd. It must be something like that. For this purpose, it is necessary to increase the gate length of the transistor TRd.

  Next, attention is focused on the third-stage memory cell MC3 in a non-selected state. Similarly to the fourth-stage memory cell MC4 in the selected state, in the memory cell MC3, even if the reset current IRST is caused to flow through the transistor TRc as much as possible, a small amount of leakage current IUS_HRc actually flows through the resistance change element HRc. There is a possibility. When the magnitude of the leakage current IUS_HRc increases, the stored information stored in the resistance change element HRc is erroneously rewritten, and the reliability of the nonvolatile memory device is reduced.

  Further, when a relatively large leak current IUS_HRc flows through the resistance change element HRc many times, deterioration (fatigue) such as an increase in the resistance value of the resistance change element occurs, and the characteristics of the memory cell change. There is a problem that the reliability of the nonvolatile memory device is lowered.

  On the other hand, in order to retain the stored information of the memory cell MC3 in the non-selected state and suppress fatigue of the resistance change element, the reset current IRST supplied from the bit line BL via the memory cell MC4 is set as much as possible. It is necessary to bypass the transistor TRc. For this reason, the resistance in the conductive state of the transistor TRc, that is, the on-resistance RON_TRc must be sufficiently lower than the resistance R1_HRc of the resistance change element HRc in the low resistance state. In other words, it is considered that the leakage current IUS_HRc flowing into the resistance change element HRc can be suppressed by making the resistance R1_HRc of the resistance change element HRc in the low resistance state sufficiently higher than the on-resistance RON_TRc. Assuming that the resistance ratio between the on-resistance RON_TRc and the resistance R1_HRc is n (> 1), the relationship between the two resistances can be expressed as resistance R1_HRc / on-resistance RON_TRc> n. In the first to second memory cells MC1 to MC2 in the non-selected state, the leakage current IUS_HRa and current ION_TRa, and the leakage current IUS_HRb and current ION_TRb, which are pairs of the current flowing through the resistance change element and the current flowing through the transistor, The relationship is the same as the relationship between the leakage current IUS_HRc and the current ION_TRc, which is the current pair in the third-stage memory cell MC3.

In general, the resistivity of a conductor is expressed by R = ρ × L / (W × T). Here, R is the resistance value of the conductor, ρ is the resistivity of the conductor, and L is the length of the conductor in the current direction. The denominator on the right side is a cross-sectional area perpendicular to the current direction of the conductor, W is referred to as the conductor width, and T is referred to as the conductor film thickness for convenience. There are the following four methods of increasing the above-described n value, that is, increasing the resistance R1_HRc of the resistance change element HRc when the value of the on-resistance RON_TRc is used as a reference.
(Method 1) Increase the resistivity ρ of the variable resistance element.
(Method 2) Extending the length L of the variable resistance element.
(Method 3) The width W of the variable resistance element is reduced.
(Method 4) The thickness T of the variable resistance element is reduced.

  Among these, the above method 2 is invalid in the unit cell described in FIG. 19A of Patent Document 1. This is because, in the memory cell of Patent Document 1, referring to FIG. 19A, the channel layer and the resistance change film are formed on the side wall of the hole formed in the deposit in which the silicon film and the insulating film are alternately laminated. This is because they are sequentially deposited. That is, when the length L of the variable resistance element is extended, the channel length of the transistor is extended along with the length L of the variable resistance element, so that the above-described resistance ratio does not change.

  In view of the above, Method 1, Method 3, and Method 4 are promising means for realizing the resistance ratio in the non-selected cell.

  An object of the present invention is to improve the reliability of a nonvolatile memory device by preventing unintended rewriting of stored information and deterioration of the nonvolatile memory.

  The above object and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

The nonvolatile memory device according to one invention of the present application is:
Formed on a semiconductor substrate,
A plurality of first wirings extending in a first direction of the main surface of the semiconductor substrate;
A first memory cell formed on each of the plurality of first wirings and electrically connected to the first wiring;
A plurality of second wirings formed in an upper part of the first memory cell and electrically connected to the first memory cell and extending in a second direction orthogonal to the first direction;
Have
The first memory cell includes a first selection element and a variable resistance element connected in parallel.
The length of the variable resistance element in the first direction is smaller than the length of the first selection element in the first direction.

According to one invention of the present application, a method for manufacturing a nonvolatile memory device is as follows:
(A) forming a laminated film by alternately laminating N + 1 layer (N ≧ 1) first insulating films and N first semiconductor layers on a semiconductor substrate;
(B) processing the laminated film in a stripe shape in a first direction along the main surface of the semiconductor substrate to form a plurality of patterns made of the laminated film;
(C) forming a second insulating film on each side wall of the plurality of patterns;
(D) forming a second semiconductor layer on each sidewall of the plurality of patterns via the second insulating film;
(E) forming a variable resistance material layer along a side surface of the second semiconductor layer;
(F) forming a third insulating film along a side surface of the variable resistance material layer and embedding a space between the adjacent patterns;
(G) A region in which the second semiconductor layer and the variable resistance material layer are left by removing a part of the second semiconductor layer and the variable resistance material layer, and the second semiconductor layer and the variable resistance material Alternately forming regions in which the layers have been removed in the first direction;
(H) After the step (g), removing a part of the side wall in the first direction of the variable resistance material layer;
It is what has.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, the reliability of the nonvolatile memory device can be improved.

It is an overhead view of the phase change memory which is Embodiment 1 of this invention. It is an overhead view of the phase change memory which is Embodiment 1 of this invention. It is a top view which shows the cross section of a part of phase change memory which is Embodiment 1 of this invention. FIG. 4 is a cross-sectional view taken along line AA of FIG. 3 for explaining a reset operation, a set operation, and a read operation of the phase change memory according to the first embodiment of the present invention. It is a principal part overhead view of the phase change memory which is Embodiment 1 of this invention. It is an equivalent circuit diagram explaining the operation | movement of the phase change memory which is Embodiment 1 of this invention. FIG. 5 is an equivalent circuit diagram illustrating a reset operation, a set operation, and a read operation of the phase change memory according to the first embodiment of the present invention. It is an overhead view which shows the manufacturing method of the phase change memory which is Embodiment 1 of this invention. FIG. 9 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 8. FIG. 10 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 9. FIG. 11 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 10. FIG. 12 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 11. FIG. 13 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 12. FIG. 14 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 13. FIG. 15 is an overhead view illustrating a method for manufacturing the phase change memory subsequent to FIG. 14. FIG. 16 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 15. FIG. 17 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 16. FIG. 18 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 17. FIG. 19 is an overhead view for explaining a method for manufacturing the phase change memory following FIG. 18. FIG. 20 is an overhead view for explaining the method for manufacturing the phase change memory following FIG. 19. FIG. 21 is an overhead view for explaining a method for manufacturing the phase change memory following FIG. 20. FIG. 22 is an overhead view for explaining the method for manufacturing the phase change memory following FIG. 21. FIG. 23 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 22. FIG. 24 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 23. FIG. 25 is an overhead view illustrating a method for manufacturing the phase change memory following FIG. 24. FIG. 26 is a top view of the phase change memory during the manufacturing process shown in FIG. 25. It is sectional drawing in the BB line of FIG. It is sectional drawing in the CC line | wire of FIG. FIG. 26 is an overhead view for explaining the method for manufacturing the phase change memory following FIG. 25. FIG. 30 is an overhead view for explaining the method for manufacturing the phase change memory following FIG. 29. FIG. 31 is a top view of the phase change memory during the manufacturing process shown in FIG. 30. It is sectional drawing in the DD line | wire of FIG. It is sectional drawing in the EE line | wire of FIG. FIG. 31 is a cross-sectional view illustrating a method for manufacturing the phase change memory following FIG. 30. FIG. 32 is a cross-sectional view illustrating the method for manufacturing the phase change memory following FIG. 31. It is a top view which shows the cross section in the FF line | wire of FIG. FIG. 36 is a cross-sectional view illustrating the method for manufacturing the phase change memory following FIG. 35. It is a top view which shows the manufacturing method of the phase change memory which is Embodiment 2 of this invention. It is sectional drawing in the II line | wire of FIG. It is sectional drawing in the HH line | wire of FIG. It is a top view which shows the cross section in the JJ line | wire of FIG. FIG. 42 is a top view illustrating a method for manufacturing the phase change memory following FIG. 41. It is sectional drawing in the KK line | wire of FIG. It is an equivalent circuit diagram which shows the unit cell which is a comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the drawings used in the following embodiments, hatching may be partially omitted even in a cross-sectional view in order to make the drawings easy to see.

  In the drawings used in the following embodiments, even a plan view or a bird's-eye view may be partially hatched to make the drawings easy to see.

(Embodiment 1)
In the present embodiment, a memory array of vertical chain memories connected in series with a polysilicon diode as a selection element between a word line and a bit line along the main surface of a semiconductor substrate, each vertical chain memory Shows an example of a nonvolatile memory device having memory cells formed on the side walls of a stripe-shaped stacked film in which a plurality of insulating layers and gate polysilicon layers are alternately stacked.

<Basic structure of vertical chain memory>
FIG. 1 shows an overhead view of the nonvolatile memory device of the present embodiment. FIG. 1 shows a part of the memory cell array, wiring, and contact plug. Although the nonvolatile memory device of this embodiment is formed on a semiconductor substrate, the semiconductor substrate is not shown in FIG. 1, and each wiring or contact is provided in a region other than the memory cell array MA. The insulating film covering the plug is not shown.

  As shown in FIG. 1, a plurality of metal wiring layers 2 extending in a stripe shape in a direction along the main surface of a semiconductor substrate (not shown), and positioned above the metal wiring layer 2, A plurality of metal wiring layers 3 are formed which serve as bit lines extending in stripes in a direction orthogonal to the extending direction. Hereinafter, the extending direction of the metal wiring layer 2 is referred to as a first direction, and the extending direction of the metal wiring layer 3 is referred to as a second direction.

  Under each of the plurality of metal wiring layers 2, a contact plug WLC that connects the metal wiring layer 2 and a wiring selector (not shown) for selecting a specific metal wiring layer 2 is electrically connected to the metal wiring layer 2. Connected and formed. On the metal wiring layer 2, a polysilicon layer 4p doped with a p-type impurity (for example, B (boron)), a polysilicon layer 5p doped with a low-concentration impurity, and an n-type impurity (for example, P (phosphorus)) A polysilicon diode PD having a stacked structure in which polysilicon layers 6p doped with is sequentially stacked is formed. Each of the polysilicon diodes PD has a columnar shape, and a plurality of polysilicon diodes PD are arranged in a line in the first direction on the metal wiring layer 2. Since a plurality of metal wiring layers 2 are formed in stripes in the second direction, a plurality of polysilicon diodes PD on the plurality of metal wiring layers 2 are arranged in a matrix in the first direction and the second direction. ing.

  The memory cells constituting the memory array MA below the area indicated by the broken line are respectively formed immediately above the polysilicon diode PD, and have a channel polysilicon layer connecting the polysilicon diode PD and the metal wiring layer 3. The channel polysilicon layers are arranged in a matrix like the polysilicon diode PD. Although not shown, an insulating film 31 is formed between the polysilicon diodes PD adjacent in the second direction, and the channel polysilicon layer adjacent to the second direction on the insulating film 31 is formed. In the region between them, the insulating film and the conductor film are alternately laminated in order from the insulating film 31 side. The conductor films are gate polysilicon layers 21p, 22p, 23p, 24p, and 61p that function as gates of selection transistors having the channel polysilicon layer as a channel region, and each gate polysilicon layer extends in the first direction. ing. On the insulating film 31 (not shown) between the polysilicon diodes PD adjacent in the second direction, the insulating film 11, the gate polysilicon layer 21p, the insulating film 12, the gate polysilicon layer 22p, the insulating film 13, and the gate A polysilicon layer 23p, an insulating film 14, a gate polysilicon layer 24p, an insulating film 15, a gate polysilicon layer 61p, and an insulating film 71 are sequentially formed.

  In regions outside the memory array MA, wirings GL1 and GL2 for supplying power to the gate polysilicon layers 21p, 22p, 23p and 24p are provided on the gate polysilicon layers 21p, 22p, 23p and 24p of the memory cells. , GL3 and GL4 are formed. A gate line STGL1 for supplying power to the gate polysilicon layer 61p is formed on the gate polysilicon layer 61p of the selection transistor, and a gate line STGL2 is formed on the other gate polysilicon layer 61p. On the gate polysilicon layers 21p, 22p, 23p and 24p, below the wirings GL1, GL2, GL3 and GL4, the gate polysilicon layers 21p, 22p, 23p and 24p and the wirings GL1, GL2 , GL3 and GL4 are formed with contact plugs GC1, GC2, GC3 and GC4, respectively. Further, contact plugs STGC1 and STGC2 are formed to connect the gate polysilicon layer 61p and the gate wiring STGL1, and the other gate polysilicon layer 61p and the gate wiring STGL2.

  Contact plugs GLC1, GLC2, GLC3, and GLC4 (not shown) that connect the wirings GL1, GL2, GL3, and GL4 and a wiring selector (not shown) are formed below the wirings GL1, GL2, GL3, and GL4. Contact plugs STGLC1 and STGLC2 for connecting the gate lines STGL1 and STGL2 and a wiring selector (not shown) are formed below the gate lines STGL1 and STGL2, respectively. A contact plug BLC for connecting the metal wiring layer 3 and a wiring selector (not shown) is formed below the metal wiring layer 3 that is a bit line.

  Although some components, that is, the contact plug GLC4 are not shown hidden behind the wirings GL1 to GL4, the contact plugs GLC1, GLC2, and GLC3 are the same as those connected to the lower portions of the wirings GL1, GL2, and GL3, respectively. Further, the contact plug GLC4 is also connected to the lower portion of the wiring GL4. Further, the metal wiring layer 2 which is a word line is formed on an oxide deposited on a semiconductor substrate (silicon substrate) not shown in FIG. The gate polysilicon layers 21p formed side by side in a stripe shape are all electrically connected to the same wiring GL1. The same applies to the gate polysilicon layers 22p, 23p and 24p. Similarly, the gate polysilicon layer 61p of the selection transistor is also formed in a stripe shape. Of the gate polysilicon layers 61p arranged in a stripe shape, the adjacent gate polysilicon layer 61p has two gate wirings STGL1 insulated from each other. , STGL2 are connected to each other, and a voltage can be applied independently. That is, the gate polysilicon layers 61p arranged in stripes are connected to the same wiring every other line, so that the gate polysilicon layers 61p adjacent to the one gate polysilicon layer 61p are electrically connected to each other. Not connected.

  FIG. 2 is a bird's-eye view showing a part of the memory array MA in the lower part of the area indicated by a broken line in FIG. Here, the insulating film 31 embedded between the polysilicon diodes PD and between the adjacent metal wiring layers 2 is not shown.

  As shown in FIG. 2, the memory array has a polysilicon diode PD formed on the metal wiring layer 2 that is a word line, and a polysilicon diode PD on the lower side of the metal wiring layer 3 that is a bit line. And formed memory cells. The stacked films of the gate polysilicon layers 21p, 22p, 23p, 24p and 61p and the insulating films 11, 12, 13, 14, 15 and 71 are patterned in a stripe shape in a direction parallel to the metal wiring layer 2 (first direction). Has been.

  In addition, the stripe-like structure composed of the laminated film of the gate polysilicon layers 21p, 22p, 23p, 24p and 61p and the insulating films 11, 12, 13, 14, 15 and 71 is formed between the metal wiring layers 2 which are word lines. It is arranged directly above the space between. The metal wiring layer 3 which is a bit line is a stripe-shaped wiring extending in a second direction orthogonal to the first direction in which the metal wiring layer 2 extends. An n-type polysilicon layer 38p is formed on the insulating film 71. Is arranged through.

  It is a space portion between the laminated films composed of the gate polysilicon layers 21p, 22p, 23p, 24p and 61p and the insulating films 11, 12, 13, 14, 15 and 71, and is directly under the metal wiring layer 3. , Gate polysilicon layers 21p, 22p, 23p, 24p, insulating films 11, 12, 13 and 14 on the side walls and insulating film 15 below the side walls of insulating film 9, insulating film 9, gate polysilicon layer 8p, diffusion The prevention film 10 and the phase change material layer 7 are formed in this order. Diffusion prevention film 10 is a layer for preventing diffusion of impurities and the like between phase change material layer 7 and channel polysilicon layer 8p. That is, a laminated film composed of gate polysilicon layers 21p, 22p, 23p, 24p, 61p formed in a stripe shape and insulating films 11, 12, 13, 14, 15, and 71, and the adjacent laminated films An insulating film 9, a channel polysilicon layer 8p, a diffusion prevention film 10, and a phase change material layer 7 are formed in this order on the opposite side walls. Further, an insulating film 91 is embedded between the phase change material layers 7 formed on the opposing side walls of the adjacent laminated films. An insulating film 33 is embedded between the diffusion preventing film 10 and the insulating film 91 in the second direction and in a portion where the phase change material layer 7 is removed.

  Further, an insulating film 9 and a channel polysilicon layer 8p are formed in this order on the upper side wall of the insulating film 15, the gate polysilicon layer 61p, and the lower side wall of the insulating film 71, respectively. An insulating film 92 is buried between the channel polysilicon layers 8p formed on the side walls of the upper side of the film 15, the gate polysilicon layer 61p, and the lower side of the insulating film 71, respectively. An insulating film 9 and a polysilicon layer 38p are laminated on the upper side wall of the insulating film 71.

  The gate polysilicon layers 21p, 22p, 23p, 24p, 61p, the space between the stacked films of the insulating films 11, 12, 13, 14, 15 and 71, and the bottom of the metal wiring layer 3, The upper surface of silicon layer 6p is in contact with channel polysilicon layer 8p. The metal wiring layer 3 and the polysilicon diode PD are connected to the gate polysilicon layers 21p, 22p, 23p, 24p, 61p, the insulating films 11, 12, 13, 14, via the polysilicon layer 38p and the channel polysilicon layer 8p. The laminated films 15 and 71 are connected in the vicinity of the opposing side walls.

  That is, the insulating film 9 is formed on the entire side wall of the laminated film composed of the gate polysilicon layers 21p, 22p, 23p, 24p, 61p and the insulating films 11, 12, 13, 14, 15, and 71. The layer 8p has a U-shaped cross-sectional shape continuously formed over one side wall of the insulating film 9 and the upper surface of the polysilicon layer 6p. However, the uppermost end of the channel polysilicon layer 8p is located above the upper surface of the gate polysilicon layer 61p and below the upper surface of the insulating film 71. A polysilicon layer 38p is formed immediately above the uppermost end of the channel polysilicon layer 8p in contact with the channel polysilicon layer 8p. The polysilicon layer 38 p is continuously formed over one side wall and upper surface of the insulating film 9 and the upper surface of the insulating film 71, and the upper surface is in contact with the metal wiring layer 3.

  Further, the uppermost ends of diffusion preventing film 10, phase change material layer 7 and insulating film 91 are located above the upper surface of gate polysilicon layer 24p and below the lower surface of gate polysilicon layer 61p. . An insulating film 92 is embedded immediately above the diffusion prevention film 10, the phase change material layer 7, and the insulating film 91 and below the metal wiring layer 3.

  Gate polysilicon layers 21p, 22p, 23p, 24p, 61p, space portions between the laminated films made of insulating films 11, 12, 13, 14, 15, and 71, and adjacent metal wiring layers 3 The channel polysilicon layer 8p, the polysilicon layer 38p, the phase change material layer 7 and the diffusion prevention film 10 are removed immediately below the space portion between them, and the polysilicon diode PD is not formed. Although not shown in FIG. 2, an insulating film 33 is embedded in this space portion. That is, the channel polysilicon layers 8p, 38p, the phase change material layer 7, the diffusion prevention film 10, and the insulating film 91 are formed of the gate polysilicon layers 21p, 22p, 23p, 24p, 61p, the insulating films 11, 12, 13, 14, 15 and a region surrounded by an insulating film 33 embedded in the space between the stacked films and immediately below the space between the adjacent metal wiring layers 3 (hereinafter, In this embodiment, it is referred to as a “connection hole”.

  As shown in FIG. 2, the phase change material layer 7 is not formed immediately above the end portion of each polysilicon diode PD in the first direction. That is, the width of the phase change material layer 7 in the first direction is narrower than the width of the channel polysilicon film 8p in the same direction.

  FIG. 3 is a top view showing a part of the memory cell shown in FIG. 2 and a cross section taken along a plane parallel to the main surface of the semiconductor substrate including the gate polysilicon layer 21p. FIG. 3 shows two memory cells formed in two connection holes formed with the gate polysilicon layer 21p interposed therebetween.

  4 is a cross-sectional view showing one of the connection holes included in the memory cell array according to the present embodiment, and is a cross-sectional view taken along line AA of FIG. The insulating film 31 is a film that is not shown in FIG. 1 and FIG. 2 for easy understanding of the drawing, and is embedded in a space between the polysilicon diodes PD.

  As is apparent from the top view shown in FIG. 3, the characteristics of the nonvolatile memory device according to the present embodiment are the length of the phase change material layer 7 in the first direction (word line direction) (hereinafter referred to as the present embodiment). Then, the line width WGST, which is called “line width”, is shorter than the line width WSI, which is the length of the channel polysilicon layer 8p in the first direction (word line direction). Further, as shown in FIG. 3, the region between the gate polysilicon layers 21p where the insulating film 91, the phase change material layer 7, the diffusion preventing film 10, the channel polysilicon layer 8p, and the insulating film 9 are not formed. Insulating film 33 is buried. Since the line width of the phase change material layer 7 in the first direction is shorter than the line width of the channel polysilicon layer 8p, the phase change material is a region between the channel polysilicon layer 8p and the diffusion prevention film 10 and the insulating film 91. An insulating film 33 is formed in a space where the layer 7 is not formed.

  Further, when the memory cell MC indicated by the broken line in the overhead view of FIG. 2 is enlarged, the structure shown in FIG. 5 is obtained. FIG. 5 is an overhead view of a main part showing an enlarged view of one memory cell. FIG. 5 does not show the insulating films 33 and 91 and the insulating films above and below the gate polysilicon layer 21p. As shown in FIG. 5, the line width WGST narrower than the line width WSI of the channel polysilicon layer 8p, the diffusion prevention film 10 and the channel polysilicon layer 8p is formed on the side walls on both sides of the gate polysilicon layer 21p via the insulating film 9. The phase change material layers 7 having the above are respectively formed.

  As shown in FIGS. 3 to 5, one memory cell MC includes a channel polysilicon layer 8 p and a phase change material layer 7. A selection transistor that controls which of the channel polysilicon layer 8p and the phase change material layer 7 of the memory cell MC has a current flows is a gate polysilicon layer (for example, a gate polysilicon layer) formed on the side wall of the memory cell MC. 21p) and a channel polysilicon layer 8p separated from the gate polysilicon layer by the insulating film 9.

  With such a structure, the resistance value of the phase change material layer 7 in the set state can be made higher than the resistance value of the transistor in the ON state. The necessity of such dimensions will be described in detail after the operation of the vertical chain memory is described.

<Operation of vertical chain memory>
FIG. 6 is an equivalent circuit diagram of the element described in the cross-sectional view of FIG. That is, a plurality of memory cells formed in one connection hole are shown, and a plurality of memory cells connected in series and one select transistor are connected in parallel in two rows in one connection hole. Is formed. Hereinafter, the operation of the memory cell will be described with reference to FIG. In FIG. 6, a memory cell not selected (not rewritten or not read) among the memory cells surrounded by a broken line is selected as a non-selected cell USMC1, and is selected (rewritten or read). ) A memory cell is shown as a selected cell SMC.

  First, 0 V is applied to the wiring GL1 to which the selected cell SMC is connected, and the transistor whose channel is the channel polysilicon layer 8p is cut off. 5 V is applied to the wirings GL2, GL3, and GL4 to which the selected cell SMC is not connected, and the transistor is turned on. 0V is applied to the bit line BL1, and 5, 4, and 2V are applied to the word line WL1 during reset operation, set operation, and read operation, respectively. The gate polysilicon of the selection transistor applies 5V to the gate on the side connected to the selection cell SMC, that is, the gate wiring STGL1 to make the transistor conductive. 0 V is applied to the gate on the side to which the selected cell SMC is not connected, that is, the gate wiring STGL2, so that the transistor is cut off.

  In the non-selected cell USMC1, when the transistor becomes conductive, the resistance of the channel becomes low. Further, when gate line STGL1 is driven to 5V, the corresponding selection transistor is in a conductive state, and its channel polysilicon layer 8p is also in a low resistance state. In the phase change memory according to the present embodiment, as described above, the line of phase change material layer 7 is set so that the resistance value of phase change material layer 7 in the set state is sufficiently higher than the resistance value of the transistor in the conductive state. Since the width is formed narrower than the line width of the channel polysilicon layer 8p, most of the current input to the non-selected cell USMC1 flows through the transistor. Therefore, it is possible to prevent leakage current from flowing through the phase change material layer 7 in the non-selected cell USMC1, and to prevent the resistance value of the phase change material layer 7 from changing unintentionally. That is, an erroneous write operation can be avoided. In addition, since charge injection into the phase change material layer 7 is suppressed, deterioration of electrical characteristics of the phase change material layer 7, so-called fatigue can be prevented.

  On the other hand, in the selected cell SMC, since the transistor is in the cut-off state, most of the input current flows through the phase change material layer 7. In the reset operation and the set operation, the resistance value of the phase change material layer 7 is changed by the current flowing through the phase change material layer 7, and information is stored. In the read operation, the stored information is detected by separating the value of the current flowing according to the resistance value of the phase change material layer 7.

  Since the gate voltages of the transistors in the unselected cells USMC2 and USMC3 are the same as the transistors in the selected cell SMC and the unselected cell USMC1, the transistors in the unselected cell USMC2 are cut off and the transistors in the unselected cell USMC3 are conductive. State. However, since the gate line STGL2 which is the gate line is held at 0V, the corresponding selection transistor is kept in the OFF state, so that no current flows through the non-selected cells USMC2 and USMC3. From the above, it is possible to realize a selection operation in which a necessary current is applied only to the phase change material layer 7 of the selected cell SMC.

<Shape of phase change material layer>
The characteristic of the phase change material layer 7 in the vertical chain memory is that, as shown in FIGS. 3 and 5, the length of the phase change material layer 7 in the word line direction (first direction), that is, the line width WGST is the channel poly. The silicon layer 8p is at a point shorter than the line width WSI in the same direction. The purpose of such a structure is to make the resistance value of the phase change material layer 7 in the low resistance state higher than the resistance value of the transistor in the conductive state in the non-selected cell. Hereinafter, the reason why the method of narrowing the line width WGST is adopted as the means for adjusting the resistance value of the phase change material layer 7 will be described.

In general, the resistivity of a conductor is R = ρ × L / (W × T). Here, in the above formula, R is the resistance value of the conductor, ρ is the resistivity of the conductor, L is the length of the conductor in the current direction, W is the width of the conductor, and T is the film thickness of the conductor. There are four possible methods for increasing the resistance value of the variable resistance element in the low resistance state when the resistance value in the conductive state of the transistor (hereinafter referred to as the on-resistance value) is used as a reference.
(Method 1) Increase the resistivity ρ of the variable resistance element.
(Method 2) Extending the length L of the variable resistance element.
(Method 3) The width W of the variable resistance element is reduced.
(Method 4) The thickness T of the variable resistance element is reduced.

  Here, the reason why the method 2 cannot be applied to the vertical chain cell is as follows, as is apparent from FIG. 2 or FIG. That is, this memory cell is formed by sequentially depositing a channel layer and a resistance change film on the side wall of a hole formed in a deposit in which silicon films and insulating films are alternately stacked. For this reason, since the length of the phase change material layer 7 is extended together with the channel length of the transistor (the length of the channel polysilicon layer 8p), the resistance change element in the low resistance state while maintaining the on-resistance value of the transistor It is not possible to raise only the resistance value.

  Next, in Method 4, the film thickness of the variable resistance element (here, the dimension in the direction in which the bit line formed of the metal wiring layer 3 extends (second direction)) is reduced by adjusting the film forming conditions. Is easy. However, in a non-volatile memory device with a strong demand for bit cost reduction, it is important to form memory cells that occupy most of the chip area as small as possible. Therefore, the thickness of the resistance change film formed in the hole having a diameter of several tens of nanometers formed by using the most advanced processing technology is only about several nanometers (for example, about 3 nanometers). In such an extremely thin resistance change film, the resistance change phenomenon may not easily occur. Therefore, it is assumed that it will lose its effectiveness in the future.

  On the other hand, it is desirable that Method 1 is a suboptimal measure for the following reason. That is, since the resistivity ρ of the variable resistance element depends on the physical properties of the variable resistance element, it is necessary to introduce a new material corresponding to a desired resistance value in order to increase the specific resistance ρ of the variable resistance element. However, if the material of the resistance change element is changed, the operation characteristics of the memory cell may change. Therefore, it is presumed that it is difficult to rely on the new material for all the resistance value adjustments of the phase change material. Further, it is considered that it is difficult to reduce the leakage current flowing through the resistance change element only by increasing the resistivity ρ. Therefore, regardless of whether the resistivity ρ of the resistance change element is increased or not, the structural It is important to adopt a method of increasing the resistance value of the variable resistance element.

  From the above consideration, it is inevitably understood that Method 3 is preferable as a resistance value adjusting means.

<Memory cell array configuration and selection operation>
The memory cell array according to the present embodiment includes a vertical chain memory and a polysilicon diode PD formed between a bit line and a word line at each intersection of a plurality of bit lines and a plurality of word lines. Yes. In FIG. 7, the bit lines BL1, BL2, BL3, word lines WL1, WL2, WL3, wirings GL1, GL2, GL3, GL4 when performing the reset operation, set operation, and read operation of the phase change memory according to the present embodiment. The relationship between the potentials of the gate lines STGL1 and STGL2 is shown. In FIG. 7, in order to apply a forward bias only to the polysilicon diode PD in the vertical chain memory connected to the intersection of the bit line BL1 and the word line WL1 so that a necessary current flows, during the reset operation, During the set operation, the potential of the word line WL1 during the read operation is set to 5/4 / 2V as in FIG. The potential of the bit line BL1 is always 0V. Under such a voltage setting, only the selected cell SMC can be selected by performing the control described with reference to FIG. 4 in the vertical chain memory.

  Similarly, the other terminals in FIG. 7 also sequentially represent potentials during the reset operation, the set operation, and the read operation. In a vertical chain memory connected to the bit line BL2 or the bit line BL3 and connected to the word line WL1, the potential of the bit line and the word line is 5V during the reset operation, 4V during the set operation, and 2V during the read operation. There is no potential difference between the bit line and the word line, so no current flows. Further, in the vertical chain memory connected to the bit line BL1 and connected to the word line WL2 or the word line WL3, the potential of the bit line and the word line is 0 V in any of the reset operation, the set operation, and the read operation. No current flows because there is no potential difference between the bit line and the word line. Further, in the vertical chain memory connected to the bit line BL2 or the bit line BL3 and connected to the word line WL2 or the word line WL3, the word line and the bit line are respectively set to 0 V and 5 V during the reset operation, and the word line and the bit line are set during the set operation. Since 0V and 4V are applied to the bit lines, respectively, and 0V and 2V are applied to the word lines and the bit lines, respectively, in the read operation, a reverse bias direction voltage is applied to the polysilicon diode PD that selects the vertical chain memory. . Since the breakdown voltage of the polysilicon diode PD can be made larger than 5 V, the vertical chain memory arranged at the intersection of the bit lines BL2 and BL3 and the word lines WL2 and WL3 can be formed by the above voltage setting. , No large current flows. As described above, it is possible to pass a current only to a selected vertical chain memory among a plurality of vertical chain memories arranged in a matrix.

<Manufacturing method>
Hereinafter, a method for manufacturing the nonvolatile memory device according to the present embodiment will be described with reference to FIGS. 8 to 25, 29, and 30 are overhead views for explaining the method for manufacturing the nonvolatile memory device according to the present embodiment. 26, 31 and 36 are top views for explaining the method for manufacturing the nonvolatile memory device according to the present embodiment. 27, 28, 32 to 35, and 37 are cross-sectional views illustrating a method for manufacturing the nonvolatile memory device according to the present embodiment.

  First, as shown in FIG. 8, an interlayer insulating film 30, a metal wiring layer 2 serving as a word line, a p-type impurity on a semiconductor substrate 1 on which peripheral circuits (not shown) and contact plugs WLC (not shown) are formed. An amorphous silicon layer 4a doped with (for example, B (boron)), an amorphous silicon layer 5a doped with a low-concentration impurity, and an amorphous silicon layer 6a doped with an n-type impurity (for example, P (phosphorus)) are sequentially arranged. Form a film. In the sex film process at this time, for example, a CVD (Chemical Vapor Deposition) method is used.

  Next, as shown in FIG. 9, the amorphous silicon layers 4a, 5a, 6a and the metal wiring layer 2 formed in the process described with reference to FIG. 8 are processed into a stripe pattern extending in the first direction. . Since the amorphous silicon layers 4a, 5a and 6a to the metal wiring layer 2 which is the word line are collectively processed in a self-aligned manner, the metal wiring layer 2 and the amorphous silicon pillar are not aligned in the first direction. There is no misalignment between the layers, and the reliability of the memory operation can be improved. Note that the illustration of the semiconductor substrate 1 is omitted in FIGS.

  Subsequently, a space between the stripe-like stacked films formed by the process described with reference to FIG. 9 is embedded with an insulating film 31 as shown in FIG. Thereafter, the upper part of the insulating film 31 is removed and planarized by CMP (Chemical Mechanical Polishing), and then the upper surface of the amorphous silicon layer 6a is exposed as shown in FIG.

  Next, as shown in FIG. 12, the insulating film 11, the amorphous silicon layer 21a, the insulating film 12, the amorphous silicon layer 22a, the insulating film 13, the amorphous silicon layer 23a, the insulating film 14, and the amorphous silicon layer 24a are formed by CVD, for example. The insulating film 15, the amorphous silicon layer 61a, and the insulating film 71 are sequentially formed.

  Next, as shown in FIG. 13, the laminated film formed in the process described with reference to FIG. 12 is processed into a stripe shape extending in the first direction. At that time, the insulating film 11, the amorphous silicon layer 21a, the insulating film 12, the amorphous silicon layer 22a, the insulating film 13, the amorphous silicon layer 23a, the insulating film 14, the amorphous silicon layer 24a, and the insulating film 15 are provided immediately above the metal wiring layer 2. Then, processing is performed so that the stripe space portion of the laminated film composed of the amorphous silicon layer 61a and the insulating film 71 is disposed. That is, the insulating film 11, the amorphous silicon layer 21a, the insulating film 12, the amorphous silicon layer 22a, the insulating film 13, the amorphous silicon layer 23a, the insulating film 14, the amorphous silicon layer 24a, the insulating film 15, the amorphous silicon layer 61a, and the insulating film 71. The laminated film made of is disposed immediately above the insulating film 31 and is not disposed immediately above the polysilicon diode PD.

  At this time, the insulating film 11, the amorphous silicon layer 21a, the insulating film 12, the amorphous silicon layer 22a, the insulating film 13, the amorphous silicon layer 23a, the insulating film 14, the amorphous silicon layer 24a, the insulating film 15, the amorphous silicon layer 61a, and the insulating film The width in the second direction of the laminated film 71 may be narrower than the width in the same direction of the insulating film 31. With this configuration, when an insulating film 9 to be described later is formed, the width in the second direction of the space portion between the adjacent laminated films is the same as that of the amorphous silicon layers 4a, 5a, and 6a. It can be prevented from becoming narrower than the width.

  Next, as shown in FIG. 14, an insulating film 9 is formed by, for example, a CVD method so as not to completely fill the space of the stripe pattern formed in the process described with reference to FIG. Thereafter, as shown in FIG. 15, the insulating film 9 on the insulating film 71 and the insulating film 9 on the upper surface of the amorphous silicon layer 6a are removed by etch back. As a result, the insulating film 9 remains only on the sidewalls on both sides of each of the stripe patterns formed in the process described with reference to FIG.

  Next, as shown in FIG. 16, an amorphous silicon layer 8a to be a channel polysilicon layer 8p (not shown) and an insulating film 51 are formed on the entire main surface of the semiconductor substrate (not shown). The amorphous silicon layer 8a is formed by a CVD method or the like so that the space of the stripe pattern formed in the process described with reference to FIG. 13 is not completely filled, and the insulating film 51 is completely filled with the space. A film is formed by a CVD method or the like. That is, at this time, the upper surface of the amorphous silicon layer 6a is in contact with the lower surface of the amorphous silicon layer 8a, and the upper surface of the insulating film 71 is in contact with the amorphous silicon layer 8a.

  Next, as shown in FIG. 17, arsenic (As) or phosphorus (P), which is an n-type impurity, is implanted by ion implantation from a direction perpendicular to the main surface of a semiconductor substrate (not shown) for insulation. The upper part of the amorphous silicon 8a layer is doped through the film 51. The doped amorphous silicon layer 8a becomes an amorphous silicon layer 38a. The doping of As or P is performed so as not to spread below the upper surface of the amorphous silicon layer 61a. That is, the n-type impurity is implanted into the amorphous silicon layer 8a only in the region above the lower surface of the insulating film 71 in this step.

  Next, as shown in FIG. 18, the amorphous silicon layers 4a, 5a, 6a, 8a, 38a, 21a, 22a, 23a, 24a and 61a are crystallized by heat treatment and the impurities contained therein are activated. After that, the insulating film 51 is removed. The amorphous silicon layers 4a, 5a, 6a, 8a, 38a, 21a, 22a, 23a, 24a and 61a are subjected to heat treatment to form polysilicon layers 4p, 5p, 6p, channel polysilicon layers 8p, 38p, gate polysilicon, respectively. Layers 21p, 22p, 23p and 24p are formed.

Next, as shown in FIG. 19, the diffusion prevention film 10 and the phase change material layer 7 are formed on the channel polysilicon layer 8p and the polysilicon layer 38p by a CVD method or the like so that the space is not completely buried. Form in order. Here, the member of the phase change material layer 7 is preferably made of chalcogenide such as Ge ₂ Sb ₂ Te ₅ .

  Here, one of the reasons for using chalcogenide is that chalcogenide has a large amount of change in resistance value between an amorphous (non-crystalline) state and a crystalline state, and therefore, it is easy to read information stored in the phase change memory. There is a reason. This is because a memory using a phase change material such as chalcogenide has good compatibility with a diode connected as a selection element. For example, in the case of a non-volatile memory device that performs a rewrite operation by changing the direction of magnetization of a magnetic material constituting a resistance change element, such as an MRAM (Magnetoresistive Random Access Memory) that rewrites information by a spin current method, When information is rewritten by changing the direction of the current flowing through the film, a rectifying element such as a diode cannot be used as a selection element. When a field effect transistor is used instead of a diode, the area occupied by the selection element is larger than when a diode is used, which is disadvantageous for miniaturization of a semiconductor memory device.

  In contrast, in a phase change memory using a phase change material such as chalcogenide, information can be rewritten due to the difference in the magnitude of the current flowing through the phase change material constituting the resistance change element. Can be used as a selection element. That is, a phase change memory in which a diode that can be formed in a smaller area than a variable resistance field effect transistor and a memory made of chalcogenide are connected in series is advantageous for miniaturization of a nonvolatile memory device. For this reason, in this embodiment, chalcogenide is used as the material of the resistance change element of the phase change memory.

  Next, as shown in FIG. 20, an insulating film 91 is formed on the phase change material layer 7 so that the space is completely embedded. Here, as a member of the insulating film 91, it is desirable to use a coating type low dielectric constant interlayer insulating film material (SOG: Spin On Glass) so that it can be easily selectively removed later.

  Next, as shown in FIG. 21, the height of the top surface of the phase change material layer 7 is lower than the height of the top surface of the insulating film 15 and higher than the height of the bottom surface of the insulating film 15 by etch back. Thus, the phase change material layer 7 is processed. At this time, a part of the insulating film 91 is also removed at the same time, and the height of the top surface of the insulating film 91 is substantially the same as the height of the top surface of the phase change material layer 7. That is, the insulating film 91 formed above the uppermost surface of the insulating film 15 is removed, and the insulating film 91 remains only in each of the spaces.

  Making the height of the top surface of the phase change material layer 7 lower than the height of the top surface of the insulating film 15 means that when the transistor having the gate polysilicon layer 61p as a channel is cut off, the current is changed to the phase change material layer. This is to prevent a current from flowing between the source and the drain via 7. Further, the height of the uppermost surface of the phase change material layer 7 is made higher than the height of the lowermost surface of the insulating film 15 because the transistor using the gate polysilicon layer 24p formed immediately below the insulating film 15 as a channel is cut. This is to allow a current to flow through the phase change material layer 7 located between the source and drain when turned off.

  Next, as shown in FIG. 22, after the insulating film 92 formed by the CVD method or the like is buried in the space on the insulating film 91, the polysilicon layer 38p is finally formed by the CMP method as shown in FIG. Expose the top surface. Thereby, the upper surface of the insulating film 92 and the upper surface of the polysilicon layer 38p are planarized. Here, as a member of the insulating film 92, it is desirable to use a coating type low dielectric constant interlayer insulating film material (SOG) so that it can be easily selectively removed later.

  Subsequently, a contact plug BLC (not shown) for connecting a metal wiring layer 3 (see FIG. 1), which is a bit line formed in a later process, and a peripheral circuit (not shown) formed on a semiconductor substrate (not shown). 1).

  Next, as shown in FIG. 24, a metal wiring layer 3 to be a bit line is formed by sputtering, for example.

  Next, as shown in FIG. 25, the metal wiring layer 3 and the n-type polysilicon layer 38p are perpendicular to the extending direction (first direction) of the metal wiring layer 2 that is a word line (second direction). Processed into stripes extending to A plan view of the phase change memory during the manufacturing process is shown in FIG. As shown in FIG. 26, by removing the polysilicon layer 38p on the insulating film 71, main components that can be a short-circuit path between adjacent bit lines are eliminated. Note that the polysilicon layer 38p remaining between the insulating film 71 and the insulating film 92 is removed in a later step.

  27 is a cross-sectional view taken along line BB in FIG. That is, it is a cross-sectional view along the extending direction (second direction) of one metal wiring layer 3 among the metal wiring layers 3 formed in a stripe shape, and the metal wiring layer 3 is included in this cross-sectional view. ing. FIG. 28 is a cross-sectional view taken along the line CC of FIG. This sectional view is a section along the second direction and shows a section between adjacent metal wiring layers 2. As shown in FIG. 28, in the process described with reference to FIG. 25, the metal wiring layer 3 and the polysilicon layer 38p are processed until the insulating films 71 and 92 are exposed.

  Next, as shown in FIG. 29, an insulating film 101 is formed on the entire main surface of the semiconductor substrate (not shown) so as to cover the metal wiring layer 3, for example, by the CVD method, and then the insulating film 101 by the CMP method. Then, the upper surface of the insulating film 101 is planarized by removing the upper portion thereof.

  Subsequently, as shown in FIG. 30, a hard mask used as a mask for forming a plurality of vertical chain cells in the first direction is processed. That is, as shown in FIG. 30, the insulating film 101 which is a hard mask is processed by anisotropic dry etching using a photolithography technique. At this time, a plurality of openings arranged in a matrix are formed in the insulating film 101. The opening penetrates from the upper surface to the lower surface of the insulating film 101 and is formed immediately above the metal wiring layer 2 and directly above the space between the metal wiring layers 3.

  FIG. 31 is a plan view of the phase change memory during the manufacturing process shown in FIG. As can be seen by comparing FIGS. 26 and 31, the opening of the insulating film 101 is, for example, on the insulating film 92, on the polysilicon layer 38p, and on the insulating film 9, and the metal wiring layer 3 (not shown) is formed. It is formed by anisotropic dry etching immediately above a region where it is not formed. This dry etching is performed to a depth at which the insulating films 9 and 92 and the polysilicon layer 38p are exposed, as shown in FIG. 33 which is a cross-sectional view taken along the line EE of FIG. Therefore, the insulating film 101 in the state shown in FIG. 29 is made of the metal wiring layer 3 after the anisotropic dry etching, as shown in FIG. 32 which is a sectional view taken along the line DD in FIG. It is necessary that the insulating film 101 be formed on the bit line so as to remain.

  Next, as shown in FIG. 34, the insulating films 91 and 92 existing immediately below the plurality of openings formed on the upper surface of the insulating film 101 are removed by anisotropic etching. Subsequently, as shown in FIG. 35, isotropic etching is performed so that the insulating films 9, 91 (not shown) and 92 (not shown) existing immediately below the non-opening portion of the insulating film 101 remain partially. Then, the channel polysilicon layers 8p and 38p, the diffusion prevention film 10 and the phase change material layer 7 existing immediately below the opening of the insulating film 101 are removed. Here, FIG. 36 shows a top view which is a cross section taken along line FF of FIG. As shown in FIG. 36, the phase change material layer 7 and the diffusion prevention are formed in the vertical chain cell portion, that is, immediately above the metal wiring layer 2 (see FIG. 35) and directly below the metal wiring layer 3 (see FIG. 32). The film 10 is removed so as to be scraped from the side walls on both sides in the first direction directly below the opening.

  That is, the phase change material layer 7 and the diffusion preventing film 10 are isotropically etched from the region immediately below the opening (see FIG. 30) of the insulating film 101, that is, from the region immediately above the polysilicon layer 6p shown in FIG. Therefore, a part of the side wall on both sides in the first direction is removed. At this time, it is conceivable that the side walls on both sides of the channel polysilicon layer 8p in contact with the diffusion prevention film 10 are also slightly removed. However, in the isotropic etching step, the silicon layer constituting the channel polysilicon layer 8p is removed. In order to perform etching having a selection ratio that is difficult to remove and a member that constitutes the phase change material layer 7 (for example, chalcogenide), the line width of the channel polysilicon layer 8p in the first direction is the phase change material. It becomes wider than the line width of the layer 7 in the same direction.

  Therefore, as shown in FIG. 36, in the cross section along the line along the main surface of the semiconductor substrate (not shown), the planar shape of the memory cell including the phase change material layer 7, the diffusion prevention film 10, and the channel polysilicon layer 8p is From the adjacent insulating film 9 to the adjacent insulating film 91, the width in the first direction becomes narrower, for example, a trapezoidal shape. That is, the line width in the same direction of the phase change material layer 7 in contact with the insulating film 91 is smaller than the line width in the first direction of the channel polysilicon layer 8 p in contact with the insulating film 9.

  Note that the gap 110 shown in FIG. 36 is hollow. A polysilicon layer 6p is formed immediately below the gap 110, but is not shown here. By the above method, the line width of the phase change material layer 7 in the first direction can be made narrower than the line width of the channel polysilicon layer 8p in the same direction. Further, immediately below the opening (see FIG. 30) of the insulating film 101, a part of the upper surface of each of the polysilicon layer 6p and the insulating film 31 in contact with the sidewall of the polysilicon layer 6p is exposed.

  Next, as shown in FIG. 37, the polysilicon layers 4p, 5p, and 6p immediately below the opening (see FIG. 30) of the insulating film 101 are removed by anisotropic etching, thereby removing the polysilicon shown in FIG. Polysilicon diodes PD made of silicon films 4p to 5p are formed. FIG. 37 is a cross-sectional view in the same region as the line EE in FIG.

  Thereafter, although not shown, in order to prevent sublimation of the phase change material layer that has become hot during the memory rewrite operation, the opening and the space below it are filled with an insulating film 33 (see FIG. 2), and the phase change material is filled. Seal layer 7 (see FIG. 2). Here, it is desirable to apply a coating type low dielectric constant interlayer insulating film material (SOG) to the insulating film. Since SOG is excellent in embedding property, the minute gap 110 (see FIG. 36) can be completely embedded in the insulating film. In addition, since SOG has low thermal conductivity, an effect of reducing the rewriting current can be expected by increasing the heat generation efficiency in the rewriting operation.

<Effects of the present embodiment>
Here, features of the vertical chain memory will be described below.

  In a semiconductor memory device disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2008-160004), a plurality of through holes are formed in a laminated film of a conductor film and an insulating film, and a gate insulating film is formed on the inner wall of the through hole. A channel film and a phase change film are formed in this order. In such a phase change memory, the film is filled from all directions toward the center of each through hole to form a channel film and the like, so that at least the gate insulating film and the channel film have an annular planar shape. In this case, since only one row of serial memory cells can be formed in each through hole, the amount of information that can be stored per unit area is small, which is not suitable for high integration.

  On the other hand, the vertical chain memory as described in this embodiment has the following characteristics.

  The first feature is that two rows of memory cells can be formed inside the connection hole. More specifically, as shown in FIG. 3, the phase change material layer 7 formed inside the connection hole includes a first region in contact with the surface of one channel polysilicon layer 8p, an insulating film It is formed separately from the second region in contact with the surface of the other channel polysilicon layer 8p facing each other across 91. That is, two memory cells made of the phase change material layer 7 in contact with the channel polysilicon layer 8p through the channel polysilicon layer 8p and the diffusion prevention film 10 are formed in one connection hole. In addition, two transistors for controlling current paths flowing through the two phase change material layers 7 are provided in one connection hole, and currents flowing through the left and right phase change material layers 7 are independently controlled. It has a configuration. With such a configuration, by cutting off the transistor formed on one surface, a large current flows in the first region of the phase change material layer 7, but it is formed on the other surface facing each other. By holding the transistor in a conductive state, it is possible to prevent current from flowing through the second region. Therefore, it is possible to store 2 bits more than the memory cell of Patent Document 1, which has the effect of being able to store twice as much in one connection hole, and the bit cost can be reduced.

  The second feature is that the number of memory cells controlled by the selection element is doubled. As can be seen from FIG. 3, two vertical chain memories are connected to one polysilicon diode PD (see FIG. 2) in one connection hole. The polysilicon diode PD has a function of selecting a vertical chain memory to be connected depending on a potential relationship between a word line made of the metal wiring layer 2 (see FIG. 2) and a bit line made of the metal wiring layer 3 (see FIG. 2). Have. Therefore, in the vertical chain memory as in the present embodiment, the two vertical chain memories are configured to share one diode. With this configuration, the number of bits for one polysilicon diode PD can be increased, and the bit cost can be reduced.

  The third feature is that each layer formed in the connection hole has an effect of increasing the density of cells per unit area by forming a structure in contact with the insulating layer that separates the connection holes in the first direction. is there. That is, the phase change material layer 7 and the like are formed on the side surface of the gate polysilicon layer 21p shown in FIG. 3, but the direction in which the thickness of the film increases due to crystal growth is between the adjacent gate polysilicon layers 21p. This is the direction in which the two opposing surfaces face each other. The film formed on the side wall of the gate polysilicon layer 21p is formed only in the direction of filling between the two facing surfaces. As a result, unlike the memory cell of Patent Document 1, no film is formed in the direction of filling from all directions toward the center of the hole. In other words, the direction in which the thickness of the film increases due to crystal growth is only the direction in which the two faces face each other. There is no need to set and process. Therefore, the perpendicular direction does not depend on the thickness of the film to be formed, and can be formed with the minimum processing dimension. That is, the bit cost can be reduced by improving the cell density per unit area.

  The characteristics of the vertical chain memory in which two rows of memory cells are formed in one connection hole have been described above. However, in the vertical chain memory having the above three characteristics, as described above, the width of the resistance change element It is difficult to increase the resistance value of the resistance change element by narrowing and to prevent leakage current from flowing through the resistance change element in the non-selected memory cell.

  On the other hand, in this embodiment, after forming the matrix-shaped opening formed in the insulating film 101 shown in FIG. 30, an opening reaching the upper part of the polysilicon layer 6p from the opening (see FIG. 35) is formed. Then, the above problem is solved by selectively removing a part of the side wall of the phase change material layer 7 by isotropic etching. Note that the isotropic etching is isotropic etching, for example, wet etching having a selection ratio such that the silicon oxide film is hardly removed.

  Thus, as shown in FIG. 3, the resistance of the phase change material layer 7 is reduced by making the line width of the phase change material layer 7 formed inside the connection hole narrower than the line width of the channel polysilicon layer 8p. Since the value can be increased, a more ideal selection operation can be realized. That is, with this configuration, the set resistance of the phase change material layer 7 in the low resistance state can be set higher than the resistance of the transistor in the conductive state. As a result, when a memory cell formed on one surface in the connection hole is selected, a large current flows through the phase change material layer 7 in the selected cell by cutting off the transistor. In the selected cell, it is possible to prevent a current from flowing through the phase change material layer 7 by turning on the transistor. That is, by making it possible to suppress the amount of charge injected into the phase change material layer 7 in the non-selected cell, the storage information retention time can be improved, and further deterioration of electrical characteristics can be prevented. Therefore, the reliability of the nonvolatile memory device including the vertical chain memory having the above three characteristics can be improved.

(Embodiment 2)
In the present embodiment, an example of a manufacturing method for reducing the line width of the phase change material layer 7 shown in FIG. 2 and different from the first embodiment will be described. In the manufacturing method described here, the phase-change material layer 7 is selected after separating the vertical chain cell and the polysilicon diode PD aligned in the direction (first direction) in which the word line made of the metal wiring layer 2 extends. The characteristic feature is that the phase change material layer 7 is thinned mainly by the selective etching.

  First, the manufacturing method up to the formation of a hard mask used when separating the vertical chain cell and the polysilicon diode PD adjacent to each other in the direction in which the word line made of the metal wiring layer 2 extends is described in the first embodiment. As described with reference to FIGS. Subsequently, after the process described with reference to FIG. 33, as shown in FIGS. 38 and 39, the insulating films 91, 92, and 9, the diffusion prevention film 10, and the polysilicon layer 4p existing immediately below the opening of the insulating film 101 are formed. 5p, 6p, 8p, 38p and the phase change material layer 7 are removed. FIG. 38 is a plan view of the phase change memory during the manufacturing process, and FIG. 39 is a cross-sectional view taken along the line II of FIG. 40 is a cross-sectional view taken along the line HH in FIG.

  Here, since the insulating film 9 is removed, the insulating film 31 that separates the polysilicon diode composed of the polysilicon layers 4p to 6p is also slightly removed. Further, the thickness of the insulating film 101 from the upper surface of the metal wiring layer 3 shown in FIG. 29 to the upper surface of the insulating film 101 is set so as to protect the metal wiring layer 3 shown in FIGS. Needs to be controlled to a thickness that remains on the metal wiring layer 3 (see FIG. 40). Therefore, the remaining insulating film 101 in FIG. 39 is thicker than the remaining insulating film 101 in FIG. Moreover, the top view in the cross section of the JJ line of FIG. 40 becomes like FIG.

  That is, as shown in FIG. 41, for example, between the adjacent gate polysilicon layers 21p, the insulating film 9 and the channel poly are formed from one surface to the other surface of the opposing gate polysilicon layers 21p. The region where the silicon layer 8p, the diffusion preventing film 10, the phase change material layer 7, the insulating film 91, the phase change material layer 7, the diffusion preventing film 10, the channel polysilicon layer 8p, and the insulating film 9 are formed in this order is the first. It is formed intermittently in the direction. That is, between the adjacent gate polysilicon layers 21p, there are only a region where the insulating film 91, the phase change material layer 7, the diffusion prevention film 10, the channel polysilicon layer 8p and the insulating film 9 are formed, and a gap. A certain region is alternately formed in the first direction, and the polysilicon layers 4p to 6p are not formed in the region immediately below the gap, but the metal wiring layer 2 is formed.

  Next, the phase change material layer 7 is selectively removed by isotropic etching. As a result, the top view of the cross section at the same position as in FIG. 41 is as shown in FIG. 42, the gaps 111 formed at both ends of the phase change material layer 7 correspond to the portions from which the phase change material layer 7 has been removed. A silicon layer 8p is formed. In FIG. 42, illustration of the diffusion prevention film 10 and the channel polysilicon layer 8p immediately below the gap 111 is omitted.

  Here, FIG. 43 shows a cross-sectional view taken along the line KK of FIG. FIG. 43 is a cross-sectional view along the second direction including the end of the channel polysilicon layer 8p in the first direction. As shown in FIG. 43, the phase change material layer 7 is selectively removed, and voids 111 are formed in the region. In FIG. 43, the phase change material layer 7 having a narrow line width is formed in the back of the gap 111, but the phase change material layer 7 is not shown for easy understanding of the drawing.

  Thereafter, in order to prevent sublimation of the phase change material layer that has become hot during the memory rewrite operation, the opening and the gap 111 are filled with an insulating film (not shown), and the phase change material layer 7 is sealed. At this time, it is desirable to apply a coating type low dielectric constant interlayer insulating film material (SOG) to the insulating film. Since SOG is excellent in embedding property, the minute gap 111 can be completely embedded in the insulating film. In addition, since the thermal conductivity of SOG is low, an effect of reducing the rewriting current can be expected by increasing the heat generation efficiency in the rewriting operation.

  42, the phase change material layer 7 can be selectively removed as shown in FIG. 42, and the line width of the phase change material layer 7 can be reduced while maintaining the line width of the polysilicon layer 38p. It is possible to make it thinner. As described above, the channel polysilicon layer 8p is prevented from being removed and the phase change material layer 7 is selectively thinned in that the line width of the channel polysilicon layer 8p can be more reliably maintained. More preferable than the configuration of the first embodiment.

  As described above, in the nonvolatile memory device of this embodiment, the set resistance of the phase change material layer 7 can be significantly higher than the resistance of the transistor in the conductive state, and an ideal selection operation can be realized. it can. Therefore, the reliability of the nonvolatile memory device can be improved.

  Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the first and second embodiments have been described on the premise of a phase change memory using a chalcogenide material as a storage element. However, the material of the storage element is not limited, and the magnetoresistive random access is not limited to the phase change memory. -It is also possible to apply to various semiconductor memories such as a memory (MRAM) or other resistive memory whose electrical characteristics change by passing a current through the element.

  The first and second embodiments have been described on the assumption that polysilicon is used for the gate polysilicon layer for performing the gate operation and the channel polysilicon layer for the source / drain path. The material of the polysilicon layer is not limited, and the present invention can be realized by applying a conductor such as a semiconductor material capable of performing a gate operation.

  Further, in the first and second embodiments, the expressions “word line” and “bit line” are used for easy understanding, but both are selection lines used to select one vertical chain memory. Therefore, the positional relationship or the like may be upside down, and needless to say, it is not necessary to connect a read circuit such as a sense amplifier to the bit line side.

  The method for manufacturing a nonvolatile memory device of the present invention is widely used for nonvolatile memory devices having a resistance change element formed adjacent to a channel of a selection transistor.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Metal wiring layer 3 Metal wiring layers 4a-6a Amorphous silicon layers 4p-6p Polysilicon layer 7 Phase change material layer 8a Amorphous silicon layer 8p Channel polysilicon layer 9 Insulating film 10 Diffusion prevention films 11-15 Insulating film 21a -24a Amorphous silicon layers 21p-24p Gate polysilicon layer 30 Interlayer insulating films 31-33 Insulating film 38a Amorphous silicon layer 38p Polysilicon layer 51 Insulating film 61a Amorphous silicon layer 61p Gate polysilicon layer 71 Insulating films 91, 92 Insulating film 101 Insulating film 110, 111 Air gap BL Bit line BL1-BL3 Bit line BLC Contact plug GC1-GC4 Contact plug GL1-GL4 Wiring GLC1-GLC4 Contact plug HRa-HRd Resistance change element HRk Resistance change element ILK_TRd Leakage current ION_TRa Current ION_TRb Current ION_TRc Current IRST Reset current IRST_HRd Current IUS_HRa Leakage current IUS_HRb Leakage current IUS_HRc Leakage current MA Memory array MC Memory cell MC1 to MC4 Memory cell MCj Memory cell PD Polysilicon diode R Resistance c Resistance R1 Resistance R Source line SMC Selected cell STGC1, STGLC2 Contact plug STGL1 Gate wiring STGL2 Gate wiring T Film thickness TRa to TRd Transistor TRe Vertical transistor TRk Transistor USMC1 Non-selected cell USMC2 Non-selected cell USMC3 Non-selected cell W Width WGST Line width WL1-WL3 Word Line WLC Contact plug WSI Line width ρ Anti-rate

Claims (18)

Formed on a semiconductor substrate,
A plurality of first wirings extending in a first direction of the main surface of the semiconductor substrate;
A first memory cell formed on each of the plurality of first wirings and electrically connected to the first wiring;
A plurality of second wirings formed in an upper part of the first memory cell and electrically connected to the first memory cell and extending in a second direction orthogonal to the first direction;
Have
The first memory cell includes a first selection element and a variable resistance element connected in parallel.
A length of the variable resistance element in the first direction is smaller than a length of the first selection element in the first direction. A plurality of the first memory cells are formed in each of the spaces where the plurality of first wirings and the plurality of second wirings intersect in a plane,
2. The nonvolatile memory device according to claim 1, wherein the plurality of first memory cells are connected in series between each of the plurality of first wirings and each of the plurality of second wirings. The variable resistance element extends in a direction perpendicular to a main surface of the semiconductor substrate;
The nonvolatile memory device according to claim 1, wherein the first direction and the second direction are directions along a main surface of the semiconductor substrate.   The nonvolatile memory device according to claim 1, wherein the variable resistance element includes chalcogenide. The first memory cell has a second memory cell and a third memory cell connected in parallel;
2. The nonvolatile memory device according to claim 1, wherein each of the second memory cell and the third memory cell includes the variable resistance element and the first selection element.   2. The nonvolatile memory device according to claim 1, wherein the first direction and the second direction are orthogonal to a third direction which is a direction perpendicular to a main surface of the semiconductor substrate. N (N is a natural number) fourth memory cells are further formed between the first wiring and the second memory cell and between the first wiring and the third memory cell. ,
6. The nonvolatile memory device according to claim 5, wherein each of the fourth memory cells includes the variable resistance element and the first selection element. A second selection element is formed between the plurality of first wirings, the second memory cell, and the third memory cell;
A third selection element is formed between the second memory cell and the second wiring;
6. The nonvolatile memory device according to claim 5, wherein a fourth selection element is formed between the third memory cell and the second wiring.   9. The nonvolatile memory device according to claim 8, wherein the second selection element is a diode. Formed on a semiconductor substrate,
A plurality of first wirings extending in a first direction of the main surface of the semiconductor substrate;
A plurality of second wirings formed on top of the plurality of first wirings and extending in a second direction orthogonal to the first direction;
The plurality of first wirings and the plurality of second wirings are formed in a space intersecting in a plane, and extend between each of the plurality of first wirings and each of the plurality of second wirings. A variable resistance material layer;
A first semiconductor film formed in a space where the plurality of first wirings and the plurality of second wirings intersect in a plane, and extending along the first variable resistance material layer;
A third wiring disposed between the plurality of first wirings and the plurality of second wirings and extending in the first direction;
Have
The non-volatile memory device, wherein a length of the first variable resistance material layer in the first direction is smaller than a length of the first semiconductor film in the first direction.   11. The non-volatile device according to claim 10, wherein a plurality of the third wirings are formed along the first semiconductor film between the plurality of first wirings and the plurality of second wirings. Storage device. The first variable resistance material layer extends in a direction perpendicular to a main surface of the semiconductor substrate;
The first direction and the second direction are directions along a main surface of the semiconductor substrate,
The third wiring is disposed immediately above a region between each of the plurality of first wirings formed immediately below the first variable resistance material layer and the plurality of first wirings adjacent to each other. The nonvolatile memory device according to claim 10.   The nonvolatile memory device according to claim 10, wherein the first variable resistance material layer includes chalcogenide. The first variable resistance material layer includes a second variable resistance material layer and a third variable resistance material layer extending between each of the plurality of first wirings and each of the plurality of second wirings;
The first semiconductor film includes a second semiconductor film extending along the second variable resistance material layer, and a third semiconductor film extending along the third variable resistance material layer,
The non-volatile memory device according to claim 10, wherein the third wiring is also formed on the opposite side across the first semiconductor film. A stack of a semiconductor film having a first conductivity type and a semiconductor film having a second conductivity type formed between the plurality of first wirings, the second resistance change material layer, and the third resistance change material layer. A membrane,
A fourth wiring formed between the third wiring and the plurality of second wirings;
Have
The second variable resistance material layer and the third variable resistance material layer are not formed at the same height as the fourth wiring, and the second semiconductor film and the third semiconductor film are formed. 15. The non-volatile memory device according to claim 14, wherein (A) forming a laminated film by alternately laminating N + 1 layer (N ≧ 1) first insulating films and N first semiconductor layers on a semiconductor substrate;
(B) processing the laminated film in a stripe shape in a first direction along the main surface of the semiconductor substrate to form a plurality of patterns made of the laminated film;
(C) forming a second insulating film on each side wall of the plurality of patterns;
(D) forming a second semiconductor layer on each sidewall of the plurality of patterns via the second insulating film;
(E) forming a variable resistance material layer along a side surface of the second semiconductor layer;
(F) forming a third insulating film along a side surface of the variable resistance material layer and embedding a space between the adjacent patterns;
(G) A region in which the second semiconductor layer and the variable resistance material layer are left by removing a part of the second semiconductor layer and the variable resistance material layer, and the second semiconductor layer and the variable resistance material Alternately forming regions in which the layers have been removed in the first direction;
(H) After the step (g), removing a part of the side wall in the first direction of the variable resistance material layer;
A method for manufacturing a non-volatile memory device. (A1) Before the step (a), a fourth insulating film, a first conductive layer, a first conductive type third semiconductor layer, and a second conductive type fourth semiconductor layer are sequentially stacked on the semiconductor substrate. Process,
(A2) before the step (a), processing the first conductive layer, the third semiconductor layer, and the fourth semiconductor layer in a stripe shape in the first direction;
Further comprising
In the step (g), by removing a part of the third semiconductor layer and the fourth semiconductor layer, the second semiconductor layer, the variable resistance material layer, the third semiconductor layer, and the fourth semiconductor layer And a region from which the second semiconductor layer, the variable resistance material layer, the third semiconductor layer, and the fourth semiconductor layer are removed are alternately formed in the first direction. Item 17. A method for manufacturing a nonvolatile memory device according to Item 16. (F1) forming a second conductive layer electrically connected to the second semiconductor layer on the second semiconductor layer after the step (f) and before the step (g); ,
(F2) processing the second conductive layer into a stripe shape in a second direction orthogonal to the first direction;
(F3) After the step (f2), after forming the fifth insulating film thicker than the second conductive layer so as to cover the second conductive layer, the upper surface of the fifth insulating film is flattened. And the process of
(F4) By removing the fifth insulating film at a position where the space portions of the first conductive layer formed in a stripe shape and the second conductive layer formed in a stripe shape overlap in a plane, Forming a mask used when removing a part of the second semiconductor layer and the variable resistance material layer in the step (g);
The method of manufacturing a nonvolatile memory device according to claim 16, comprising:

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