CN112436088A - Memristor-based micro sustainable chip heat dissipation structure and preparation method - Google Patents
Memristor-based micro sustainable chip heat dissipation structure and preparation method Download PDFInfo
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- 230000017525 heat dissipation Effects 0.000 title claims abstract description 49
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 239000000110 cooling liquid Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 230000007306 turnover Effects 0.000 claims description 11
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 235000011149 sulphuric acid Nutrition 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000009616 inductively coupled plasma Methods 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 239000010955 niobium Substances 0.000 claims description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 3
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- -1 tungsten nitride Chemical class 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 238000009776 industrial production Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 35
- 239000007789 gas Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical group [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 241000218993 Begonia Species 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 229910000366 copper(II) sulfate Inorganic materials 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000013456 study Methods 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
- H10N70/8613—Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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Abstract
The invention provides a memristor-based micro sustainable chip heat dissipation structure and a preparation method thereof, wherein the heat dissipation structure comprises a bottom electrode, an overturning substrate, a barrier layer and a substrate layer which are sequentially attached from top to bottom, wherein the substrate layer is provided with a wire heat dissipation channel, and the heat dissipation structure also comprises a cooling liquid pipeline which is vertical to the wire heat dissipation channel; the invention also provides a corresponding preparation method of the heat dissipation structure; the heat dissipation structure provided by the invention has good heat conductivity and stability, the memristor attached to the heat dissipation structure is more stable in resistance state, and the heat dissipation structure can be used for heat dissipation of a memristor network and has a wide application prospect; in addition, the preparation method of the memristor is simple, convenient and efficient, has low cost, and can be widely applied to industrial production.
Description
Technical Field
The invention relates to the technical field of integrated circuit heat dissipation, in particular to a micro sustainable chip heat dissipation structure based on a memristor and a preparation method.
Background
The memristor is a fourth kind of passive element except for resistance, capacitance and inductance, and is a passive circuit element related to magnetic flux and electric charge. As early as 1971, professor zeisure studys theorizes the existence of memristors based on circuit theory. In 2008, a memristor prototype device is first constructed experimentally in a Hewlett packard laboratory, and the theory of the Chua begonia on the memristor is verified. The memristor has novel nonlinear electrical properties, has the characteristics of high density, small size, low power consumption, non-volatility and the like, and is considered as an ideal scheme for developing a next generation of novel non-volatile memory. The first object of the memristor is a sandwich structure, the top electrode and the bottom electrode are made of inert metal, and the resistance change mechanism is based on titanium dioxide doped with oxygen holes. In recent years, the resistive layer of memristors is being replaced by some materials with superior performance.
At present, as the size of the memristor is continuously reduced, adverse effects caused by the electrothermal effect of the memristor are highlighted, the adverse effects can change the material structure and the chemical properties of the functional layer of the memristor, the power consumption of the functional layer of the memristor is increased, and the operation result deviates from the design expectation. Some heat dissipation structures have been proposed, which have the characteristics of higher heat dissipation efficiency, lower technical requirements and manufacturing cost, etc. The metal wire has good thermal conductivity, and the heat dissipation of the circuit under various sizes can be realized by changing the topological structure of the metal wire in the circuit. This technology has been applied to complementary metal oxide field effect transistors (CMOS). However, the microstructure of the memristor for heat dissipation is relatively rare due to the limitations of the process critical dimension and the application. In addition, how to design reasonable memristor network heat dissipation structure also needs to be explored to reduce the energy consumption of the memristor and improve the working efficiency of the memristor.
Disclosure of Invention
The purpose of the invention is as follows: in order to solve the problems in the background art, the invention provides a micro sustainable chip heat dissipation structure based on a memristor and a preparation method thereof.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:
the miniature sustainable chip heat dissipation structure comprises a bottom electrode, a turnover substrate, a barrier layer and a substrate layer, wherein the bottom electrode, the turnover substrate, the barrier layer and the substrate layer are sequentially attached from top to bottom, and the substrate layer is provided with a bottom electrode wire heat dissipation channel and a condensate circulation channel.
Further, the longitudinal depth of the wire heat dissipation channel along the substrate layer is greater than the transverse depth, and the range of the transverse-longitudinal ratio is 1: 10-1: 20, the bottom electrode is one of aluminum, molybdenum, niobium, copper, gold, palladium, platinum, tantalum, ruthenium oxide, silver, tantalum nitride, titanium nitride, tungsten and tungsten nitride.
Furthermore, the bottom of the substrate layer is also provided with a cooling liquid pipeline, and the cooling liquid pipeline is perpendicular to the wire heat dissipation channel.
Further, the barrier layer is a gallium nitride barrier layer.
Further, the turnover substrate is made of one of titanium, aluminum, nickel and gold.
Furthermore, the bottom electrode leads are distributed in a mutually crossed fin shape, and the thickness of the leads in the fin-shaped area does not exceed that of the bottom electrode.
A method for adopting the micro sustainable chip heat dissipation structure based on the memristor comprises the following steps:
step S1, depositing a layer of SiO2 plasma on the pure silicon substrate by a vapor deposition method to be used as an etching mask;
s2, opening a plurality of staggered gap patterns in the SiO2 etching mask plate by a chemical etching method in an inductively coupled plasma etching mode according to a preset pattern;
s3, stripping the residual photoresist by using plasma, and sequentially etching SiO2 etching mask and barrier layer along the longitudinal direction until the pure silicon-based substrate layer is reached;
step S4, placing the chip in a KOH solution with the temperature of 60 ℃ and the mass ratio of 40% to soak for 5 minutes, and removing the residual barrier layer material in the slits for further etching the silicon slits;
step S5, using isotropic XeF2 gas etching to further etch the silicon slits and enlarge the micro-channels in the silicon; specifically, the XeF2 gas etch is performed in a pulsed manner: exposing the sample to be etched to XeF2 under controlled pressure and then evacuating the etch chamber; repeating the process several times until the desired channel width is obtained; the channel is a wire heat dissipation channel;
s6, using electron beam evaporation deposition to turn over the substrate to realize ohmic contact, and carrying out lift-off photoetching and annealing on the turned-over substrate; etching the inlet and outlet channels to the back of the chip until the channels are merged from the heat dissipation holes and the bottom layer condensate flow channel;
s7, depositing a uniform chromium-copper seed crystal layer on the top of the turnover substrate in an electron beam evaporation mode; immersing the chip into H2SO4 solution to remove a surface oxide layer; defining a region to be electroplated based on a preset pattern and electroplating;
step S8, stripping the photoresist, and selectively etching the bottom electrode layer by adopting short copper wet etching; the photoresist covering the bottom electrode was removed using a dicing saw to form the bottom electrode pattern, form the bottom electrode, and mount the memristor above.
The invention has the beneficial effects that: the structure of an electrode and a substrate is changed on the design of a bottom electrode structure of a memristor crossbar structure, meanwhile, cooling liquid is added into the substrate to accelerate heat transfer, the memristor crossbar structure has the advantages of being high in heat dissipation performance and temperature control performance, simple to operate, low in cost, beneficial to large-scale application, capable of improving the performance of the memristor crossbar structure and expanding the application of the memristor crossbar structure.
Drawings
FIG. 1 is a flow chart for preparing a micro sustainable chip heat dissipation structure based on memristors, provided by the present invention;
FIG. 2 is a top view of a micro sustainable chip heat dissipation structure based on memristors provided by the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
The invention provides a memristor-based micro sustainable chip heat dissipation structure which comprises a bottom electrode, an overturning substrate, a barrier layer and a substrate layer, wherein the bottom electrode, the overturning substrate, the barrier layer and the substrate layer are sequentially attached to one another from top to bottom. Wherein the substrate layer is equipped with wire heat dissipation channel, and wire heat dissipation channel is greater than horizontal degree of depth along the longitudinal depth of substrate layer, and the horizontal-longitudinal ratio scope is 1: 10-1: 20, the preferred embodiment of the present invention is 1: 16. and a cooling liquid pipeline is also arranged at the bottom of the substrate layer and is perpendicular to the wire heat dissipation channel. The barrier layer is preferably a gallium nitride barrier layer. The overturning substrate is made of one of titanium, aluminum, nickel and gold. The bottom electrode is made of one of aluminum, molybdenum, niobium, copper, gold, palladium, platinum, tantalum, ruthenium oxide, silver, tantalum nitride, titanium nitride, tungsten and tungsten nitride.
The bottom electrode leads are shaped in an interdigitated fin-like arrangement as shown in fig. 2. Wherein the conductive line thickness of the fin region does not exceed the bottom electrode thickness.
The preparation method of the memristor-based micro sustainable chip heat dissipation structure is shown in fig. 1. The method specifically comprises the following steps:
and step S1, depositing a layer of SiO2 plasma on the pure silicon-based substrate by a vapor deposition method to be used as an etching mask.
And S2, opening a plurality of staggered slit patterns in the SiO2 etching mask plate according to a preset pattern by using a C4F8 chemical method and an inductively coupled plasma etching mode.
And S3, stripping the photoresist by using O2 plasma, and sequentially etching the SiO2 etching mask and the barrier layer along the longitudinal direction until the pure silicon-based substrate layer is reached. The etching method here may use a chemical method of Cl2+ Ar.
And step S4, placing the chip in 40% KOH solution at the temperature of 60 ℃ for soaking for 5 minutes, and removing the residual barrier layer material in the slits for further etching the silicon slits.
Step S5, using isotropic XeF2 gas etching to further etch the silicon slits and enlarge the micro-channels in the silicon; specifically, the XeF2 gas etch is performed in a pulsed manner: exposing the sample to be etched to XeF2 under controlled pressure and then evacuating the etch chamber; repeating the process several times until the desired channel width is obtained; the channel is a wire heat dissipation channel;
s6, using electron beam evaporation deposition to turn over the substrate to realize ohmic contact stacking, and carrying out lift-off photoetching and annealing on the turned-over substrate; and etching the inlet channel and the outlet channel to the back of the chip until the channels are combined from the two sides of the heat dissipation holes and the bottom layer condensate liquid circulation channel.
And step S7, depositing a uniform chromium-copper seed crystal layer on the top of the turnover substrate by adopting an electron beam evaporation mode. Immersing the chip into H2SO4 solution to remove a surface oxide layer; and defining a region to be electroplated based on the preset pattern and electroplating. Specifically, the electroplating method employs a CuP anode in a solution containing CuSO4, H2SO4, and Cl "using a galvanostat.
Step S8, stripping the photoresist, and selectively etching the bottom electrode layer by using short copper wet etching; the dies were separated using a dicing saw, the bottom electrode was formed, and the memristor was mounted above.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (7)
1. The micro sustainable chip heat dissipation structure based on the memristor is characterized by comprising a bottom electrode, a turnover substrate, a barrier layer and a substrate layer, wherein the bottom electrode, the turnover substrate, the barrier layer and the substrate layer are sequentially attached to each other from top to bottom, and the substrate layer is provided with a bottom electrode lead heat dissipation channel and a condensate liquid circulation channel.
2. The memristor-based micro sustainable chip heat dissipation structure according to claim 1, wherein the longitudinal depth of the wire heat dissipation channel along the substrate layer is greater than the transverse depth, and the transverse-longitudinal ratio ranges from 1: 10-1: 20, the bottom electrode is one of aluminum, molybdenum, niobium, copper, gold, palladium, platinum, tantalum, ruthenium oxide, silver, tantalum nitride, titanium nitride, tungsten and tungsten nitride.
3. The memristor-based micro sustainable chip heat dissipation structure as claimed in claim 1, wherein a cooling liquid pipe is further arranged at the bottom of the substrate layer, and the cooling liquid pipe is perpendicular to the wire heat dissipation channel.
4. The micro sustainable chip heat dissipation structure of claim 1, wherein the barrier layer is a gan barrier layer.
5. The memristor-based micro sustainable chip heat dissipation structure as claimed in claim 1, wherein the flip substrate is made of one of titanium, aluminum, nickel and gold.
6. The memristor-based micro sustainable chip heat dissipation structure as claimed in claim 1, wherein the bottom electrode wires are distributed in a shape of mutually crossed fin-shaped wires, and the wire thickness of the fin-shaped area does not exceed the bottom electrode thickness.
7. A method for preparing the micro sustainable chip heat dissipation structure based on the memristor according to any one of claims 1-6, the method comprising the following steps:
step S1, depositing a layer of SiO2 plasma on the pure silicon substrate by a vapor deposition method to be used as an etching mask;
s2, opening a plurality of staggered gap patterns in the SiO2 etching mask plate by a chemical etching method in an inductively coupled plasma etching mode according to a preset pattern;
s3, stripping the residual photoresist by using plasma, and sequentially etching SiO2 etching mask and barrier layer along the longitudinal direction until the pure silicon-based substrate layer is reached;
step S4, placing the chip in a KOH solution with the temperature of 60 ℃ and the mass ratio of 40% to soak for 5 minutes, and removing the residual barrier layer material in the slits for further etching the silicon slits;
step S5, using isotropic XeF2 gas etching to further etch the silicon slits and enlarge the micro-channels in the silicon; specifically, the XeF2 gas etch is performed in a pulsed manner: exposing the sample to be etched to XeF2 under controlled pressure and then evacuating the etch chamber; repeating the gas etching several times until a desired channel width is obtained; the channel is a wire heat dissipation channel;
s6, using electron beam evaporation deposition to turn over the substrate to realize ohmic contact, and carrying out lift-off photoetching and annealing on the turned-over substrate; etching the inlet and outlet channels to the back of the chip until the channels are merged from the heat dissipation holes and the bottom layer condensate flow channel;
s7, depositing a uniform chromium-copper seed crystal layer on the top of the turnover substrate in an electron beam evaporation mode; immersing the chip into H2SO4 solution to remove a surface oxide layer; defining a region to be electroplated based on a preset pattern and electroplating;
step S8, stripping the photoresist, and selectively etching the bottom electrode layer by adopting short copper wet etching; the photoresist covering the bottom electrode was removed using a dicing saw to form the bottom electrode pattern, form the bottom electrode, and mount the memristor above.
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| CN113990826A (en) * | 2021-10-26 | 2022-01-28 | 山东大学 | Near-junction heat dissipation method of silicon-based gallium nitride device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112864317A (en) * | 2021-03-11 | 2021-05-28 | 长江先进存储产业创新中心有限责任公司 | Three-dimensional memory and forming method thereof |
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| CN113990826A (en) * | 2021-10-26 | 2022-01-28 | 山东大学 | Near-junction heat dissipation method of silicon-based gallium nitride device |
| CN113990826B (en) * | 2021-10-26 | 2022-11-29 | 山东大学 | Near-junction heat dissipation method for silicon-based gallium nitride device |
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