CN113113476A - GaN HEMT device suitable for low-working-voltage high-efficiency application and preparation method thereof - Google Patents
GaN HEMT device suitable for low-working-voltage high-efficiency application and preparation method thereof Download PDFInfo
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- 238000001312 dry etching Methods 0.000 claims abstract description 15
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- 238000000059 patterning Methods 0.000 claims abstract description 12
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- 230000004888 barrier function Effects 0.000 claims description 30
- 229910015844 BCl3 Inorganic materials 0.000 claims description 22
- 238000000137 annealing Methods 0.000 claims description 8
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
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Abstract
The invention relates to a GaN HEMT device suitable for low working voltage and high efficiency application and a preparation method thereof, wherein the method comprises the following steps of S1: growing a GaN-based heterojunction on a substrate; s2: growing n on GaN-based heterojunctions+A GaN cap layer; s3: adopting Cl-based plasma dry etching process to n+Carrying out graphical self-termination etching on the GaN cap layer to form a source region graphical through hole and a drain region graphical through hole; s4: patterning via and drain regions in source regionsDepositing metal in the field patterning through hole to form a source electrode ohmic contact and a drain electrode ohmic contact; s5: n of grid region by Cl-based plasma dry etching process+The GaN cap layer is subjected to self-termination etching to form a grid groove; s6: depositing metal in the gate groove to form a gate, wherein the gate is connected with the n+The GaN cap layers have a spacing therebetween. The preparation method of the invention prepares the graphical ohmic contact structure, and greatly reduces the ohmic contact resistance of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a GaN HEMT device suitable for low-working-voltage and high-efficiency application and a preparation method thereof.
Background
In the 5G low frequency band, Si-based, GaAs-based, and GaN-based technologies are still suitable for PA technology of mobile terminals, but GaN technology has obvious advantages if both large output power density and high power added efficiency are required. In addition, in 5G communication, in order to achieve the goals of faster information transmission rate and lower electromagnetic interference, the operating frequency of the system is preferably selected in the millimeter wave frequency band, based on which Si-based devices have been difficult to meet the requirements, while GaAs-based devices have relatively low power density, so that GaN technology stands out and becomes the dominant force in 5G millimeter wave applications.
When a high-performance millimeter wave power device is prepared, a very important and effective method is to reduce the parasitic resistance of the device. Since the parasitic resistance of the device depends mainly on three aspects: the size, the square resistance and the contact resistance of the device can be optimized from the three aspects. However, since the size of the device depends on the process level of the production line, in the case where the process level reaches the limit, attention may be focused more on the direction of reducing the sheet resistance and the contact resistance of the device.
In general, the sheet resistance of the device depends mainly on the heterojunction material used, and currently well-established and readily available heterojunctions are AlGaN/GaN and InAlN/GaN. But in comparison, the InAlN/GaN heterojunction has stronger polarization intensity, so that low sheet resistance is easier to obtain, and the InAlN/GaN heterojunction is a preferred material for preparing high-efficiency millimeter wave high-power devices. However, it is far from sufficient to actually manufacture a high-performance millimeter wave power device by optimizing a heterojunction material, and in order to finally achieve the goal of reducing the parasitic resistance of the device, the ohmic contact resistance of the device needs to be further reduced to achieve optimization of ohmic contact.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a GaN HEMT device suitable for low-working-voltage and high-efficiency application and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a preparation method of a GaN HEMT device suitable for low-working-voltage and high-efficiency application, which comprises the following steps:
s1: growing a GaN-based heterojunction on a substrate;
s2: growing n on the GaN-based heterojunction+A GaN cap layer;
s3: adopting Cl-based plasma dry etching process to carry out dry etching on the n+Carrying out graphical self-termination etching on the GaN cap layer to form a source region graphical through hole and a drain region graphical through hole;
s4: depositing metal on the source region patterning through hole and the drain region patterning through hole to form a source ohmic contact and a drain ohmic contact;
s5: n for the gate region by dry etching with Cl-based plasma+The GaN cap layer is subjected to self-termination etching to form a grid groove;
s6: depositing metal in the grid groove to form a grid, wherein the grid and the n+The GaN cap layers have a spacing therebetween.
In an embodiment of the present invention, the S1 includes: and sequentially stacking and growing a GaN buffer layer, an AlN insert layer and a barrier layer on the substrate from bottom to top by using MOCVD equipment.
In one embodiment of the present invention, the GaN buffer layer has a thickness of 1 to 3 μm, the AlN insertion layer has a thickness of 1nm to 1.5nm, and the barrier layer is one of AlGaN, InAlN, InAlGaN, ScAlN, or AlN and has a thickness of 3nm to 15 nm.
In one embodiment of the present invention, in the S2, the n+The thickness of the GaN cap layer is 15nm-30nm, and the doping concentration is 5 multiplied by 1018cm-3-1×1020cm-3。
In one embodiment of the present invention, in the S3, the self-stop etching gas is SF6And BCl3Wherein, SF6And BCl3Has a gas flow ratio of 1:3, SF6The gas flow rate of (B) is 5-15sccm, BCl3The flow rate is 15-45 sccm;
the parameters of the etching process are as follows: the power of an electrode on the ICP is 90-110W, the power of an electrode under the ICP is 8-15W, and the pressure is 2-8 mTorr.
In one embodiment of the present invention, in the S3, the size of the via hole is 0.5 × 0.5 μm2。
In an embodiment of the present invention, the S4 includes: patterning via holes in the source region and the drain region using electron beam evaporation equipment, depositing Ti/Al/Ni/Au ohmic stack metal, and then depositing N2And carrying out rapid thermal annealing in the atmosphere to form a source electrode ohmic contact and a drain electrode ohmic contact, wherein the annealing temperature is 850 ℃ and the annealing time is 30 s.
In one embodiment of the present invention, in the S5, the self-stop etching gas is SF6And BCl3Wherein, SF6And BCl3Has a gas flow ratio of 1:3, SF6The gas flow rate of (B) is 5-15sccm, BCl3The flow rate is 15-45 sccm;
the parameters of the etching process are as follows: the power of the ICP upper electrode is 160-240W, the power of the ICP lower electrode is 24-36W, and the pressure is 2-8 mTorr.
The invention also provides a GaN HEMT device suitable for low working voltage and high-efficiency application, which is prepared by the preparation method of any embodiment, and the GaN HEMT device comprises:
a substrate layer, a GaN buffer layer, an AlN insert layer, a barrier layer and n which are sequentially stacked from bottom to top+A GaN cap layer;
a source and a drain arranged in the ohmic region and located at the n+On a GaN cap layer, the source and the drain are respectively connected with the n+The GaN cap layer forms a graphical ohmic contact structure;
a gate electrode disposed on the n+The lower end of the GaN cap layer penetrates through the n+A GaN cap layer connected with the barrier layer and positioned on the n+The gate portion and the n within the GaN cap layer+The GaN cap layers have a spacing therebetween.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention relates to a preparation method of a GaN HEMT device suitable for low working voltage and high efficiency application, which adopts a Cl-based plasma dry etching process to carry out n+And carrying out patterning self-termination etching on the GaN cap layer to prepare a patterned ohmic contact structure, so that the contact area between ohmic contact metal and a semiconductor material is increased. The distance between the source and drain electrodes and the 2DEG is shortened, and the ohmic contact resistance of the device is greatly reduced;
2. the preparation method of the GaN HEMT device suitable for low working voltage and high efficiency application grows highly doped n on the GaN-based heterojunction+GaN cap layer, n+The GaN cap layer and the two-dimensional electron gas (2DEG) channel can participate in the conduction at the same time, so that the total square resistance is effectively reduced, and the performance of the millimeter wave power device is improved;
3. the invention relates to a preparation method of a GaN HEMT device suitable for low working voltage and high efficiency application, which adopts a Cl-based plasma dry etching process to carry out n+The GaN cap layer is subjected to graphical self-termination etching, the etching can be stopped on the surface of the barrier layer spontaneously, and the processing technology is simple and easy to operate.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a GaN HEMT device suitable for low-operating-voltage high-efficiency applications according to an embodiment of the present invention;
fig. 2 a-2 e are schematic diagrams of a process for manufacturing a GaN HEMT device suitable for low-operating-voltage high-efficiency applications according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a GaN HEMT device suitable for low-operating-voltage high-efficiency applications according to an embodiment of the present invention.
Detailed Description
In order to further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, a GaN HEMT device and a method for manufacturing the same according to the present invention will be described in detail below with reference to the accompanying drawings and the following embodiments.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
Example one
Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a GaN HEMT device suitable for low-operating-voltage and high-efficiency applications according to an embodiment of the present invention. As shown in the figure, the method for manufacturing a GaN HEMT device suitable for low-operating-voltage high-efficiency application of the embodiment includes:
s1: growing a GaN-based heterojunction on a substrate;
specifically, the method comprises the following steps: and sequentially stacking and growing a GaN buffer layer, an AlN insert layer and a barrier layer on the substrate from bottom to top by using MOCVD equipment.
Optionally, the GaN buffer layer has a thickness of 1-3 μm, and forms a heterojunction with the barrier layer to generate a two-dimensional electron gas.
Optionally, the barrier layer is one of AlGaN, InAlN, InAlGaN, ScAlN or AlN, and preferably, the barrier layer is InAlN, which forms a lattice-matched InAlN/GaN heterojunction structure with low sheet resistance with the GaN buffer layer.
If the barrier layer is AlN, the AlN insertion layer is not necessary.
Since the thickness of the barrier layer greatly influences the concentration of the two-dimensional electron gas formed by the device, the two-dimensional electron gas density rapidly increases and then saturates with the increase of the thickness of the barrier layer. The large two-dimensional electron gas concentration can effectively reduce parasitic resistance and improve output power, but the thickness of the two-dimensional electron gas concentration cannot be too large, and if the two-dimensional electron gas concentration is too thick, the short channel effect of the device is particularly obvious, so that the frequency characteristic and the pinch-off characteristic of the device are influenced, and the application of the device in a high-frequency scene is influenced. Therefore, both considerations should be taken into account, and the barrier layer should be made as thin as possible at the appropriate required two-dimensional electron concentration. Optionally, the barrier layer has a thickness of 3nm to 15 nm.
The AlN insert layer can improve the effective conduction band offset of the barrier layer and the buffer layer under the action of polarization effect, and the formed deep and narrow quantum well can improve the electronic concentration of a channel; on the other hand, alloy disordered scattering from the potential barrier can be inhibited, and the channel electron mobility is improved. An AlN insertion layer that is too thin, optionally 1nm to 1.5nm thick, may not be as effective and may introduce significant stress into the barrier layer.
S2: growing n on GaN-based heterojunctions+A GaN cap layer;
in the present embodiment, n+The primary function of the GaN cap layer is to make good contact with the ohmic metal to form a low resistance contact and to provide a channel for carrier transport, optionally n+The thickness of the GaN cap layer is 15nm-30 nm.
n+N in GaN cap layer+Doping concentration of GaNIf too low to achieve the goal of making good contact with the ohmic metal and if too high to affect carrier transport, optionally n+N in GaN cap layer+The doping concentration of GaN is 5X 1018cm-3-1×1020cm-3。
S3: adopting Cl-based plasma dry etching process to n+Carrying out graphical self-termination etching on the GaN cap layer to form a source region graphical through hole and a drain region graphical through hole;
specifically, in the present embodiment, the self-stop etching gas is SF6And BCl3Wherein, SF6And BCl3Has a gas flow ratio of 1:3, SF6The gas flow rate of (1) is 5-15sccm, BCl3The flow rate is 15-45 sccm. Etching depth of n+Thickness of the GaN cap layer. The etching equipment adopts ICP etching equipment. The smaller the side length of the patterned via, the smaller the ohmic contact resistance, optionally the via size is 0.5 x 0.5 μm2. The source region patterned through hole and the drain region patterned through hole both comprise a plurality of 0.5 multiplied by 0.5 mu m distributed in an array2Of (3) a through-hole.
Further, the etching process parameters are as follows: the power of an electrode on the ICP is 90-110W, the power of an electrode under the ICP is 8-15W, and the pressure is 2-8 mTorr.
In this embodiment, SF6And BCl3Mixed gas pair n of+The GaN cap layer is subjected to graphical etching at n+After the GaN cap layer is completely etched, when SF is used6Contact reaction with barrier layer containing Al to form AlF3Can block SF6And BCl3The mixed gas is used for further etching the barrier layer, so that the etching barrier rate is extremely low, and the self-termination etching is realized.
It should be noted that, in order to ensure the etching precision of the region, the low-speed etching is adopted, so the power of the upper and lower electrodes of the ICP should be in the low-speed mode.
S4: depositing metal on the source region patterning through hole and the drain region patterning through hole to form a source ohmic contact and a drain ohmic contact;
specifically, the method comprises the following steps: miningPatterning via holes in the source region and the drain region with an electron beam evaporation apparatus, depositing a Ti/Al/Ni/Au ohmic stack metal, followed by N2And carrying out rapid thermal annealing in the atmosphere to form a source electrode ohmic contact and a drain electrode ohmic contact, wherein the annealing temperature is 850 ℃ and the annealing time is 30 s.
In this example, the thickness of the Ti/Al/Ni/Au ohmic stack metal was 22/160/55/45nm, respectively.
S5: n of grid region by Cl-based plasma dry etching process+The GaN cap layer is subjected to self-termination etching to form a grid groove;
specifically, in the present embodiment, the self-stop etching gas is SF6And BCl3Wherein, SF6And BCl3Has a gas flow ratio of 1:3, SF6The gas flow rate of (1) is 5-15sccm, BCl3The flow rate is 15-45 sccm. N of the gate region by self-terminating etch+And removing the GaN cap layer to form a grid groove. The etching equipment adopts ICP etching equipment.
Further, the etching process parameters are as follows: the power of an electrode on the ICP is 160-240W, the etching gas is ensured to form a plasma state, the power of the electrode on the ICP is 24-36W, certain bombardment etching capacity is given to the plasma, and the pressure is 2-8 mTorr. Unlike the self-termination etching in step S3, the requirement for etching accuracy is not so high here, and therefore, the upper and lower electrode powers of the ICP are relatively high.
S6: depositing metal in the gate groove to form a gate, wherein the gate is connected with the n+The GaN cap layers have a spacing therebetween.
In this example, an electron beam evaporation apparatus was used to deposit the Ni/Au gate stack metal, wherein the thickness of the Ni/Au gate stack metal was 45/400nm, respectively.
In the preparation method of the GaN HEMT device suitable for low working voltage and high efficiency application, the Cl-based plasma dry etching process is adopted for n+And carrying out patterning self-termination etching on the GaN cap layer to prepare a patterned ohmic contact structure, so that the contact area between ohmic contact metal and a semiconductor material is increased. WhileAnd the distance between the source and drain electrodes and the 2DEG is shortened, so that the ohmic contact resistance of the device is greatly reduced.
In addition, a highly doped n + GaN cap layer is grown on the GaN-based heterojunction, and the n + GaN cap layer and the two-dimensional electron gas (2DEG) channel can participate in conduction at the same time, so that the total square resistance is effectively reduced, and the performance of the millimeter wave power device is improved.
According to the preparation method of the GaN HEMT device applicable to low working voltage and high efficiency application, the n + GaN cap layer is subjected to graphical self-termination etching by adopting a Cl-based plasma dry etching process, etching can be stopped on the surface of the barrier layer spontaneously, and the preparation method is simple in processing process and easy to operate.
Example two
Taking InAlN/GaN heterojunction as an example, the method for manufacturing the GaN HEMT device suitable for low-operating-voltage and high-efficiency application of this embodiment will be specifically described. Referring to fig. 2 a-2 e, fig. 2 a-2 e are schematic diagrams of a process for fabricating a GaN HEMT device suitable for low-operating-voltage high-efficiency applications according to an embodiment of the present invention.
The preparation method comprises the following specific steps:
the method comprises the following steps: sequentially stacking and growing a GaN layer 202, an AlN layer 203, In on an SiC substrate 201 by using an MOCVD apparatus0.17Al0.83N layers 204 and N+GaN layer 205, as shown in fig. 2 a.
Wherein the GaN layer 202 has a thickness of 2 μm, the AlN layer 203 has a thickness of 1nm, In0.17Al0.83The N layer 204 has a thickness of 8nm, N+The GaN layer 205 had a thickness of 20nm and a doping concentration of 1X 1019cm-3。
Step two: performing dry etching on n by using ICP etching equipment and Cl-based plasma+The GaN layer 205 is subjected to a patterned self-stop etch to form source region patterned vias and drain region patterned vias as shown in fig. 2 b.
Wherein the etching depth is 20nm, and the size of the through hole is 0.5 × 0.5 μm2The self-stop etching gas is SF6/BCl3The flow rate is 10/30sccm, the pressure is 5mTorr, the power of the upper electrode of ICP is 100W, and the power of the lower electrode isAt 10W, a slow rate etch was used to ensure the accuracy of the patterned areas.
Step three: ohmic stack of Ti/Al/Ni/Au metal was deposited using electron beam evaporation equipment followed by deposition on N2A rapid thermal anneal is performed in an ambient to form source ohmic contacts 206 and drain ohmic contacts 207 as shown in figure 2 c.
Wherein the thickness of the ohmic laminated metal of Ti/Al/Ni/Au is 22/160/55/45nm, the annealing temperature is 850 ℃, and the annealing time is 30 s.
Step four: utilizing ICP etching equipment and adopting self-termination etching method to etch n of grid region+The GaN layer 205 is removed to form a gate recess 208 as shown in fig. 2 d.
Wherein the self-stop etching gas is SF6/BCl3The flow rate was 10/30sccm, the pressure was 5mTorr, the top electrode power for ICP was 200W, and the bottom electrode power was 30W, respectively.
Step five: a Ni/Au gate stack metal is deposited in the gate recess 208 using an electron beam evaporation device to form a gate 209, as shown in figure 2 e.
Wherein the thickness of the Ni/Au gate stack metal is 45/400nm, and the gate 209 and n are respectively+There is a spacing between the GaN layers 205.
EXAMPLE III
The embodiment provides a GaN HEMT device suitable for low-working-voltage and high-efficiency application, and the GaN HEMT device is prepared by adopting the method of any embodiment. Referring to fig. 3, fig. 3 is a schematic structural diagram of a GaN HEMT device suitable for low-operating-voltage high-efficiency applications according to an embodiment of the present invention. As shown in the drawing, the GaN HEMT device of the present embodiment includes: substrate layer 301, GaN buffer layer 302, AlN insert layer 303, barrier layer 304, n+A GaN cap layer 305, a source 306, a drain 307, and a gate 308. Among them, a substrate layer 301, a GaN buffer layer 302, an AlN insert layer 303, a barrier layer 304 and n+The GaN cap layers 305 are stacked in this order from bottom to top. The source electrode 306 and the drain electrode 307 are arranged in the ohmic region and are positioned at n+On the GaN cap layer 305, and the source 306 and the drain 307 are respectively connected with n+The GaN cap layer 305 forms a patterned ohmic contact structure. The gate 308 is set at n+Above the GaN cap layer 305, the lower end thereof passes through n+The GaN cap layer 305 is connected to the barrier layer 304 at n+Portion of gate 308 and n within GaN cap layer 305+There is a spacing between the GaN cap layers 305.
Optionally, the barrier layer 304 is one of AlGaN, InAlN, InAlGaN, ScAlN or AlN, preferably, the barrier layer 304 is InAlN, which forms a lattice-matched InAlN/GaN heterojunction structure with a GaN buffer layer having a low sheet resistance.
Note that if the barrier layer 304 is AlN, the AlN insertion layer 303 is not necessary.
The GaN HEMT device suitable for low working voltage and high efficiency application adopts a lattice matching InAlN/GaN heterojunction structure with low sheet resistance, and a highly doped n + GaN cap layer is added on the lattice matching InAlN/GaN heterojunction structure, so that the GaN HEMT device can form good contact with ohmic metal. In addition, the ohmic contact adopts a graphical ohmic contact structure, so that the contact area of ohmic metal and a semiconductor material is increased, and the distance between the ohmic metal and the semiconductor material and the 2DEG is increased, the ohmic contact resistance is greatly reduced, and the low-resistance ohmic contact is realized.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The directional or positional relationships indicated by "upper", "lower", "left", "right", etc., are based on the directional or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A preparation method of a GaN HEMT device suitable for low working voltage and high efficiency application is characterized by comprising the following steps:
s1: growing a GaN-based heterojunction on a substrate;
s2: growing n on the GaN-based heterojunction+A GaN cap layer;
s3: adopting Cl-based plasma dry etching process to carry out dry etching on the n+Carrying out graphical self-termination etching on the GaN cap layer to form a source region graphical through hole and a drain region graphical through hole;
s4: depositing metal on the source region patterning through hole and the drain region patterning through hole to form a source ohmic contact and a drain ohmic contact;
s5: n for the gate region by dry etching with Cl-based plasma+The GaN cap layer is subjected to self-termination etching to form a grid groove;
s6: depositing metal in the grid groove to form a grid, wherein the grid and the n+The GaN cap layers have a spacing therebetween.
2. The method according to claim 1, wherein the S1 includes: and sequentially stacking and growing a GaN buffer layer, an AlN insert layer and a barrier layer on the substrate from bottom to top by using MOCVD equipment.
3. The method of claim 2, wherein the GaN buffer layer has a thickness of 1-3 μm, the AlN insertion layer has a thickness of 1nm-1.5nm, and the barrier layer is one of AlGaN, InAlN, InAlGaN, ScAlN or AlN having a thickness of 3nm-15 nm.
4. The method according to claim 1, wherein in the S2, the n is+The thickness of the GaN cap layer is 15nm-30nm, and the doping concentration is 5 multiplied by 1018cm-3-1×1020cm-3。
5. The method of claim 1, wherein in the step S3, the self-stop etching gas is SF6And BCl3Wherein, SF6And BCl3Has a gas flow ratio of 1:3, SF6The gas flow rate of (1) is 5-15sccm, BCl3The flow rate is 15-45 sccm;
the parameters of the etching process are as follows: the power of an electrode on the ICP is 90-110W, the power of an electrode under the ICP is 8-15W, and the pressure is 2-8 mTorr.
6. The method of claim 1, wherein in the S3, the size of the via hole is 0.5 x 0.5 μm2。
7. The method according to claim 1, wherein the S4 includes: patterning via holes in the source region and the drain region using electron beam evaporation equipment, depositing Ti/Al/Ni/Au ohmic stack metal, and then depositing N2And carrying out rapid thermal annealing in the atmosphere to form a source electrode ohmic contact and a drain electrode ohmic contact, wherein the annealing temperature is 850 ℃ and the annealing time is 30 s.
8. The method of claim 1, wherein in the step S5, the self-stop etching gas is SF6And BCl3Wherein, SF6And BCl3Has a gas flow ratio of 1:3, SF6The gas flow rate of (1) is 5-15sccm, BCl3The flow rate is 15-45 sccm;
the parameters of the etching process are as follows: the power of the ICP upper electrode is 160-240W, the power of the ICP lower electrode is 24-36W, and the pressure is 2-8 mTorr.
9. A GaN HEMT device suitable for low operating voltage high efficiency applications, prepared by the method of any one of claims 1-8, comprising:
a substrate layer, a GaN buffer layer, an AlN insert layer, a barrier layer and n which are sequentially stacked from bottom to top+A GaN cap layer;
a source and a drain arranged in the ohmic region and located at the n+On a GaN cap layer, the source and the drain are respectively connected with the n+The GaN cap layer forms a graphical ohmic contact structure;
a gate electrode disposed on the n+On the GaN cap layer, and the lower end of the GaN cap layer passes through the n+A GaN cap layer connected with the barrier layer and positioned on the n+The gate portion and the n within the GaN cap layer+The GaN cap layers have a spacing therebetween.
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