CN108010844B - HEMT device and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000000903 blocking effect Effects 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 16
- 229910017115 AlSb Inorganic materials 0.000 claims description 31
- 238000002161 passivation Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 27
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 5
- 229910000673 Indium arsenide Inorganic materials 0.000 description 22
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 22
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
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- 229910002059 quaternary alloy Inorganic materials 0.000 description 1
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- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention relates to a HEMT device and a preparation method thereof, wherein the preparation method comprises the following steps: s101, selecting a substrate material; s102, sequentially growing a first buffer layer and a second buffer layer on the surface of the substrate material; s103, preparing a groove area on the surface of the second buffer layer; s104, sequentially growing a lower barrier layer, a channel layer, an isolation layer, a doping layer, an upper barrier layer, a hole blocking layer and a cap layer in the groove region; and S105, preparing a grid electrode, a source electrode and a drain electrode to complete preparation of the HEMT device. The HEMT device and the preparation method thereof solve the problem that the performance of the device is reduced due to the fact that the material of the buffer layer is easy to oxidize; the second buffer layer can be used as a mesa etching stop layer, the leakage of gate current is not increased while the isolation effect of the device is ensured, and the working performance of the HEMT device is further improved.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to an HEMT device and a preparation method thereof.
Background
The first generation of High Electron Mobility Transistor (HEMT) has a GaAs/AlGaAs heterojunction as a core structure, grown on a GaAs substrate. In order to enhance the electron mobility and the electron-confining ability of the quantum well, In element is added to the channel to form an AlGaAs/InGaAs heterojunction, which is also called phemt (pseudomorphic hemt). In order to meet the application of higher frequency, the In composition In the channel is increased to more than 50%. Accordingly, to maintain lattice matching, the barrier layer becomes InAlAs, and an InP substrate is employed. Such a transistor based on the InAlAs/InGaAs/InP structure is also called an InP HEMT, and becomes a second-generation HEMT. Because the reliability of the InP substrate is poor, the device is expected to grow on the GaAs substrate with better reliability, but the lattice mismatch between the GaAs substrate and the channel with high In composition is large, and the interface roughness and a large number of defects caused by the GaAs substrate can reduce the electron mobility of the channel. Thus, a growth technique called metamorphic has been developed. This technique grows a channel of high In composition on a GaAs substrate through a metamorphic buffer layer, and its performance is not much degraded compared to an InP HEMT. The HEMT prepared in this way is also called a HEMT (metameric HEMT). As the requirements of people on the performance of devices are continuously improved, the In component of the channel is continuously increased, a third-generation compound HEMT based on a pure InAs channel is developed, and the corresponding barrier layer is also changed into AlSb which is In lattice match with the barrier layer, namely the InAs/AlSb HEMT. The electron mobility and saturation drift velocity of InAs are greatly improved compared with InGaAs. On the other hand, InAs/AlSb has a larger conduction band offset and produces a higher concentration of two-dimensional electron gas (2DEG) than previous material systems. Therefore, the InAs/AlSb HEMT theoretically has lower power consumption, better RF and noise characteristics and is particularly suitable for low-power consumption and low-noise microwave-millimeter wave application.
Mesa isolation is the first key process for the fabrication of InAs/AlSb HEMTs devices, which can form effective electrical isolation of devices on the same wafer. Common mesa isolation methods are classified into wet etching and dry etching. Dry etching is etching by Inductively Coupled Plasma (ICP), and wet etching is etching and dissolving a material of a region to be isolated by using a chemical etchant to achieve an isolation effect of different regions. When an InAs/AlSbHEMT device is manufactured, whether wet etching or dry etching is adopted for mesa isolation, the buffer layer material can be always exposed in the air in the subsequent process, the buffer layer material of the InAs/AlSb HEMT device is generally easier to oxidize, the AlGaSb material is commonly used for replacing AlSb as a mesa etching stop layer to reduce mesa oxidation at present, but compared with the AlSb material, the AlGaSb material introduces lower resistance, the leakage of gate current can be increased, the device isolation effect can be reduced, and the performance of the HEMT device is greatly influenced.
Therefore, it is becoming more and more important what kind of material and process is used to improve the working performance of the InAs/AlSb HEMT device.
Disclosure of Invention
In order to improve the working performance of the HEMT device, the invention provides the HEMT device and a preparation method thereof; the technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of an HEMT device, which comprises the following steps:
s101, selecting a substrate material;
s102, sequentially growing a first buffer layer and a second buffer layer on the surface of the substrate material;
s103, preparing a groove area on the surface of the second buffer layer;
s104, sequentially growing a lower barrier layer, a channel layer, an isolation layer, a doping layer, an upper barrier layer, a hole blocking layer and a cap layer in the groove region;
and S105, preparing a grid electrode, a source electrode and a drain electrode to complete preparation of the HEMT device.
In one embodiment of the present invention, S103 includes:
s1031, growing a first passivation layer on the surface of the second buffer layer by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) process;
s1032, etching the first passivation layer until the second buffer layer is exposed by utilizing an ICP etching technology to form the groove region.
In an embodiment of the present invention, the substrate material is GaAs, the first buffer layer material is GaAs, and the second buffer layer material is AlSb.
In one embodiment of the present invention, a sum of thicknesses of the lower barrier layer, the channel layer, the isolation layer, the doping layer, the upper barrier layer, the hole blocking layer, and the cap layer is equal to a depth of the trench region.
In an embodiment of the invention, the depth of the trench region is 80-100 nm.
Another embodiment of the present invention provides a HEMT device, including: the device comprises a substrate, a first buffer layer, a second buffer layer, a first passivation layer, a lower barrier layer, a channel layer, an isolation layer, a doping layer, an upper barrier layer, a hole blocking layer and a cap layer; a gate electrode, a source electrode, a drain electrode and a second passivation layer; wherein the content of the first and second substances,
the first buffer layer, the second buffer layer, the lower barrier layer, the channel layer, the isolation layer, the doping layer, the upper barrier layer, the hole blocking layer and the cap layer are sequentially arranged on the substrate;
the first passivation layer is arranged on the second buffer layer, and the first passivation layer and the second buffer layer form a groove region; the lower barrier layer, the channel layer, the isolation layer, the doping layer, the upper barrier layer, the hole blocking layer and the cap layer are all arranged in the groove region;
the grid electrode is arranged on the hole blocking layer, and the source electrode and the drain electrode are both arranged on the cap layer;
the second passivation layer is arranged on the surface of the device.
In one embodiment of the invention, the material of the first buffer layer is GaAs, and the thickness is 200 nm; the second buffer layer is made of AlSb and is 1500nm thick.
In one embodiment of the present invention, the first passivation layer has a thickness equal to a sum of thicknesses of the lower barrier layer, the channel layer, the isolation layer, the doping layer, the upper barrier layer, the hole blocking layer, and the cap layer.
In one embodiment of the invention, the thickness of the first passivation layer is 88.2 nm.
In one embodiment of the invention, the material of the lower barrier layer is AlSb, and the thickness is 50 nm; the channel layer is made of InAs and has the thickness of 15 nm; the isolating layer is made of AlSb and is 5nm thick; the material of the doped layer is InAs, and the thickness is 1.2 nm; the upper barrier layer is made of AlSb and is 8nm thick; the hole blocking layer is made of InAlAs and is 4nm thick; the cap layer is made of InAs and is 5nm thick.
Compared with the prior art, the invention has the following beneficial effects:
1. the HEMT device and the preparation method thereof provided by the invention solve the problem that the performance of the device is reduced due to the fact that the material of the buffer layer is easy to oxidize.
2. According to the HEMT device and the preparation method thereof, the second buffer layer can be used as the mesa etching stop layer, the isolation effect of the device is ensured, meanwhile, the leakage of gate current is not increased, and the working performance of the HEMT device is further improved.
3. The HEMT device and the preparation method thereof can ensure that the subsequent process is carried out on a plane, and the HEMT device without grid control caused by grid metal fracture can not occur; at the same time, the gate metal is also prevented from shorting to the channel.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Fig. 1 is a schematic flow chart of a method for manufacturing a HEMT device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an HEMT device according to an embodiment of the present invention;
fig. 3a to fig. 3f are schematic diagrams illustrating a method for manufacturing another HEMT device according to an embodiment of the present invention;
fig. 4 is a real graph of a gate metal fracture of an InAs/AlSb HEMT device prepared by a conventional process according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing an HEMT device according to an embodiment of the present invention, including:
s101, selecting a substrate material;
s102, sequentially growing a first buffer layer and a second buffer layer on the surface of the substrate material;
s103, preparing at least one groove area on the surface of the second buffer layer;
s104, sequentially growing a lower barrier layer, a channel layer, an isolation layer, a doping layer, an upper barrier layer, a hole blocking layer and a cap layer in the groove region;
and S105, preparing a grid electrode, a source electrode and a drain electrode to complete preparation of the HEMT device.
Preferably, S103 may include:
s1031, growing a first passivation layer on the surface of the second buffer layer by utilizing a PECVD process;
s1032, etching the first passivation layer until the second buffer layer is exposed by utilizing an ICP etching technology to form the groove region.
Preferably, S105 may include:
s1051, respectively preparing a grid electrode on the surface of the hole blocking layer and preparing a source electrode and a drain electrode on the surface of the cap layer
And S1052, generating a second passivation layer on the surface of the device by utilizing a PECVD process.
Specifically, the sum of the thicknesses of the lower barrier layer, the channel layer, the isolation layer, the doping layer, the upper barrier layer, the hole blocking layer, and the cap layer is equal to the depth of the trench region.
Preferably, the depth of the groove region is 80-100 nm, and the width of the groove region is 10-150 nm.
Preferably, the substrate material is GaAs, the first buffer layer material is GaAs, and the second buffer layer material is AlSb.
Preferably, the doped layer has a doped Si concentration of 4 × 1019cm-3。
Preferably, the material of the first passivation layer and the second passivation layer is SiO2Or SiNx。
The HEMT preparation method provided by the embodiment solves the problem that the performance of the device is reduced due to the fact that the material of the second buffer layer is easy to oxidize; meanwhile, the groove region is prepared on the surface of the second buffer layer, so that the follow-up process can be carried out on a plane, and a grid-control-free HEMT device caused by grid metal fracture can not be formed.
Example two
Referring to fig. 2 and fig. 2 are schematic structural diagrams of a HEMT device according to an embodiment of the present invention, which is described in detail below on the basis of the above embodiments.
Specifically, the method comprises the following steps: a substrate 201, a first buffer layer 202, a second buffer layer 203, a first passivation layer 204, a lower barrier layer 205, a channel layer 206, an isolation layer 207, a doping layer 208, an upper barrier layer 209, a hole blocking layer 210, a cap layer 211; a gate 212, a source 213, and a drain 214; wherein the content of the first and second substances,
the first buffer layer 202, the second buffer layer 203, the lower barrier layer 205, the channel layer 206, the isolation layer 207, the doping layer 208, the upper barrier layer 209, the hole blocking layer 210, and the cap layer 211 are sequentially disposed on the substrate 201;
the first passivation layer 204 is disposed on the second buffer layer 203, and the first passivation layer 204 and the second buffer layer 203 form a trench region; the lower barrier layer 205, the channel layer 206, the isolation layer 207, the doping layer 208, the upper barrier layer 209, the hole blocking layer 210, and the cap layer 211 are all disposed within the trench region;
the gate electrode 212 is disposed on the hole blocking layer 210, and the source electrode 213 and the drain electrode 214 are both disposed on the cap layer 211;
the HEMT device further comprises a second passivation layer, wherein the second passivation layer is arranged on the surface of the device.
Preferably, the material of the substrate 201 is a GaAs or InP substrate.
Specifically, the material of the first buffer layer 202 may be a binary, ternary, or quaternary alloy compound of In, Al, Ga, As, and Sb; the second buffer layer 203 is made of AlSb.
Preferably, the material of the first buffer layer 202 may be GaAs, with a thickness of 200 nm; the second buffer layer 203 is made of AlSb and has a thickness of 1500 nm.
The lower barrier layer 205 is made of AlSb; the material of the channel layer 206 is InAs; the isolating layer 207 is made of AlSb; the upper barrier layer 209 is made of AlSb; the material of the hole blocking layer 210 is InAlAs.
Preferably, the doped layer 208 is Si-doped InAs or Te-doped AlSb.
Preferably, the material of the cap layer 211 is InAs heavily doped with Si.
Preferably, the material of the first passivation layer and the second passivation layer is SiO2Or SiNx。
Preferably, the thickness of the first passivation layer 204 is equal to the sum of the thicknesses of the lower barrier layer 205, the channel layer 206, the isolation layer 207, the doping layer 208, the upper barrier layer 209, the hole blocking layer 210, and the cap layer 211.
Preferably, the thickness of the first passivation layer 204 is 88.2 nm.
Preferably, the thickness of the lower barrier layer 205 is 50nm, the thickness of the channel layer 206 is 15nm, the thickness of the isolation layer 207 is 5nm, the thickness of the doping layer 208 is 1.2nm, the thickness of the upper barrier layer 209 is 8nm, the thickness of the hole blocking layer 210 is 4nm, and the thickness of the cap layer 211 is 5 nm.
The HEMT device provided by the embodiment solves the problems that the metal of the metal gate of the existing HEMT device is easy to break and the channel and the gate are short-circuited; meanwhile, the second buffer layer AlSb is used as a mesa etching stop layer, and the lower barrier layer AlSb has no lattice mismatch; the work performance and stability of the HEMT device are improved.
EXAMPLE III
Further, referring to fig. 3a to fig. 3f, fig. 3a to fig. 3f are schematic diagrams of another method for manufacturing an HEMT device according to an embodiment of the present invention, the method includes the following steps:
s301, as shown in FIG. 3a, selecting a GaAs substrate 001;
s302, as shown in fig. 3b, sequentially growing a first buffer layer 002 and a second buffer layer 003 on the substrate by using a Molecular Beam Epitaxy (MBE) process; wherein the first buffer layer 002 is made of GaAs; the second buffer layer 003 is made of AlSb;
s303, as shown in FIG. 3c, SiO with a thickness of 88.2nm is deposited by PECVD process2 A passivation layer 004;
s304, etching the SiO by using an ICP etching method as shown in figure 3d2The passivation layer 004 to the second buffer layer 003 form a trench region;
s305, as shown in the figure 3e, utilizing an MBE process to sequentially grow an AlSb lower barrier layer 005 with the thickness of 50nm, an InAs channel layer 006 with the thickness of 15nm, an AlSb isolating layer 007 with the thickness of 5nm, an InAs doping layer 008 with the thickness of 1.2nm, an AlSb upper barrier layer 009 with the thickness of 8nm, an InAlAs hole blocking layer 010 with the thickness of 4nm and an InAs cap layer 011 with the thickness of 5nm in a groove region;
s306, as shown in fig. 3f, forming a gate 012, a source 013, and a drain 014 by photolithography, etching, and electron beam evaporation;
s307, depositing a SiN passivation layer by using a PECVD (plasma enhanced chemical vapor deposition) process to finish the preparation of the HEMT device.
According to the preparation method of the HEMT device provided by the embodiment, the first passivation layer is arranged on the second buffer layer, so that the problem that the performance of the device is degraded because the buffer layer material is always exposed in the air and is easily oxidized in the subsequent process regardless of wet etching or dry etching in the conventional mesa isolation is solved, and the working performance of the InAs/AlSb HEMT device is improved; meanwhile, the second buffer layer is used as a mesa etching stop layer, the leakage of gate current is not increased while the isolation effect of the device is ensured, and the working performance of the HEMT device is further improved.
Further, referring to fig. 4, fig. 4 is a gate metal fracture real object diagram of an InAs/AlSbHEMT device prepared by the prior art provided by the embodiment of the present invention, the prepared gate is a key process for preparing an InAs/AlSb HEMTs device, the minimum gate length prepared at present can reach dozens of nanometers, after the mesa is etched, the metal on the side wall of the mesa fractures after the metal gate is evaporated by using an electronic book, and the metal on the side wall of the mesa is connected with the metal gate, which can cause the short circuit of the channel and the gate; the preparation method of the HEMT device provided by the embodiment can ensure that the subsequent process is carried out on a plane, and the prepared HEMT device does not have the phenomenon of grid metal fracture.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (4)
1. A preparation method of an HEMT device is characterized by comprising the following steps:
s101, selecting a substrate material;
s102, sequentially growing a first buffer layer and a second buffer layer on the surface of the substrate material;
s103, preparing a groove area on the surface of the second buffer layer;
s104, sequentially growing a lower barrier layer, a channel layer, an isolation layer, a doping layer, an upper barrier layer, a hole blocking layer and a cap layer in the groove region;
s105, preparing a grid electrode, a source electrode and a drain electrode to complete the preparation of the HEMT device,
wherein the S103 comprises:
s1031, growing a first passivation layer on the surface of the second buffer layer by utilizing a PECVD process;
s1032, etching the first passivation layer until the second buffer layer is exposed by utilizing an ICP etching technology to form the groove region.
2. The production method according to claim 1, wherein the substrate material is GaAs, the first buffer layer is GaAs, and the second buffer layer is AlSb.
3. The method of manufacturing according to claim 1, wherein a sum of thicknesses of the lower barrier layer, the channel layer, the isolation layer, the doping layer, the upper barrier layer, the hole blocking layer, and the cap layer is equal to a depth of the trench region.
4. The method according to claim 3, wherein the trench region has a depth of 80 to 100 nm.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762146A (en) * | 2009-12-23 | 2016-07-13 | 英特尔公司 | Techniques for forming contacts to quantum well transistors |
| CN106972056A (en) * | 2017-04-20 | 2017-07-21 | 郑州大学 | The anti-proton irradiation InP-base HEMT device and its processing method being passivated based on BCB |
| CN107123668A (en) * | 2017-04-12 | 2017-09-01 | 西安电子科技大学 | A kind of InAs/AlSb HEMT epitaxial structures and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762146A (en) * | 2009-12-23 | 2016-07-13 | 英特尔公司 | Techniques for forming contacts to quantum well transistors |
| CN107123668A (en) * | 2017-04-12 | 2017-09-01 | 西安电子科技大学 | A kind of InAs/AlSb HEMT epitaxial structures and preparation method thereof |
| CN106972056A (en) * | 2017-04-20 | 2017-07-21 | 郑州大学 | The anti-proton irradiation InP-base HEMT device and its processing method being passivated based on BCB |
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