CN108010844A - HEMT device and preparation method thereof - Google Patents
HEMT device and preparation method thereof Download PDFInfo
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- CN108010844A CN108010844A CN201711138236.1A CN201711138236A CN108010844A CN 108010844 A CN108010844 A CN 108010844A CN 201711138236 A CN201711138236 A CN 201711138236A CN 108010844 A CN108010844 A CN 108010844A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 62
- 230000004888 barrier function Effects 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000926 separation method Methods 0.000 claims abstract description 22
- 230000000903 blocking effect Effects 0.000 claims abstract description 20
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 7
- 229910017115 AlSb Inorganic materials 0.000 claims description 37
- 238000002161 passivation Methods 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 26
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 25
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical group [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 25
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 9
- 230000026267 regulation of growth Effects 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 claims description 2
- 230000007423 decrease Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The present invention relates to a kind of HEMT device and preparation method thereof, including：S101, choose substrate material；S102, in the substrate material surface grow first buffer layer and second buffer layer successively；S103, the second buffer layer surface prepare trench area；S104, grow successively in the trench area lower barrierlayer, channel layer, separation layer, doped layer, on barrier layer, hole blocking layer and cap layers；S105, prepare grid, source electrode and drain electrode to complete the preparation of HEMT device.HEMT device provided by the invention and preparation method thereof solves the problems, such as that cushioning layer material is oxidizable and causes device performance to decline；It using second buffer layer as mesa etch stop layer, can will not increase the leakage of gate current while the effect of device isolation is ensured, further increase the working performance of HEMT device.
Description
Technical field
The invention belongs to microelectronics technology, more particularly to a kind of HEMT device and preparation method thereof.
Background technology
First generation high electron mobility transistor (High Electron Mobility Transistor, HEMT) with
GaAs/AlGaAs hetero-junctions is as nuclear structure, and growth is on gaas substrates.In order to lift the electricity of electron mobility and Quantum Well
Beamlet ties up ability, and In elements are added into raceway groove, forms AlGaAs/InGaAs hetero-junctions, and this device is also referred to as
pHEMT(pseudomorphic HEMT).In order to meet the application of higher frequency, in raceway groove the component lifting of In to 50% with
On.Correspondingly, in order to keep Lattice Matching, barrier layer is changed into InAlAs, and employs InP substrate.It is this to be based on InAlAs/
The transistor of InGaAs/InP structures is also referred to as InP HEMT, becomes second generation HEMT.Due to InP substrate Reliability comparotive
Difference, we, which are more desirable to device, can be grown on the GaAs substrates of better reliability, but the raceway groove of GaAs substrates and high In components
Lattice mismatch is larger, the interface roughness caused by it with it is a large amount of the defects of can decline channel electron mobility.Then, it is a kind of
The growing technology for being referred to as metamorphic is developed.This technology is by metamorphic cushions by high In components
Raceway groove be grown on GaAs substrates, and its performance compared with InP HEMT without too big decline.In this way
The HEMT prepared is also referred to as mHEMT (metamorphic HEMT).Since requirement of the people for device performance constantly carries
Height, raceway groove In components continue to increase, and have developed the third generation compound HEMT based on pure InAs raceway grooves, corresponding barrier layer
It is changed into the AlSb of Lattice Matching therewith, here it is InAs/AlSb HEMT.The electron mobility of InAs is with satisfying compared with InGaAs
There is very big raising with drift velocity.On the other hand, there is bigger compared to material system before, InAs/AlSb
Conduction band offset amount, produces two-dimensional electron gas (2DEG) concentration of higher.Therefore, in theory InAs/AlSb HEMT have it is lower
Power consumption, more preferable RF and noise characteristic, particularly suitable and low-power consumption, low noise microwave-Millimeter Wave Applications.
Mesa-isolated is first critical process prepared by InAs/AlSb HEMTs devices, it can be in same wafer
Each device form effective electric isolation.Common mesa-isolated method is divided into two kinds of wet etching and dry etching.Dry method
Etching is etched using inductively coupled plasma (Inductively Coupled Plasma, abbreviation ICP), and wet etching is
The material corrosion in region to be isolated is dissolved with chemical corrosion liquid, to reach the buffer action of different zones.In InAs/AlSb
When HEMT device makes, mesa-isolated can all make cushioning layer material follow-up no matter using wet etching or dry etching
It is constantly exposed in technique in air, and the cushioning layer material of InAs/AlSb HEMT devices is generally easier to aoxidize, at present
Commonly use AlGaSb materials reduces table top oxidation instead of AlSb as mesa etch cutoff layer, but compares AlSb materials,
AlGaSb materials introduce relatively low resistance, it will increase the leakage of gate current, and can reduce the effect of device isolation, pole
The big performance that have impact on HEMT device.
Therefore, which kind of material and technique are used to improve the increasingly heavier of the working performance of InAs/AlSb HEMT devices change
Will.
The content of the invention
In order to improve the working performance of HEMT device, the present invention provides a kind of HEMT device and preparation method thereof；This hair
Bright technical problems to be solved are achieved through the following technical solutions：
The embodiment provides a kind of preparation method of HEMT device, including：
S101, choose substrate material；
S102, in the substrate material surface grow first buffer layer and second buffer layer successively；
S103, the second buffer layer surface prepare trench area；
S104, grow successively in the trench area lower barrierlayer, channel layer, separation layer, doped layer, on barrier layer, sky
Cave barrier layer and cap layers；
S105, prepare grid, source electrode and drain electrode to complete the preparation of HEMT device.
In one embodiment of the invention, S103 includes：
S1031, utilize plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor
Deposition, abbreviation PECVD) technique, one passivation layer of growth regulation on the second buffer layer surface；
S1032, using ICP lithographic techniques, etch first passivation layer until exposing the second buffer layer to be formed
The trench area.
In one embodiment of the invention, the substrate material is GaAs, and the material of the first buffer layer is GaAs,
The material of the second buffer layer is AlSb.
In one embodiment of the invention, the lower barrierlayer, the channel layer, the separation layer, the doped layer,
The thickness summation of the upper barrier layer, the hole blocking layer and the cap layers is equal to the depth of the trench area.
In one embodiment of the invention, the depth of the trench area is 80~100nm.
An alternative embodiment of the invention provides a kind of HEMT device, including：Substrate, first buffer layer, the second buffering
Layer, the first passivation layer, lower barrierlayer, channel layer, separation layer, doped layer, upper barrier layer, hole blocking layer, cap layers；Grid, source
Pole, drain electrode and the second passivation layer；Wherein,
It is the first buffer layer, the second buffer layer, the lower barrierlayer, the channel layer, the separation layer, described
Doped layer, the upper barrier layer, the hole blocking layer and the cap layers are set in turn on the substrate；
First passivation layer is arranged in the second buffer layer, and first passivation layer and the second buffer layer
Form trench area；The lower barrierlayer, the channel layer, the separation layer, the doped layer, the upper barrier layer, the sky
Cave barrier layer and the cap layers are respectively provided with the trench area；
The grid is arranged on the hole blocking layer, and the source electrode and the drain electrode may be contained within the cap layers；
Second passivation layer is arranged at device surface.
In one embodiment of the invention, the material of the first buffer layer is GaAs, thickness 200nm；Described
The material of two cushions is AlSb, thickness 1500nm.
In one embodiment of the invention, the thickness of first passivation layer is equal to the lower barrierlayer, the raceway groove
Layer, the separation layer, the doped layer, the upper barrier layer, the thickness summation of the hole blocking layer and the cap layers.
In one embodiment of the invention, the thickness of first passivation layer is 88.2nm.
In one embodiment of the invention, the lower barrierlayer material is AlSb, thickness 50nm；The channel layer
Material is InAs, thickness 15nm；The material of the separation layer is AlSb, thickness 5nm；The material of the doped layer is
InAs, thickness 1.2nm；The material of the upper barrier layer is AlSb, thickness 8nm；The material of the hole blocking layer is
InAlAs, thickness 4nm；The material of the cap layers is InAs, thickness 5nm.
Compared with prior art, the invention has the advantages that：
1st, HEMT device provided by the invention and preparation method thereof, solves that cushioning layer material is oxidizable to cause device performance
The problem of decline.
2nd, HEMT device provided by the invention and preparation method thereof, can terminate second buffer layer as mesa etch
Layer, will not increase the leakage of gate current while the effect of device isolation is ensured, further increase the work of HEMT device
Make performance.
3rd, HEMT device provided by the invention and preparation method thereof can ensure that subsequent technique carries out in the plane, will not go out
Existing grid metal is broken and causes the HEMT device of no grid-control；Meanwhile it also prevent grid metal and raceway groove short circuit.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
By the detailed description below with reference to attached drawing, other side of the invention and feature become obvious.But it should know
Road, which is only the purpose design explained, not as the restriction of the scope of the present invention, this is because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale attached drawing, they only try hard to concept
Ground illustrates structure and flow described herein.
Fig. 1 is a kind of preparation method flow diagram of HEMT device provided in an embodiment of the present invention；
Fig. 2 is a kind of HEMT device structure diagram provided in an embodiment of the present invention；
Fig. 3 a- Fig. 3 f are the preparation method schematic diagram of another HEMT device provided in an embodiment of the present invention；
Fig. 4 is InAs/AlSb HEMT devices grid metal fracture prepared by a kind of existing process provided in an embodiment of the present invention
Pictorial diagram.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of preparation method flow diagram of HEMT device provided in an embodiment of the present invention, is wrapped
Include：
S101, choose substrate material；
S102, in the substrate material surface grow first buffer layer and second buffer layer successively；
S103, on the second buffer layer surface prepare at least one trench area；
S104, grow successively in the trench area lower barrierlayer, channel layer, separation layer, doped layer, on barrier layer, sky
Cave barrier layer and cap layers；
S105, prepare grid, source electrode and drain electrode to complete the preparation of HEMT device.
Preferably, S103 can include：
S1031, using pecvd process, one passivation layer of growth regulation on the second buffer layer surface；
S1032, using ICP lithographic techniques, etch first passivation layer until exposing the second buffer layer to be formed
The trench area.
Preferably, S105 can include：
S1051, prepare grid in the hole barrier layer surface respectively and prepare source electrode and drain electrode on the cap layers surface
S1052, using pecvd process, generate the second passivation layer in device surface.
Specifically, the lower barrierlayer, the channel layer, the separation layer, the doped layer, the upper barrier layer, institute
The thickness summation for stating hole blocking layer and the cap layers is equal to the depth of the trench area.
Preferably, the depth of the trench area is 80~100nm, and the width of the trench area is 10~150nm.
Preferably, the substrate material is GaAs, and the material of the first buffer layer is GaAs, the second buffer layer
Material is AlSb.
Preferably, the doping Si concentration of the doped layer is 4 × 1019cm-3。
Preferably, the material of first passivation layer and the second passivation layer is SiO2Or SiNx。
HEMT preparation methods provided in this embodiment, solve that second buffer layer material is oxidizable to cause device performance to decline
The problem of；Meanwhile by preparing trench area on second buffer layer surface, it is ensured that subsequent technique carries out in the plane, will not
Form HEMT device that is that grid metal is broken and causing no grid-control.
Embodiment two
Fig. 2 is refer to, Fig. 2 is a kind of HEMT device structure diagram provided in an embodiment of the present invention, and the present embodiment is upper
On the basis of stating embodiment, HEMT device of the invention is described in detail as follows.
Specifically, including：Substrate 201, first buffer layer 202, second buffer layer 203, the first passivation layer 204, lower potential barrier
Layer 205, channel layer 206, separation layer 207, doped layer 208, upper barrier layer 209, hole blocking layer 210, cap layers 211；Grid
212nd, source electrode 213 and drain electrode 214；Wherein,
The first buffer layer 202, the second buffer layer 203, the lower barrierlayer 205, the channel layer 206, institute
State separation layer 207, the doped layer 208, upper barrier layer 209, the hole blocking layer 210 and the cap layers 211 according to
It is secondary to be arranged on the substrate 201；
First passivation layer 204 is arranged in the second buffer layer 203, and first passivation layer 204 with it is described
Second buffer layer 203 forms trench area；The lower barrierlayer 205, the channel layer 206, the separation layer 207, the doping
Layer 208, upper barrier layer 209, the hole blocking layer 210 and the cap layers 211 may be contained within the trench area；
The grid 212 is arranged on the hole blocking layer 210, and the source electrode 213 and the drain electrode 214 may be contained within
In the cap layers 211；
The HEMT device further includes the second passivation layer, and second passivation layer is arranged at device surface.
Preferably, the material of the substrate 201 is GaAs or InP substrate.
Specifically, the material of the first buffer layer 202 can be binary, ternary or the quaternary of In, Al, Ga, As and Sb
Alloy cpd；The material of the second buffer layer 203 is AlSb.
Preferably, the material of the first buffer layer 202 can be GaAs, thickness 200nm；The second buffer layer
203 material is AlSb, thickness 1500nm.
The material of the lower barrierlayer 205 is AlSb；The material of the channel layer 206 is InAs；The separation layer 207
Material is AlSb；The material of the upper barrier layer 209 is AlSb；The material of the hole blocking layer 210 is InAlAs.
Preferably, the doped layer 208 is mixes the InAs of Si or mixes the AlSb of Te.
Preferably, the material that the cap layers 211 are is the InAs of heavy doping Si.
Preferably, the material of first passivation layer and the second passivation layer is SiO2Or SiNx。
Preferably, the thickness of first passivation layer 204 is equal to the lower barrierlayer 205, channel layer 206, described
Separation layer 207, the doped layer 208, the upper barrier layer 209, the thickness of the hole blocking layer 210 and the cap layers 211
Spend summation.
Preferably, the thickness of first passivation layer 204 is 88.2nm.
Preferably, the thickness of the lower barrierlayer 205 is 50nm, and the thickness of the channel layer 206 is 15nm, the isolation
The thickness of layer 207 is 5nm, and the thickness of the doped layer 208 is 1.2nm, and the thickness of the upper barrier layer 209 is 8nm, the sky
The thickness on cave barrier layer 210 is 4nm, and the thickness of the cap layers 211 is 5nm.
HEMT device provided in this embodiment, solves the metal easy fracture of current HEMT device metal gate, and can make
The problem of raceway groove and short-circuit grid；Meanwhile do not have second buffer layer AlSb as mesa etch stop layer, and lower barrierlayer AlSb
The situation of lattice mismatch；Improve the working performance and stability of HEMT device.
Embodiment three
Further, Fig. 3 a- Fig. 3 f, Fig. 3 a- Fig. 3 f be refer to as another HEMT device provided in an embodiment of the present invention
Preparation method schematic diagram, which includes the following steps：
S301, as shown in Figure 3a, chooses GaAs substrates 001；
S302, as shown in Figure 3b, using molecular beam epitaxy (Molecular Beam Epitaxy, abbreviation MBE) technique,
First buffer layer 002 and second buffer layer 003 are grown on substrate successively；Wherein, the material of the first buffer layer 002 is GaAs
Thing；The material of the second buffer layer 003 is AlSb；
S303, as shown in Figure 3c, utilizes the SiO that pecvd process deposition thickness is 88.2nm2Passivation layer 004；
S304, as shown in Figure 3d, the method for utilizing ICP etchings, etches SiO2Passivation layer 004 is to the second buffer layer
003 forms trench area；
S305, as shown in Figure 3 e, using MBE techniques, potential barrier under the AlSb that growth thickness is 50nm successively in trench area
Layer 005, thickness be 15nm InAs channel layers 006, thickness be 5nm AlSb separation layers 007, thickness be 1.2nm InAs mix
Diamicton 008, thickness are the InAlAs hole blocking layers 010 that barrier layer 009, thickness are 4nm on the AlSb of 8nm and thickness is 5nm
InAs cap layers 011；
S306, as illustrated in figure 3f, by the method for photoetching, corrosion and electron beam evaporation formed grid 012, source electrode 013 and
Drain electrode 014；
S307, utilize pecvd process, deposit SiN passivation layers, to complete the preparation of HEMT device.
The preparation method of HEMT device provided in this embodiment, by setting the first passivation layer in second buffer layer, solution
Existing mesa-isolated of having determined can all make cushioning layer material one in follow-up technique no matter using wet etching or dry etching
Straight exposure is easier to aoxidize in atmosphere, so that the problem of causing device performance degeneration, improves InAs/AlSb HEMT devices
Working performance；Meanwhile using second buffer layer as mesa etch stop layer, will not while the effect of device isolation is ensured
Increase the leakage of gate current, further increase the working performance of HEMT device.
Further, Fig. 4 is refer to, Fig. 4 is InAs/AlSb prepared by a kind of existing process provided in an embodiment of the present invention
HEMT device grid metal is broken pictorial diagram, and it is a critical process prepared by InAs/AlSb HEMTs devices to prepare grid, at present
The grid length of preparation is minimum up to tens nanometers, can there are table top side after using e-book evaporated metal grid after mesa etch
The situation of wall metal fracture, and cause mesa side walls part metals and metal gate to link together, raceway groove and grid can be caused
Short circuit；HEMT device preparation method provided in this embodiment can ensure that subsequent technique carries out in the plane, the HEMT devices of preparation
Grid metal phenomenon of rupture will not occur for part.
Above content is that a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to is assert
The specific implementation of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (10)
- A kind of 1. preparation method of HEMT device, it is characterised in that including：S101, choose substrate material；S102, in the substrate material surface grow first buffer layer and second buffer layer successively；S103, the second buffer layer surface prepare trench area；S104, grow successively in the trench area lower barrierlayer, channel layer, separation layer, doped layer, on barrier layer, hole resistance Barrier and cap layers；S105, prepare grid, source electrode and drain electrode to complete the preparation of the HEMT device.
- 2. preparation method according to claim 1, it is characterised in that S103 includes：S1031, using pecvd process, one passivation layer of growth regulation on the second buffer layer surface；S1032, using ICP lithographic techniques, it is described to be formed until exposing the second buffer layer to etch first passivation layer Trench area.
- 3. preparation method according to claim 1, it is characterised in that the substrate material is GaAs, first buffering The material of layer is GaAs, and the material of the second buffer layer is AlSb.
- 4. preparation method according to claim 1, it is characterised in that the lower barrierlayer, the channel layer, the isolation Layer, the doped layer, the upper barrier layer, the thickness summation of the hole blocking layer and the cap layers are equal to the trench area Depth.
- 5. preparation method according to claim 4, it is characterised in that the depth of the trench area is 80~100nm.
- A kind of 6. HEMT device, it is characterised in that including：Substrate, first buffer layer, second buffer layer, the first passivation layer, lower gesture Barrier layer, channel layer, separation layer, doped layer, upper barrier layer, hole blocking layer, cap layers；Grid, source electrode, drain electrode and the second passivation Layer；Wherein,The first buffer layer, the second buffer layer, the lower barrierlayer, the channel layer, the separation layer, the doping Layer, the upper barrier layer, the hole blocking layer and the cap layers are set in turn on the substrate；First passivation layer is arranged in the second buffer layer, and first passivation layer is formed with the second buffer layer Trench area；The lower barrierlayer, the channel layer, the separation layer, the doped layer, the upper barrier layer, hole resistance Barrier and the cap layers are respectively provided with the trench area；The grid is arranged on the hole blocking layer, and the source electrode and the drain electrode may be contained within the cap layers；Second passivation layer is arranged at device surface.
- 7. HEMT device according to claim 6, it is characterised in that the material of the first buffer layer is GaAs, thickness For 200nm；The material of the second buffer layer is AlSb, thickness 1500nm.
- 8. HEMT device according to claim 6, it is characterised in that the thickness of first passivation layer is equal to the lower gesture Barrier layer, the channel layer, the separation layer, the doped layer, the upper barrier layer, the hole blocking layer and the cap layers Thickness summation.
- 9. HEMT device according to claim 8, it is characterised in that the thickness of first passivation layer is 88.2nm.
- 10. HEMT device according to claim 9, it is characterised in that the lower barrierlayer material is AlSb, and thickness is 50nm；The material of the channel layer is InAs, thickness 15nm；The material of the separation layer is AlSb, thickness 5nm；It is described The material of doped layer is InAs, thickness 1.2nm；The material of the upper barrier layer is AlSb, thickness 8nm；The hole resistance The material of barrier is InAlAs, thickness 4nm；The material of the cap layers is InAs, thickness 5nm.
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| CN105762146A (en) * | 2009-12-23 | 2016-07-13 | 英特尔公司 | Techniques for forming contacts to quantum well transistors |
| US20170092483A1 (en) * | 2014-07-15 | 2017-03-30 | International Business Machines Corporation | Hetero-integration of iii-n material on silicon |
| CN106972056A (en) * | 2017-04-20 | 2017-07-21 | 郑州大学 | The anti-proton irradiation InP-base HEMT device and its processing method being passivated based on BCB |
| CN107123668A (en) * | 2017-04-12 | 2017-09-01 | 西安电子科技大学 | A kind of InAs/AlSb HEMT epitaxial structures and preparation method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762146A (en) * | 2009-12-23 | 2016-07-13 | 英特尔公司 | Techniques for forming contacts to quantum well transistors |
| US20170092483A1 (en) * | 2014-07-15 | 2017-03-30 | International Business Machines Corporation | Hetero-integration of iii-n material on silicon |
| CN107123668A (en) * | 2017-04-12 | 2017-09-01 | 西安电子科技大学 | A kind of InAs/AlSb HEMT epitaxial structures and preparation method thereof |
| CN106972056A (en) * | 2017-04-20 | 2017-07-21 | 郑州大学 | The anti-proton irradiation InP-base HEMT device and its processing method being passivated based on BCB |
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