TW201306252A - Nitride semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device in the present invention includes a nitride semiconductor layer, a first insulation layer disposed on the nitride semiconductor layer, a second insulation layer disposed on the first insulation layer, a first electrode and a second electrode which are disposed separately on the nitride semiconductor layer, a field plate which is disposed on the second insulation layer and between the first electrode and the second electrode and connected to the nitride semiconductor layer by an opening portion that penetrates through the first insulation layer and the second insulation layer. In the opening portion, a first tilt angle between a surface of the nitride semiconductor layer and a sidewall of the first insulation layer is smaller than a second tilt angle between the surface of the nitride semiconductor layer and an elongation surface from a sidewall of the second insulation layer.

Description

Nitride semiconductor device and method of manufacturing same

The present invention relates to a nitride semiconductor device having a field plate in contact with a nitride semiconductor layer and a method of fabricating the same.

In a lateral-type field effect transistor (FET) having an AlGaN/GaN hetero junction, when a high voltage is applied between the source and the drain during the turn-off operation, A strong electric field is generated at the end of the gate on the drain side (hereinafter referred to as "the drain side end portion"). Since a current flows from the drain to the gate depending on the electric field, in order to suppress the amount of leakage at the time of the closing operation, it is desirable to alleviate the electric field at the end portion of the gate on the drain side.

For example, a technique of forming a field plate on an interlayer insulating film between a gate and a drain is proposed (for example, refer to Patent Document 1).

Patent Document 1: (Japanese) JP-A-2008-277604

When an electrode is formed on the nitride semiconductor layer, a protective film which is an insulating film formed on the nitride semiconductor layer is etched to form an opening. An electrode is formed on the protective film in such a manner that the electrode is in contact with the nitride semiconductor layer. In order to avoid damage to the nitride semiconductor layer when forming the opening of the protective film, a "wet etching" process or a "dry etching + wet etching" process is employed.

At this time, the shape of the opening of the interlayer insulating film changes depending on the process accuracy of the wet etching and the adhesion of the interlayer insulating film to the photoresist film. This shape change has an effect on the leakage characteristics. Therefore, in order to obtain stable characteristics of the nitride semiconductor device, it has been desired to form the shape of the opening of the interlayer insulating film with high accuracy.

In order to achieve the above-described requirements, an object of the present invention is to provide a nitride semiconductor device and a method of manufacturing the same, in which an opening portion of an interlayer insulating film on a nitride semiconductor layer can be accurately and stably formed into a shape that moderates concentration of an electric field.

A first aspect of the invention provides a nitride semiconductor device having: a nitride semiconductor layer; a first insulating film disposed on the nitride semiconductor layer; and a second insulating film disposed on the first insulating film; An electrode and a second main electrode which are disposed apart from each other on the nitride semiconductor layer; a field plate disposed on the second insulating film between the first main electrode and the second main electrode via the first insulating film And an opening of the second insulating film is connected to the nitride semiconductor layer. In the opening portion, a surface of the nitride semiconductor layer and a side surface of the first insulating film form a first tilt angle which is larger than a surface of the nitride semiconductor layer and a second insulating layer The second oblique angle formed by the extended line extending from the side of the film is small.

Another aspect of the present invention provides a method of fabricating a nitride semiconductor device for fabricating a nitride semiconductor device having a first main electrode and a second main electrode on a main surface, comprising the steps of: nitride Forming the first on the semiconductor layer a second insulating film is formed on the first insulating film; and a portion of the first insulating film and the second insulating film are selectively etched and removed until a portion of the surface of the nitride semiconductor layer is exposed to form a nitride semiconductor layer The first inclined angle formed by the surface and the side surface of the first insulating film is smaller than the second inclined angle formed by the surface of the nitride semiconductor layer and the extended line extending the side surface of the second insulating film; A field plate is formed on the second insulating film between the electrode and the second main electrode, and the nitride semiconductor layer and the field plate are connected via the opening.

According to the present invention, it is possible to provide a nitride semiconductor device in which the opening portion of the interlayer insulating film on the nitride semiconductor layer is stably formed in a shape that moderately concentrates the concentration of the electric field, and a method of manufacturing the same.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect. In the following description of the drawings, the same or similar parts will be marked with the same or similar. However, the drawings are merely illustrative, and the relationship between the thickness and the plane size, the ratio of the lengths of the respective portions, and the like are different from the actual conditions. Therefore, the specific dimensions should be determined by referring to the following instructions. In addition, it is obvious that the drawings also include mutually different dimensional relationships and ratios. The embodiment shown below shows an apparatus and method for embodying the technical idea of the present invention, and the technical idea of the present invention does not limit the shape, structure, arrangement, and the like of the constituent members to the following. Embodiments of the invention may be within the scope of protection of the claimed patent Make various changes.

As shown in FIG. 1, the nitride semiconductor device 1 of the present embodiment has a nitride semiconductor layer 30, a first insulating film 41 provided on the nitride semiconductor layer 30, and a second insulating layer provided on the first insulating film 41. The film 42, the first main electrode 51 and the second main electrode 52 which are disposed apart from each other on the nitride semiconductor layer 30, and the field provided on the second insulating film 42 between the first main electrode 51 and the second main electrode 52 Field plate 60.

FIG. 1 exemplarily shows a case where the nitride semiconductor device 1 is a High Electron Mobility Transistor (HEMT). That is, the buffer layer 20 is provided on the substrate 10, and the nitride semiconductor layer 30 is provided on the buffer layer 20. A control electrode 53 is provided on the nitride semiconductor layer 30 between the first main electrode 51 and the second main electrode 52. The field plate 60 is connected to the control electrode 53 and disposed between the control electrode 53 and the second main electrode 52.

The field plate 60 is connected to the nitride semiconductor layer 30 via the opening 400, and the opening 400 is provided in the interlayer insulating film 40 in which the first insulating film 41 and the second insulating film 42 are laminated. In one embodiment, the control electrode 53 whose end is connected to the field plate 60 is disposed on the nitride semiconductor layer 30 in such a manner as to be buried in the opening portion 400. Further, the first main electrode 51 and the second main electrode 52 are also in contact with the nitride semiconductor layer 30 at the opening formed in the interlayer insulating film 40.

As shown in Fig. 1, the opening portion 400 is preferably formed in a tapered shape. In one embodiment, the opening portion 400 has a first inclination angle θ 1 of the surface 300 of the nitride semiconductor layer 30 and the side surface 410 of the first insulating film 41, a surface 300 of the nitride semiconductor layer 30, and a second insulating film. The second inclined angle θ 2 formed by the extended line L extended by the side surface 420 of 42 is formed to be small. Therefore, in the cross section perpendicular to the surface 300 of the nitride semiconductor layer 30, the opening portion of the first insulating film 41 and the opening portion of the second insulating film 42 are formed in a trapezoidal shape in which the upper bottom is wider than the lower bottom.

In one embodiment, the first main electrode 51 is used as a source, the second main electrode 52 is used as a drain, and the control electrode 53 is used as a gate, and the transition of the drain side end of the gate is controlled by the field plate 60. The curvature of the depletion layer concentrates on the concentration of the electric field concentrated at the end of the gate of the gate. Therefore, in the nitride semiconductor device 1, leakage current flowing from the drain to the gate during the shutdown operation of the nitride semiconductor device 1 (hereinafter referred to as "gate leakage current") is suppressed.

Further, as shown in FIG. 1, the electric field can be alleviated by imparting inclination to the side surface connected to the bottom surface of the field plate 60 that is in contact with the nitride semiconductor layer 30. Hereinafter, an example in which the electric field relaxation by tilting the bottom of the field plate 60 is verified by 2-dimensional device simulation will be described.

Fig. 2 shows the construction of a device model for two-dimensional element simulation. As the nitride semiconductor layer 30M, a laminated structure in which an AlGaN layer 32M having an Al composition of 0.26 and a film thickness of 25 nm is provided on the undoped GaN layer 31M is used. A source electrode 51M, a drain electrode 52M, and a gate electrode 53M are provided on the nitride semiconductor layer 30M. The gate electrode 53M has a length of 2 μm, and the distance between the gate electrode 53M and the gate electrode 52M is 12 μm. The interlayer insulating film 40M on the nitride semiconductor layer 30M is a yttrium oxide (SiO _x ) film having a film thickness of 500 nm. As shown in Fig. 2, the field plate 60M connected to the gate electrode 53M is provided on the drain side, and the side surface of the interlayer insulating film 40M is inclined at the opening 400M. In addition, two types of component models A and B having different inclination angles θ are set in consideration of the actual component fabrication range. A tilt angle [theta] element model larger than the inclination angle element model B θ.

Fig. 3A and Fig. 3B show the gate leakage current characteristics at the time of the closing operation. The horizontal axis represents the drain-source voltage Vds, and the vertical axis represents the gate leakage current Ig. The gate-source voltage Vgs is -6V. Fig. 3A is a simulation result, and Fig. 3B is a measurement result of an actually fabricated element. The characteristic A is the characteristic of the component model A, and the characteristic B is the characteristic of the component model B. As shown in FIG. 3A, the element model B having a small inclination angle θ suppresses the gate leakage current Ig more than the element model A. As shown in Fig. 3B, the same tendency is also observed in actual components.

The electric field distribution at the end of the gate 53M at the gate voltage of 200 V is shown in Figs. 4A and 4B. Fig. 4A is an electric field distribution of the element model A, and Fig. 4B is an electric field distribution of the element model B. Further, Fig. 4C shows an electric field distribution in the channel direction which is 5 μm deep from the surface of the AlGaN layer 32M. The characteristic A is the characteristic of the component model A, and the characteristic B is the characteristic of the component model B. The horizontal axis of FIGS. 4A to 4C is the distance d from the end portion of the interlayer insulating film 40M on the nitride semiconductor layer 30M, and the vertical axis of FIG. 4C is the magnitude of the electric field. As shown in Figures 4A to 4C, the component model B is larger than the component model. Type A further alleviates the electric field at the end of gate 53M.

As described above, in order to suppress the gate leakage current in order to reduce the concentration of the electric field, it is effective to provide the inclination angle θ at the bottom end portion of the opening portion 400M formed in the interlayer insulating film 40M, and to confirm that the inclination angle θ is smaller. The effect of electric field relaxation is greater. However, when the inclination angle θ is decreased, there is a problem that the area of the opening portion 400M becomes extremely large.

In particular, the thicker the film thickness of the interlayer insulating film, the larger the area of the opening of the upper surface of the interlayer insulating film, and the problem that the area of the nitride semiconductor device increases. On the other hand, it is desirable to increase the film thickness of the interlayer insulating film for the following reasons.

In order to obtain a process margin in the semiconductor fabrication step, each electrode is formed with an area larger than an area of the opening portion in the upper surface of the interlayer insulating film, and therefore, each electrode and the nitride semiconductor layer are formed with an interlayer insulating film interposed therebetween. The opposite area (hereinafter referred to as the "flange portion"). This flange portion functions as a field plate. At this time, it is conventionally known that the field plate electrically connected to the drain electrode deteriorates the current collapse phenomenon. Therefore, in order to reduce the role of the flange portion in the drain as the field plate, it is necessary to increase the thickness of the interlayer insulating film. However, when the thickness of the interlayer insulating film is increased without deteriorating the current collapse phenomenon, the area of the nitride semiconductor device is increased by reducing the inclination angle of the side surface of the interlayer insulating film in order to relax the electric field. .

On the other hand, in the nitride semiconductor device 1 shown in FIG. 1, the interlayer insulating film 40 provided on the nitride semiconductor layer 30 is formed into a two-layer structure of the first insulating film 41 and the second insulating film 42, and The second inclination angle θ 2 formed by the surface 300 of the nitride semiconductor layer 30 and the extension line L extending the side surface 420 of the second insulating film 42 is larger than the surface 300 of the nitride semiconductor layer 30 and the side surface 410 of the first insulating film 41. The opening portion 400 is formed in such a manner that the first inclination angle θ 1 of the configuration is large.

Therefore, in the nitride semiconductor device 1, the effect of relaxing the electric field concentration is improved by reducing the first inclination angle θ1 as much as possible, and by making the second inclination angle θ 2 larger than the first inclination angle θ 1 , it is possible to suppress The area of the opening 400 is increased. In order to alleviate electric field concentration, the first inclination angle θ 1 is, for example, 45° or less, and more preferably 10° to 15°. In order to suppress an increase in the area of the nitride semiconductor device 1, the second inclination angle θ 2 is preferably large. For example, the second inclination angle θ 2 is determined according to the desired area of the opening 400, the desired film thickness of the interlayer insulating film 40, and the like.

As described above, in the nitride semiconductor device 1 according to the embodiment of the present invention, the field plate 60 is brought into contact with the nitride semiconductor layer 30 via the opening portion 400 which is effective in relieving the electric field and has a gentle slope on the side surface. Further, the side surface of the first insulating film 41 having the relaxed first inclination angle θ 1 and the side surface of the second insulating film 42 having the second inclination angle θ 2 larger than the first inclination angle θ 1 constitute the opening portion 400 Tilted sideways. Thereby, according to the nitride semiconductor device 1, the electric field is not moderated without increasing the area of the opening 400, and the gate leakage current is suppressed.

In addition, a nitride semiconductor layer of the nitride semiconductor device 1 as a HEMT 30. As shown in Fig. 1, a structure in which the carrier supply layer 32 and the carrier transport layer 31 which form a heterojunction with the carrier supply layer 32 are laminated.

The carrier transport layer 31 provided on the buffer layer 20 is formed by epitaxial growth of, for example, undoped GaN to which impurities are not added by a metal organic chemical vapor deposition (MOCVD) method or the like. By non-doping is meant that impurities are not intentionally added.

The carrier supply layer 32 provided on the carrier transport layer 31 has a larger energy gap than the carrier transport layer 31, and has a lattice constant smaller than that of the carrier transport layer 31. Composition of a nitride semiconductor. As the carrier supply layer 32, undoped Al _X Ga _1-X N can be used.

The carrier supply layer 32 is formed on the carrier transport layer 31 by epitaxial growth such as MOCVD. Since the lattice constants of the carrier supply layer 32 and the carrier transport layer 31 are different, piezoelectric polarization due to lattice strain occurs. By the piezoelectric polarization and the spontaneous polarization of the crystal of the carrier supply layer 32, high-density carriers are generated on the carrier-transporting layer 31 near the heterojunction, and are formed as current paths (channels). The two-dimensional carrier gas layer 33.

Hereinafter, a method of manufacturing the nitride semiconductor device 1 according to the embodiment of the present invention will be described with reference to FIGS. 5 to 10. Here, a description will be given of a manufacturing method of the nitride semiconductor device 1 shown in FIG. 1 . In addition, the manufacture of the nitride semiconductor device described below The method is one of the embodiments, and those skilled in the art can understand that in the embodiments thereof, the nitride semiconductor device can be fabricated by various manufacturing methods.

(I) As shown in Fig. 5, a buffer layer 20 is formed on the substrate 10. Further, the carrier transport layer 31 and the carrier supply layer 32 are sequentially epitaxially grown on the buffer layer 20 to form the nitride semiconductor layer 30.

(II) Next, as shown in FIG. 6, the first insulating film 41 is formed on the carrier supply layer 32. Further, a second insulating film 42 is formed on the entire surface of the first insulating film 41. In addition, the etching rate of the isotropic etching at the time of forming the opening 400 described later is selected such that at least the second insulating film 42 is larger than the first insulating film 41, and the first insulating film 41 and the second insulating film 42 are selected. material.

(III) Using, for example, a lithography method, as shown in FIG. 7, openings 510 and 520 are formed at predetermined positions of the first insulating film 41 and the second insulating film 42. For example, the first insulating film 41 and the second insulating film 42 which are disposed to form the positions of the first main electrode 51 and the second main electrode 52 are etched away by using the photoresist film as a mask.

(IV) A metal film is formed on the second insulating film 42 so as to embed the openings 510 and 520. Thereafter, the metal film is patterned using a lithography process or the like. Thereby, as shown in FIG. 8, the first main electrode 51 provided in the opening 510 and the second main electrode 52 in which the opening 520 is buried are formed.

(V) Using the photoresist film 90 as an etching mask, the second insulating film 42 at which the position of the control electrode 53 is to be formed is etched away in the thickness direction by an anisotropic etching such as a dry etching process. At this time, as shown in FIG. 9, in the preferred embodiment of the present invention, a portion of the second insulating film 42 remains on the first insulating film 41 because wet etching is used in the subsequent process. When the first insulating film 41 is etched in a state where the second insulating film 42 is not left when the insulating film 41 is removed by etching, a step is likely to occur on the side surface 410 of the first insulating film 41, and the inclined surface may not have the same tilt. Therefore, in the anisotropic etching, it is preferable to remove the second insulating film 42 to the middle in the film thickness direction. For example, the second insulating film 42 is left in a film thickness of about 100 nm to 200 nm.

(VI) Using the photoresist film 90 as an etch mask, an isotropic etching such as a wet etching process is used to remove the remaining portion of the second insulating film 42 and the first insulating film 41 until a part of the surface of the nitride semiconductor layer 30 Exposed. In one embodiment of the present invention, in the isotropic etching, the etching rate of the first insulating film 41 is smaller than the etching rate of the second insulating film 42. Therefore, the second insulating film 42 and the first insulating film 41 are removed by isotropic etching in which the etching rate of the first insulating film 41 is smaller than the etching rate of the second insulating film 42. Therefore, as shown in FIG. 10, the etching result results in the opening portion 400, and the surface 300 of the nitride semiconductor layer 30 and the side surface 410 of the first insulating film 41 constitute a first inclination angle θ 1 which is larger than that of the nitride semiconductor layer 30. The surface 300 is smaller than the second inclination angle θ2 formed by the extension line L that extends the side surface 420 of the second insulating film 42.

(VII) after removing the photoresist film 90, in the second manner in which the opening portion 400 is buried A metal film is formed on the insulating film 42, and the metal film is patterned. Thereby, the field plate 60 is formed together with the control electrode 53 so that the opening 400 is in contact with the nitride semiconductor layer 30. Alternatively, the control electrode 53 and the field plate 60 may be formed using a lift-off method. As described above, the nitride semiconductor device 1 shown in Fig. 1 is completed.

In one embodiment of the present invention, the first insulating film 41 and the second insulating film 42 do not have any special conditions except for the condition that the etching rate of the isotropic etching of the first insulating film 41 is smaller than that of the second insulating film 42. . Therefore, the first insulating film 41 and the second insulating film 42 may be a yttrium oxide (SiO _x ) film, a tantalum nitride (SiN) film, a tetraethoxy decane (TEOS) film or the like which is generally used as an interlayer insulating film. Boron and phosphorus borophosphosilicate glass (BPSG) film, phosphorus-added phosphosilicate glass (PSG) film, and the like.

For example, the first insulating film 41 uses a BPSG film, and the second insulating film 42 uses a SiO _X film or a TEOS film. Alternatively, the first insulating film 41 uses a TEOS film, and the second insulating film uses a SiO _X film.

In another embodiment of the present invention, the first insulating film 41 and the second insulating film 42 may also use the same material. At this time, the first insulating film 41 may be modified such that the etching rate of the first insulating film 41 is smaller than that of the second insulating film 42. For example, after the first insulating film 41 is formed, the etching rate of the first insulating film 41 is reduced by heat treatment or the like. Then, a film of the same material as the first insulating film 41 is formed as the second insulating film 42 on the first insulating film 41.

The film thickness of the first insulating film 41 may be such that the film thickness of the first tilt angle θ 1 can be reliably formed at a desired angle, and varies depending on the process accuracy, and is, for example, about 100 nm to 200 nm. Here, the film thickness of the first insulating film 41 is determined by a specific margin so that the surface 300 of the nitride semiconductor layer 30 is not exposed during dry etching. The film thickness of the second insulating film 42 is set such that the total film thickness of the first insulating film 41 and the second insulating film 42 is a desired interlayer film thickness. For example, the film thickness of the second insulating film 42 is about 250 nm to 1000 nm.

The film thicknesses of the first insulating film 41 and the second insulating film 42 are determined according to the film thickness required for each electrode, the difference between the etching rates of the first insulating film 41 and the second insulating film 42, and the like.

Further, when the BPSG film is used for the first insulating film 41 or the second insulating film 42, a BPSG film is present at a position closer to the nitride semiconductor layer 30. Therefore, it is possible to prevent the influence of floating ions or the like from the outside by the BPSG film, and it is possible to ensure the stability of the potential in the nitride semiconductor device 1 during the operation.

As the substrate 10, a semiconductor substrate such as a bismuth (Si) substrate, a tantalum carbide (SiC) substrate, or a gallium nitride (GaN) substrate, or an insulator substrate such as a sapphire substrate or a ceramic substrate can be used. For example, the substrate 10 can reduce the manufacturing cost of the nitride semiconductor device 1 by using a germanium substrate that is easily large in diameter.

The buffer layer 20 can be formed by an epitaxial growth method such as MOCVD. In Figure 1, The buffer layer 20 is illustrated as one layer, but the buffer layer 20 may also be formed in multiple layers. For example, the buffer layer 20 may be formed to buffer a multilayer structure in which a first sub-layer (first sub-layer) composed of aluminum nitride (AlN) and a second sub-layer (second sub-layer) composed of GaN are alternately laminated. Floor. Further, since the buffer layer 20 is not directly related to the operation of the HEMT, the buffer layer 20 may be omitted. The structure and arrangement of the buffer layer 20 are determined depending on the material of the substrate 10 or the like.

The first main electrode 51 and the second main electrode 52 are formed of a metal that can be in low-resistance contact (ohmic contact) with the nitride semiconductor layer 30. The first main electrode 51 and the second main electrode 52 may be, for example, aluminum (Al), titanium (Ti), or the like. Alternatively, as the laminated structure of Ti and Al, the first main electrode 51 and the second main electrode 52 are formed. For the control electrode 53 and the field plate 60, for example, nickel gold (NiAu) or the like can be used.

As described above, according to the method of manufacturing the nitride semiconductor device 1 of the embodiment of the present invention, the bottom portion having the gentle slope of the end portion of the control electrode 53 at the end portion of the control electrode 53 can be accurately and stably formed. Field plate 60. In particular, by performing isotropic etching on the isotropically etched opening 400 in a state in which the first insulating film 41 and the second insulating film 42 are present, it is possible to stably obtain the edge due to the first insulating film 41 and the second insulating layer. The opening portion 400 having a shape in which the etching rate of the film 42 is poor.

The opening portion 400 can be formed accurately and satisfactorily by combining the anisotropic etching and the isotropic etching as described above, in the case where the opening portion 400 is formed by the isotropic etching only by wet etching. In other words, it is possible to suppress an increase in the opening size of the opening 400, and it is easy to perform fine design and fine processing of the opening 400.

Further, when the laminated insulating film on the nitride semiconductor layer 30 is one layer, it is difficult to relax the inclination of the opening 400. For example, the laminated insulating film 40 is etched and removed in the film thickness direction by anisotropic etching using the photoresist film 90 as a mask as shown in FIG. 11A, and then passed through as shown in FIG. 11B. When the interlayer insulating film 40 is etched and removed to the surface of the nitride semiconductor layer 30, the side surface of the opening 400 is not inclined. When the side surface of the opening 400 is inclined, the area of the opening 400 is increased, and the nitride semiconductor device 1 is increased in size.

Therefore, by laminating the first insulating film 41 and the second insulating film 42 having different etching rates as in the method of manufacturing the nitride semiconductor device 1 according to the embodiment of the present invention, the area of the opening 400 can be prevented from increasing. The inclination of the side surface of the bottom portion of the opening portion 400 can be relaxed. Thereby, it is possible to manufacture the nitride semiconductor device 1 in which the electric field concentration is alleviated and the gate leakage current is suppressed. The structure of the nitride semiconductor device 1 is particularly effective when the thickness of the laminated insulating film 40 is thick, for the reason that the current collapse phenomenon is not deteriorated.

Further, according to the manufacturing method described above, the nitride semiconductor device 1 can be manufactured by a general-purpose device or technology, and a special device and a high process technology are not required.

Further, a part of the upper portion of the nitride semiconductor layer 30 may be etched on the bottom surface of the opening 400 where the control electrode 53 is provided, and the nitride semiconductor device 1 may be formed as a gate recess structure. Thereby, the normally off characteristic can be realized.

[First Modification]

As shown in Fig. 12, a field plate 60S may be provided on the nitride semiconductor layer 30 between the control electrode 53 and the second main electrode 52. The field plate 60S is electrically connected to the first main electrode 51.

By providing the field plate 60S between the control electrode 53 (gate) and the second main electrode 52 (drain), the electric field concentration at the end portion of the gate on the drain side is further alleviated. At this time, as shown in Fig. 12, the first insulating film 41 and the second insulating film are formed in the opening portion of the laminated insulating film 40 embedded in the field plate 60S in the same manner as the opening 400 shown in Fig. 1 . The side surface of 42 is inclined, and the second inclination angle θ 2 of the slope of the second insulating film 42 is larger than the first inclination angle θ 1 of the slope of the first insulating film 41. Therefore, in the nitride semiconductor device 1 shown in FIG. 12, the area of the nitride semiconductor device 1 is not increased to alleviate the electric field, and the gate leakage current can be suppressed.

Further, in the nitride semiconductor device 1 shown in Fig. 12, the side surface of the control electrode 53 facing the second main electrode 52 is shielded by the field plate 60S. Therefore, the Miller capacitance of the nitride semiconductor device 1 can be reduced by electrically connecting the field plate 60S and the first main electrode (source). That is, by disposing the field plate 60S between the gate and the drain, the capacitance between the gate and the drain is lowered. Thereby, the nitride semiconductor device 1 can be operated at a high speed.

[Second Modification]

Fig. 13 shows an example in which the nitride semiconductor device 1 is formed as a Schottky Barrier Diode (SBD). In the nitride semiconductor device 1 shown in FIG. 13 , a carrier semiconductor layer composed of GaN and a carrier supply layer 32 made of an AlGaN film are used as a nitride semiconductor layer, for example, in the case of the HEMT. 30. Further, on the nitride semiconductor layer 30, the anode electrode 71 as the first main electrode and the cathode electrode 72 as the second main electrode are provided separately from each other.

A Schottky junction is formed between the anode electrode 71 and the carrier supply layer 32, and an Ohmic junction is formed between the cathode electrode 72 and the carrier supply layer 32. Thereby, a current flows between the anode electrode 71 and the cathode electrode 72 via the two-dimensional carrier gas layer 33.

In the nitride semiconductor device 1 of the thirteenth aspect, the field plate 60S is connected to the end portion of the anode electrode 71 on the cathode electrode 72 side (hereinafter referred to as "cathode side end portion") to be laminatedly insulated. On the membrane 40. The curvature of the transition layer at the cathode-side end portion of the anode electrode 71 is controlled by the field plate 60, and the concentration of the electric field concentrated on the cathode-side end portion of the anode electrode 71 is alleviated. Therefore, in the nitride semiconductor device 1 described in FIG. 13, the leakage current at the time of the shutdown operation is suppressed.

At this time, as shown in FIG. 13, the opening portion 400 where the anode electrode 71 connected to the field plate 60 and the nitride semiconductor layer 30 are in contact with each other is the same as the opening portion 400 shown in FIG. The side surfaces of the insulating film 41 and the second insulating film 42 are inclined. That is, the first inclination angle θ 1 formed by the surface 300 of the nitride semiconductor layer 30 and the side surface 410 of the first insulating film 41 is longer than the extension of the surface 300 of the nitride semiconductor layer 30 and the side surface 420 of the second insulating film 42. The opening 400 is formed such that the second inclination angle θ 2 of the line L is small.

Therefore, in the nitride semiconductor device 1 shown in Fig. 13, the electric field can be alleviated and the gate leakage current can be suppressed without increasing the area of the nitride semiconductor device 1.

As described above, the present invention has been described by way of embodiments, but the description and drawings which constitute a part of the disclosure are not intended to limit the invention, and those skilled in the art can readily conceive various alternative embodiments from the disclosure. Embodiments and application techniques.

For example, the field plate 60 may be connected to a fixed electrode other than the first main electrode 51 or the control electrode 53 and supplied with a voltage fixed to a constant value. That is, by setting the field plate 60 AC to a constant potential that can be regarded as GND, the electric field concentration of the end portion of the control electrode 53 can be alleviated. Field plate 60 can also be connected to GND.

Thus, the present invention clearly encompasses various embodiments and the like which are not described in the specification. Therefore, the technical scope of the present invention is limited only by the specific matters of the invention in the scope of protection of the claims.

The above description is only a preferred embodiment of the present invention, and the patent application scope according to the present invention Equivalent changes and modifications made are intended to be within the scope of the present invention.

1‧‧‧ nitride semiconductor device

10‧‧‧Substrate

20‧‧‧buffer layer

30‧‧‧ nitride semiconductor layer

30M‧‧‧ nitride semiconductor layer

31‧‧‧carrier transport layer

31M‧‧‧GaN layer

32‧‧‧carrier supply layer

32M‧‧‧AlGaN layer

33‧‧‧Two-dimensional carrier gas

40‧‧‧Interlayer insulating film

51M‧‧‧ source electrode

52‧‧‧second main electrode

520‧‧‧ openings

52M‧‧‧汲electrode

53‧‧‧Control electrode

53M‧‧‧gate electrode

60‧‧‧ field plates

60M‧‧‧Field Plate

60S‧‧‧ Field Plate

90‧‧‧Light resistance

400‧‧‧ openings

40M‧‧‧ interlayer insulating film

41‧‧‧First insulating film

42‧‧‧Second insulation film

51‧‧‧First main electrode

510‧‧‧ openings

400M‧‧‧ openings

410‧‧‧ side

420‧‧‧ side

71‧‧‧Anode electrode

72‧‧‧Cathode electrode

Fig. 1 is a schematic cross-sectional view showing the structure of a nitride semiconductor device according to an embodiment of the present invention.

Fig. 2 is a schematic view showing the structure of a component simulation model of the nitride semiconductor device.

3A and 3B are graphs showing the gate leakage current of the nitride semiconductor device, wherein FIG. 3A is a component simulation result, and FIG. 3B is a measurement result of the fabricated device.

4A to 4C are schematic views showing the electric field distribution of the gate terminal portion, wherein FIG. 4A is the electric field distribution of the element model A, FIG. 4B is the electric field distribution of the element model B, and FIG. 4C is the inside of the nitride semiconductor layer. The electric field distribution in the channel direction.

Fig. 5 is a cross-sectional view (1) for explaining a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.

Fig. 6 is a cross-sectional view (part 2) for explaining a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.

Fig. 7 is a cross-sectional view (part 3) for explaining a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.

Fig. 8 is a cross-sectional view (fourth) for explaining a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.

Fig. 9 is a cross-sectional view (fifth) for explaining a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.

Fig. 10 is a cross-sectional view (sixth) for explaining a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention.

11A and 11B are process cross-sectional views for explaining a method of manufacturing a nitride semiconductor device of a comparative example, in which FIG. 11A shows the shape of the interlayer insulating film after dry etching, and FIG. 11B shows the interlayer after wet etching. The shape of the insulating film.

Fig. 12 is a schematic cross-sectional view showing the structure of a nitride semiconductor device according to a first modification of the embodiment of the present invention.

Fig. 13 is a schematic cross-sectional view showing the structure of a nitride semiconductor device according to a second modification of the embodiment of the present invention.

1‧‧‧ nitride semiconductor device

10‧‧‧Substrate

20‧‧‧buffer layer

30‧‧‧ nitride semiconductor layer

31‧‧‧carrier transport layer

32‧‧‧carrier supply layer

33‧‧‧Two-dimensional carrier gas

300‧‧‧ surface

40‧‧‧Interlayer insulating film

41‧‧‧First insulating film

42‧‧‧Second insulation film

51‧‧‧First main electrode

52‧‧‧second main electrode

53‧‧‧Control electrode

60‧‧‧ field plates

400‧‧‧ openings

410‧‧‧ side

420‧‧‧ side

Claims (6)

A nitride semiconductor device comprising: a nitride semiconductor layer; a first insulating film disposed on the nitride semiconductor layer; a second insulating film disposed on the first insulating film; a first main electrode and a second main electrode disposed on the nitride semiconductor layer separately from each other; and a field plate disposed on the second insulating film between the first main electrode and the second main electrode, and disposed on the second insulating film An opening portion of the first insulating film and the second insulating film is connected to the nitride semiconductor layer, wherein a surface of the nitride semiconductor layer and a side surface of the first insulating film are formed in the opening portion A tilt angle is smaller than a second tilt angle formed by the surface of the nitride semiconductor layer and an extension line extending the side surface of the second insulating film. The nitride semiconductor device according to claim 1, wherein an etching rate of the first insulating film is smaller than an etching rate of the second insulating film. The nitride semiconductor device according to claim 1 or 2, further comprising a control electrode disposed on the nitride semiconductor layer between the first main electrode and the second main electrode, the field A plate is connected to the control electrode and disposed between the control electrode and the second main electrode. A nitride semiconductor device as described in claim 1 or 2, further comprising a control electrode disposed on the nitride semiconductor layer between the first main electrode and the second main electrode, the field plate being disposed between the control electrode and the second main electrode And on the layer, and the field plate is electrically connected to the first main electrode. The nitride semiconductor device according to claim 1 or 2, wherein either one of the first main electrode and the second main electrode is connected to the field plate. A method of fabricating a nitride semiconductor device for fabricating a nitride semiconductor device having a first main electrode and a second main electrode on a main surface, wherein the manufacturing step includes: forming a first layer on a nitride semiconductor layer An insulating film; a second insulating film is formed on the first insulating film; and a portion of the first insulating film and the second insulating film are selectively removed until a portion of a surface of the nitride semiconductor layer is exposed to the nitrogen a first tilt angle formed by a surface of the semiconductor layer and a side surface of the first insulating film is smaller than a second tilt angle formed by an extension of the surface of the nitride semiconductor layer and an extension of the side surface of the second insulating film Forming an opening; and forming a field plate on the second insulating film between the first main electrode and the second main electrode, and connecting the nitride semiconductor layer and the field plate via the opening.