CN106601791A - Metal oxide semiconductor HEMT (High Electron Mobility Transistor) and manufacture method thereof - Google Patents
Metal oxide semiconductor HEMT (High Electron Mobility Transistor) and manufacture method thereof Download PDFInfo
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- CN106601791A CN106601791A CN201510671936.1A CN201510671936A CN106601791A CN 106601791 A CN106601791 A CN 106601791A CN 201510671936 A CN201510671936 A CN 201510671936A CN 106601791 A CN106601791 A CN 106601791A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 19
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims description 71
- 241000446313 Lamella Species 0.000 claims description 34
- 229910002704 AlGaN Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 238000002360 preparation method Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- VYMDGNCVAMGZFE-UHFFFAOYSA-N phenylbutazonum Chemical compound O=C1C(CCCC)C(=O)N(C=2C=CC=CC=2)N1C1=CC=CC=C1 VYMDGNCVAMGZFE-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
The invention provides a metal oxide semiconductor HEMT and a manufacture method thereof. The HEMT comprises a substrate, and an epitaxial wafer layer, a first insulating layer, a second insulating layer, a grid electrode, source electrode and drain electrodes and a third insulating layer arranged on the substrate successively; and the grid electrode extends to the upper surface of the second insulating layer to form a grid field plate. The grid electrode extends to form the grid field plate to reduce the surface electric field of a device, improve the breakdown voltage of the device and improve the voltage withstanding performance of the device.
Description
Technical field
The present invention relates to semiconductor device fabrication process technical field, more particularly to a kind of metal oxygen
Compound semiconductor HEMT and preparation method thereof.
Background technology
With the increasingly increase of efficiently complete circuit for power conversion and system requirements, with low work(
The power device of consumption and high speed characteristics has attracted recently many concerns.GaN is third generation broad stopband
Semi-conducting material, because it has big energy gap (3.4eV), high electron saturation velocities
(2e7cm/s), high breakdown electric field (1e10--3e10V/cm), higher heat-conductivity, it is corrosion-resistant and
Radiation resistance, has under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition
Stronger advantage, it is considered to be research shortwave opto-electronic device and high voltagehigh frequency rate high power device
Optimal material.GaN base AlGaN/GaN high mobility transistor is the research in power device
Focus, this is because AlGaN/GaN suppresses the two dimension electricity that high concentration, high mobility are formed at knot
Sub- gas (2DEG), while hetero-junctions has good adjustment effect to 2DEG.
Because electron concentration is very high in the two-dimensional electron gas of AlGaN/GaN hetero-junctions, if only
Field plate and unadulterated AlGaN/GaN, the gate edge electric field density of device is very big, it may occur that
Oxide layer punctures in advance.
The content of the invention
For defect of the prior art, the invention provides a kind of metal-oxide semiconductor (MOS) is high
Electron mobility transistor and preparation method thereof, by the way that grid is extended grid field plate is formed, so as to
Device surface electric field is reduced, the breakdown voltage of device is improved, the resistance to pressure of device is improve.
According to an aspect of the invention, there is provided a kind of high electronics of metal-oxide semiconductor (MOS) is moved
Shifting rate transistor, it is characterised in that include：Substrate, set gradually over the substrate it is outer
Prolong lamella, the first insulating barrier, the second insulating barrier, grid, source electrode and drain electrode and the 3rd insulation
Layer；
Wherein, the grid extends to the upper surface formation grid field plate of second insulating barrier.
Wherein, the epitaxial layer includes GaN, the unadulterated GaN of the miscellaneous P doping for setting gradually
With unadulterated AlGaN.
Wherein, the material of first insulating barrier be SiN, second insulating barrier and the described 3rd
The material of insulating barrier is silicon oxide film.
Wherein, the grid is by the first mistake through first insulating barrier and the second insulating barrier
Hole is connected with the extension lamella, and the bottom of the grid is located inside the epitaxial layer.
Wherein, the source electrode is by the second mistake through first insulating barrier, the second insulating barrier
Hole contacts with the extension lamella.
Wherein, the drain electrode is by the 3rd mistake through first insulating barrier, the second insulating barrier
Hole contacts with the extension lamella.
According to another aspect of the present invention, there is provided a kind of preceding claim metal oxide half
The preparation method of conductor HEMT, it is characterised in that include：
Extension lamella is grown on underlay substrate；
The first insulating barrier and the second insulating barrier are sequentially depositing on the extension lamella；
Grid, source electrode and drain electrode are formed respectively, and the grid is by the first via and the extension
Lamella connects, and the top of the grid extends to the upper surface of second insulating barrier and formed
Grid field plate, the source electrode is contacted by the second via with the extension lamella, and the drain electrode passes through
3rd via is contacted with the extension lamella；
Deposit the 3rd insulating barrier.
Wherein, formed before grid, source electrode and drain electrode respectively, methods described also includes：
First, second, and third through first insulating barrier and the second insulating barrier is formed respectively
Via；
Wherein, the bottom of first via is embedded in the extension lamella.
Wherein, the extension lamella includes GaN, the unadulterated GaN of the P doping for setting gradually
With unadulterated AlGaN.
Wherein, the 3rd insulating barrier be covered in the grid, source electrode, drain electrode, grid field plate with
And second insulating barrier upper surface.
A kind of metal-oxide semiconductor (MOS) HEMT of the present invention and its making side
Method, forming grid field plate by the way that grid is extended, and with reference to grid field plate and RESURF technologies, grid
Field plate is by suppressing current collapse to improve breakdown characteristic of device；RESURF technologies make Two-dimensional electron
Electronics exhausts in vertical direction in gas, so as to reduce device surface electric field, improves device
Breakdown voltage, improves the resistance to pressure of device.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below
The accompanying drawing to be used needed for embodiment or description of the prior art will be briefly described, show and
Easy insight, drawings in the following description are only some embodiments of the present invention, for this area
For those of ordinary skill, on the premise of not paying creative work, can be with according to these
Figure obtains other accompanying drawings.
Fig. 1 to Fig. 4 is that a kind of metal-oxide semiconductor (MOS) that one embodiment of the invention is provided is high
The manufacturing process schematic diagram of electron mobility transistor.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, to the technical side in the embodiment of the present invention
Case is clearly and completely described, it is clear that described embodiment is only the present invention one
Divide embodiment, rather than the embodiment of whole.Based on the embodiment in the present invention, this area is general
The every other embodiment that logical technical staff is obtained under the premise of creative work is not made,
Belong to the scope of protection of the invention.
Fig. 4 shows a kind of metal-oxide semiconductor (MOS) high electron mobility that the present embodiment is provided
The structural representation of transistor, as shown in figure 4, the transistor includes：Underlay substrate 100, according to
The secondary extension lamella 200 being arranged on the underlay substrate 100, the first insulating barrier 300, second are exhausted
Edge layer 400, source electrode 310, grid 320 and the insulating barrier 500 of drain electrode 330 and the 3rd, wherein,
The grid 320 extends to the upper surface of second insulating barrier 400 and forms grid field plate 340.
By by grid and grid field in above-mentioned metal-oxide semiconductor (MOS) HEMT
Plate is integrally formed by same patterning processes, reduces processing step, saves cost, passes through
Grid field plate is set, current collapse can be suppressed to improve the breakdown characteristics of device, reduce device
Surface field near grid, improves the pressure of device.
One of the present embodiment preferred embodiment in, the present embodiment also adopts RESURF
Technology makes electronics in two-dimensional electron gas exhaust in vertical direction, device surface electric field is reduced, with this
To improve the breakdown voltage of the metal oxide semiconductor device.
Specific above-mentioned RESURF technologies can be understood as the above-mentioned undoped p of extension lamella 200
GaN220 and AlGaN230 and underlay substrate 100 between insert P doping GaN210, pass through
The GaN of insertion P doping causes the electric field near device surface to be able to be distributed and weaken, so as to improve
The breakdown voltage of device surface.
It will be appreciated that for HEMT (High Electron Mobility
Transistor, abbreviation HEMT), breakdown voltage is mainly limited by gate edge high electric field,
The GaN of P doping is inserted below unadulterated AlGaN/GaN layers, two-dimensional electron gas can be made
Generation vertical depletion, so as to reduce the surface field near device grids, improves the pressure of device.
Specifically, in the above-described embodiments, the material of first insulating barrier 300 be SiN, institute
The material for stating the second insulating barrier 400 and the 3rd insulating barrier 500 is silicon oxide film, but first
The material of insulating barrier, the second insulating barrier and the 3rd insulating barrier can also be using being used in prior art
The other materials of such device, here is not specifically limited.Formed on above-mentioned extension lamella 200
First insulating barrier 300 and the second insulating barrier 400, it can not only improve not mixing on extension lamella
The defect of miscellaneous AlGaN interfacial states, additionally it is possible to make the first insulating barrier 300 and the second insulating barrier 400 it
Between degree of adhesion preferably, be less prone to the situation of non-bonding.
One of the present embodiment preferred embodiment in, source electrode 310 is by through described first
The via of insulating barrier 300 second is contacted with the epitaxial layer 200, and the source lead 410 is in the source
The corresponding position in pole 310 is by the 5th via and the source electrode through second insulating barrier 400
310 electrical connections.
Drain electrode 330 is described by contacting with epitaxial layer 200 through the via of the first insulating barrier 300 the 3rd
Drain lead 430 is in 330 corresponding positions of the drain electrode by through second insulating barrier 400
The 6th via 330 electrically connect with the drain electrode.
Grid 320 is connected by the first via through the first insulating barrier 300 with epitaxial layer 200.Need
It is noted that the GaN high electron mobility transistor in the present embodiment can be understood as increasing
The MOS of strong type, therefore above-mentioned gate pattern 72 can be connected by the first via with extension lamella, and
Go deep into the intra-zone of the unadulterated AlGaN of extension lamella.
Further, grid 320 extends on the surface of the second insulating barrier 400 and forms grid field plate 340,
Grid field plate is formed by the way that grid is extended, and with reference to RESURF technologies, grid field plate is by suppressing electricity
Flow avalanche to improve breakdown characteristic of device；RESURF technologies make in two-dimensional electron gas electronics vertical
Direction exhausts, and so as to reduce device surface electric field, improves the breakdown voltage of device, improves
The resistance to pressure of device.
In another embodiment of the present invention, there is provided a kind of high electricity of metal-oxide semiconductor (MOS)
The preparation method of transport factor transistor, as Figure 1-4, the method specifically includes following steps：
S1, on underlay substrate grow extension lamella；
As shown in figure 1, sequentially forming GaN210, the undoped p of P doping on underlay substrate 100
GaN220 and unadulterated AlGaN230 as epitaxial layer 200, in the present embodiment, by
The GaN of P doping is inserted between unadulterated GaN and substrate so that the electric field of device surface annex
It is able to be distributed and weakens, so as to improves the breakdown voltage of device surface.
S2, it is sequentially depositing on the extension lamella the first insulating barrier and the second insulating barrier；
As shown in Fig. 2 in one embodiment, the material of the first insulating barrier 300 is SiN, second
The material of insulating barrier 400 is silicon oxide film.
103rd, form grid, source electrode and drain electrode respectively, the grid by the first via with it is described
Extension lamella connects, and the top of the grid extends to the upper surface of second insulating barrier
Grid field plate is formed, the source electrode is contacted by the second via with the extension lamella, the drain electrode
Contacted with the extension lamella by the 3rd via；
Specifically, as shown in figure 3, etching shape on the first insulating barrier 300 and the second insulating barrier 400
Into first, second and the 3rd via, for forming grid 320, source electrode 310 and drain electrode respectively
330, specifically, the bottom of the first via extends to the inside of epitaxial layer 200.Grid 320 passes through
Second via is contacted with epitaxial layer 200, is missed 330 and is connected with epitaxial layer by the 3rd via.
In addition, during grid 320 is formed, by grid 320 in the upper table of the second insulating barrier 400
Face extends, and forms grid field plate 340, i.e., in etching grid 320, in being located at for grid layer metal
Region etch around grid forms grid field plate 340.
The process of above-mentioned formation grid, source electrode and drain electrode can be with the process of formation in prior art
Unanimously, the present embodiment is not defined to its forming process.
S4, the 3rd insulating barrier of deposition.
As shown in figure 4, on the surface of source electrode, grid, drain electrode, grid field plate and the second insulating barrier
Deposit the 3rd insulating barrier.
It will be appreciated that in the manufacturing process of above-mentioned transistor, each layer such as extension lamella,
One insulating barrier, the second insulating barrier, barrier metal layer, the 3rd insulating barrier, metal level etc. can pass through
The mode of vacuum moulding machine or magnetron sputtering is formed, and the present embodiment is no longer described in detail.
By above-mentioned technical process, shape is extended on the surface of the second insulating barrier 400 in grid 320
Into grid field plate 340, can be by suppressing current collapse to improve breakdown characteristic of device, so as to improve
The breakdown voltage of device, improves the resistance to pressure of device.
Above example only to illustrate technical scheme, rather than a limitation；Although
The present invention is described in detail with reference to the foregoing embodiments, one of ordinary skill in the art
It should be understood that；It still can modify to the technical scheme described in foregoing embodiments,
Or equivalent is carried out to which part technical characteristic；And these modifications or replacement, not
Make the spirit and scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution.
Claims (10)
1. a kind of metal-oxide semiconductor (MOS) HEMT, it is characterised in that bag
Include：Substrate, set gradually extension lamella over the substrate, the first insulating barrier, second exhausted
Edge layer, grid, source electrode and drain electrode and the 3rd insulating barrier；
Wherein, the grid extends to the upper surface formation grid field plate of second insulating barrier.
2. metal-oxide semiconductor (MOS) HEMT according to claim 1,
Characterized in that, the epitaxial layer includes GaN, the unadulterated GaN of the miscellaneous P doping for setting gradually
With unadulterated AlGaN.
3. metal-oxide semiconductor (MOS) HEMT according to claim 1,
Characterized in that, the material of first insulating barrier is SiN, second insulating barrier and described the
The material of three insulating barriers is silicon oxide film.
4. the metal-oxide semiconductor (MOS) high electron mobility according to any one of claim 1-3
Rate transistor, it is characterised in that the grid is by exhausted through first insulating barrier and second
First via of edge layer is connected with the extension lamella, and the bottom of the grid is positioned at described
Inside epitaxial layer.
5. the metal-oxide semiconductor (MOS) high electron mobility according to any one of claim 1-3
Rate transistor, it is characterised in that the source electrode is by through first insulating barrier, second exhausted
Second via of edge layer is contacted with the extension lamella.
6. the metal-oxide semiconductor (MOS) high electron mobility according to any one of claim 1-3
Rate transistor, it is characterised in that the drain electrode is by through first insulating barrier, second exhausted
3rd via of edge layer is contacted with the extension lamella.
7. the metal-oxide semiconductor (MOS) HEMT described in a kind of claim 1-6
Preparation method, it is characterised in that include：
Extension lamella is grown on underlay substrate；
The first insulating barrier and the second insulating barrier are sequentially depositing on the extension lamella；
Grid, source electrode and drain electrode are formed respectively, and the grid is by the first via and the extension
Lamella connects, and the top of the grid extends to the upper surface of second insulating barrier and formed
Grid field plate, the source electrode is contacted by the second via with the extension lamella, and the drain electrode passes through
3rd via is contacted with the extension lamella；
Deposit the 3rd insulating barrier.
8. preparation method according to claim 7, it is characterised in that formed respectively grid,
Before source electrode and drain electrode, methods described also includes：
First, second, and third through first insulating barrier and the second insulating barrier is formed respectively
Via；
Wherein, the bottom of first via is embedded in the extension lamella.
9. preparation method according to claim 8, it is characterised in that the extension lamella
Including GaN, the unadulterated GaN and unadulterated AlGaN of the P doping for setting gradually.
10. preparation method according to claim 8, it is characterised in that the 3rd insulation
Layer is covered in the upper surface of the grid, source electrode, drain electrode, grid field plate and the second insulating barrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510671936.1A CN106601791A (en) | 2015-10-15 | 2015-10-15 | Metal oxide semiconductor HEMT (High Electron Mobility Transistor) and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510671936.1A CN106601791A (en) | 2015-10-15 | 2015-10-15 | Metal oxide semiconductor HEMT (High Electron Mobility Transistor) and manufacture method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008258419A (en) * | 2007-04-05 | 2008-10-23 | Toshiba Corp | Nitride semiconductor device |
| US20090189187A1 (en) * | 2007-01-10 | 2009-07-30 | Briere Michael A | Active area shaping for Ill-nitride device and process for its manufacture |
| CN102891171A (en) * | 2011-07-21 | 2013-01-23 | 联华电子股份有限公司 | Nitride semiconductor device and manufacturing method thereof |
| CN103456781A (en) * | 2012-06-04 | 2013-12-18 | 英飞凌科技奥地利有限公司 | Compound semiconductor transistor with self aligned gate |
-
2015
- 2015-10-15 CN CN201510671936.1A patent/CN106601791A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090189187A1 (en) * | 2007-01-10 | 2009-07-30 | Briere Michael A | Active area shaping for Ill-nitride device and process for its manufacture |
| JP2008258419A (en) * | 2007-04-05 | 2008-10-23 | Toshiba Corp | Nitride semiconductor device |
| CN102891171A (en) * | 2011-07-21 | 2013-01-23 | 联华电子股份有限公司 | Nitride semiconductor device and manufacturing method thereof |
| CN103456781A (en) * | 2012-06-04 | 2013-12-18 | 英飞凌科技奥地利有限公司 | Compound semiconductor transistor with self aligned gate |
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Application publication date: 20170426 |