JP5619854B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor made of a nitride compound semiconductor.

  A semiconductor device using a group III-V nitride compound semiconductor is promising as a high-temperature operation, high-power, high-speed device due to the characteristics inherent in the material. In particular, GaN-based semiconductor devices are expected to be applied as power supply devices because they can operate at a large current.

  2. Description of the Related Art Conventionally, in a field effect transistor made of a nitride-based compound semiconductor, RESURF (REduced SURface Field, RESURF) for the purpose of alleviating electric field concentration by performing ion implantation in regions where source and drain electrodes that are ohmic electrodes are to be formed ) Has been disclosed (see, for example, Non-Patent Document 1).

  On the other hand, in Patent Document 1, a carrier supply layer made of AlGaN or the like is etched off until reaching the carrier traveling layer in the gate portion to form a recess portion, and an oxide insulating layer is formed in the recess portion to form a MOS structure. Thus, a field effect transistor is disclosed which has both a high breakdown voltage as an on characteristic and a low on resistance as an off characteristic.

International Publication No. 2003/071607

Matocha. K, Chow. T.P, Gutmann. R.J., “High-voltage normally off GaN MOSFETs on sapphire substrates”, IEEE Transaction on Electron Devices. Vol. 52, No. 1 2005 pp. 6-10

  However, in the field effect transistor disclosed in Patent Document 1, when a voltage is applied between the source and the drain, the electric field concentrates on a right-angled corner formed by the bottom surface and the side wall of the recess portion, and the withstand voltage decreases. There was a problem that there might be.

  The present invention has been made in view of the above, and an object of the present invention is to provide a field effect transistor that can realize high breakdown voltage more reliably.

  In order to solve the above-described problems and achieve the object, a field effect transistor according to the present invention is a field effect transistor made of a nitride compound semiconductor, and includes a carrier traveling layer formed on a substrate, and the carrier A carrier supply layer formed on the running layer and having a conductivity type opposite to the carrier running layer, separated by a recess formed to a depth reaching the inside of the carrier running layer, and each separated carrier supply A source electrode and a drain electrode formed on the layer with the recess portion interposed therebetween, and a gate insulating film formed on the separated carrier supply layer so as to cover a surface of the carrier traveling layer in the recess portion, A gate electrode formed on the gate insulating film in the recess, and from the upper surface of the carrier supply layer of the recess Depth, wherein the at greater 200nm or less than the layer thickness of the carrier supply layer.

  The field effect transistor according to the present invention is a field effect transistor made of a nitride compound semiconductor, and is formed on a substrate, on the lower semiconductor layer, and in the lower semiconductor layer. An undoped carrier traveling layer separated by a recess formed to a depth up to a depth, formed on each of the separated carrier traveling layers, a carrier supply layer having a band gap energy different from each carrier traveling layer, and A source electrode and a drain electrode formed on each carrier supply layer with the recess interposed therebetween, and a gate insulating film formed on the carrier supply layer so as to cover the surface of the lower semiconductor layer in the recess A gate electrode formed on the gate insulating film in the recess portion, and the front of the recess portion Depth from the carrier supply layer upper surface, wherein said at carrier supply layer than larger 200nm than the sum of the layer thickness of the carrier transit layer.

  In the field effect transistor according to the present invention as set forth in the invention described above, the carrier transit layer has a p-type conductivity type.

  In the field effect transistor according to the present invention as set forth in the invention described above, the lower semiconductor layer has a p-type conductivity.

  In the field effect transistor according to the present invention as set forth in the invention described above, the lower semiconductor layer and the carrier transit layer are made of GaN, and the carrier supply layer is made of AlGaN.

  The field effect transistor according to the present invention is characterized in that, in the above invention, the recess is formed by etching.

  According to the present invention, local electric field concentration between the source and the drain can be surely prevented, so that it is possible to more reliably realize a field effect transistor having a high breakdown voltage.

2 is a schematic cross-sectional view of a MOSFET according to the first embodiment. FIG. It is a figure explaining an example of the manufacturing method of MOSFET shown in FIG. It is a figure explaining an example of the manufacturing method of MOSFET shown in FIG. 6 is a schematic cross-sectional view of a MOSFET according to a second embodiment. FIG. It is the figure which showed the relationship between the recess part depth of MOSFET which concerns on an Example, and a comparative example, and the normalization pressure | voltage resistance. It is the figure which showed the relationship between the recess part depth of MOSFET which concerns on an Example, and a comparative example, and normalized on-resistance.

  Embodiments of a field effect transistor according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Hereinafter, the MOS field effect transistor is referred to as a MOSFET.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of a MOSFET according to Embodiment 1 of the present invention. This MOSFET 100 is a carrier traveling layer 103 made of p-GaN formed on a substrate 101 made of sapphire, SiC, Si or the like via a buffer layer 102 formed by alternately laminating AlN layers and GaN layers. It has. The buffer layer 102 is formed by stacking, for example, eight GaN / AlN composite layers having a thickness of 200 nm / 20 nm. The carrier traveling layer 103 has a thickness of about 700 nm.

The MOSFET 100 includes carrier supply layers 104 a and 104 b formed on the carrier traveling layer 103. These carrier supply layers 104a and 104b are made of n-GaN having a conductivity type opposite to that of the carrier traveling layer 103, and have a thickness of, for example, 50 to 100 nm. The carrier supply layers 104 a and 104 b are separated by a recess 105 formed to a depth reaching the carrier traveling layer 103. The width of the recess 105 is, for example, about 2 μm. Further, the MOSFET 100 includes a source electrode 106 and a drain electrode 107 formed on the carrier supply layers 104a and 104b with the recess 105 interposed therebetween. Further, MOSFET 100 includes a gate insulating film 108 made of SiO ₂ or the like so as to cover the surface of carrier running layer 103 in recess 105 over carrier supply layers 104a and 104b. A gate electrode 109 formed on the gate insulating film 108 is provided to constitute a MOS structure. The distance between the source electrode 106 and the drain electrode 107 is, for example, about 30 μm.

  Here, in this MOSFET 100, the depth D1 of the recess 105 from the upper surface of the carrier supply layers 104a and 104b is greater than or equal to the thickness of the carrier supply layers 104a and 104b and less than or equal to 200 nm. As a result, in this MOSFET 100, when a voltage is applied between the source and the drain, electric field concentration on the right-angled corner formed by the bottom and side walls of the recess 105 is prevented. In addition, since the electric lines of force generated from the drain electrode 107 terminate at the end of the carrier supply layer 104a on the gate electrode 109 side, the carrier supply layer 104b also functions as a RESURF layer. As a result, the source-drain withstand voltage of the MOSFET 100 is maintained at the same level as the original withstand voltage when the stacked structure of the semiconductor layers stacked on the substrate 101 is not provided with the recess portion 105, so that high withstand voltage can be realized.

  Further, in the MOSFET in which the recess portion is formed like this MOSFET 100, a high-resistance channel region is formed on the side wall of the recess portion, thereby increasing the on-resistance. However, in this MOSFET 100, by setting the depth D1 of the recess portion 105 to 200 nm or less, the length of the high-resistance channel region formed on the sidewall of the recess portion 105 can be sufficiently shortened, thereby increasing the on-resistance. It is suppressed and the value can be kept small. Therefore, this MOSFET 100 can realize a low on-resistance in addition to a high breakdown voltage.

  Note that the above-described problems of electric field concentration and formation of a high-resistance channel region are likely to occur only due to the depth of the recess portion 105. Therefore, regardless of the distance between the source and the drain and the width of the recess 105, if the depth D1 of the recess 105 is 200 nm or less, high breakdown voltage and low on-resistance can be realized.

  Next, a method for manufacturing the MOSFET 100 will be described. 2 and 3 are explanatory diagrams for explaining an example of a method for manufacturing MOSFET 100. FIG. In the following, the case where the metal organic chemical vapor deposition (MOCVD) method is used will be described, but there is no particular limitation.

First, as shown in FIG. 2, for example, a buffer layer 102 and a carrier traveling layer 103 are sequentially epitaxially grown on a substrate 101 made of Si having a (111) plane as a main surface. When growing the carrier traveling layer 103, for example, Mg is added as a p-type impurity at a concentration of about 1 × 10 ¹⁷ cm ⁻³ . Further, the n-GaN layer 104 to be the carrier supply layers 104a and 104b is epitaxially grown on the carrier running layer 103 with a desired thickness. When the n-GaN layer 104 is grown, for example, Si is added as an n-type impurity at a concentration of about 1 × 10 ¹⁷ cm ⁻³ . Next, a photoresist is applied to the surface of the n-GaN layer 104, a pattern for element isolation is formed using a photolithography process, and then a deep etching is performed using a dry etching method such as a reactive ion etching (RIE) method. A trench g for element isolation having a thickness of about 200 nm is formed. Thereafter, the photoresist is removed.

  Next, as shown in FIG. 3, the n-GaN layer 104 in the region to be the gate region is etched away to a depth reaching the carrier traveling layer 103 to form a recess portion 105. As a result, the n-GaN layer 104 is separated, and carrier supply layers 104a and 104b are formed. For example, the recess 105 is formed as follows. That is, for example, a plasma chemical vapor deposition (PCVD) method is used to form a mask layer made of amorphous silicon (a-Si) on the n-GaN layer 104 with a thickness of 500 nm, and patterning is performed using a photolithography process. Then, an opening is formed in a region where the recess 105 is to be formed. Then, using the mask layer as a mask, the dry etching method is used to etch away the region of the n-GaN layer 104 corresponding to the opening of the mask layer to a depth reaching the carrier traveling layer 103, and then remove the mask layer. To do.

Here, when performing the etching, the depth D1 of the recess 105 is adjusted to be not less than the thickness of the carrier supply layers 104a and 104b and not more than 200 nm by adjusting the etching depth. That is, when the thickness of the carrier supply layers 104a and 104b is 50 nm, the depth D1 is set to 50 to 200 nm. The etching depth can be easily controlled, for example, by adjusting the flow rate of the etching gas and the etching time. For example, when Cl ₂ gas is used as the etching gas, the gas flow rate may be 10 sccm and the etching time may be 100 to 300 seconds in order to set the etching depth to 50 to 200 nm.

Next, a thickness of SiO _{2 is used} so as to cover the surface of the carrier traveling layer 103 in the recess 105 over the carrier supply layers 104a and 104b by using a PCVD method using SiH ₄ and N ₂ O as source gases. A gate insulating film 108 having a thickness of 60 nm is formed. Next, part of the gate insulating film 108 is removed with hydrofluoric acid, and the drain electrode 107 and the source electrode 106 are formed over the carrier supply layers 104a and 104b, respectively, using a lift-off method. The drain electrode 107 and the source electrode 106 are in ohmic contact with the carrier supply layers 104a and 104b, for example, have a Ti / Al structure with a thickness of 25 nm / 300 nm. The metal film to be used as an electrode can be formed by using a sputtering method or a vacuum evaporation method. Then, after forming the source electrode 106 and the drain electrode 107, annealing is performed at 600 ° C. for 10 minutes.

  Next, a gate electrode 109 having a Ti / Au / Ti structure is formed in the recess portion 105 by using a lift-off method, and the MOSFET 100 shown in FIG. 1 is completed.

  As described above, in the MOSFET 100 according to the first embodiment, the depth D1 from the upper surface of the carrier supply layers 104a and 104b of the recess 105 is not less than the thickness of the carrier supply layers 104a and 104b and not more than 200 nm. Therefore, in addition to high breakdown voltage, the MOSFET can realize low on-resistance.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. The MOSFET according to the second embodiment is a MOSFET that uses a two-dimensional electron gas as a carrier.

  FIG. 4 is a schematic cross-sectional view of the MOSFET according to the second embodiment. This MOSFET 200 includes a lower semiconductor layer 210 made of p-GaN formed on a substrate 201 similar to the substrate 101 of the MOSFET 100 according to the first embodiment via a buffer layer 202 similar to the buffer layer 102. Yes. The lower semiconductor layer 210 has a thickness of about 700 nm.

  The MOSFET 200 includes carrier traveling layers 203 a and 203 b that are formed on the lower semiconductor layer 210 and separated by a recess portion 205 formed to a depth reaching the lower semiconductor layer 210. These carrier running layers 203a and 203b are made of undoped u-GaN and have a thickness of 50 to 100 nm. Further, the MOSFET 200 includes carrier supply layers 204a and 204b formed on the carrier running layers 203a and 203b, respectively. These carrier supply layers 204a and 204b are made of AlGaN having a band gap energy higher than that of GaN constituting the carrier running layers 203a and 203b, and have a thickness of 20 to 25 nm. The carrier running layers 203a and 203b have an Al composition ratio of 25%, but the Al composition is not particularly limited and can be, for example, 10 to 30%.

  Further, like the MOSFET 100, the MOSFET 200 includes a source electrode 206 and a drain electrode 207 formed between the carrier supply layers 204a and 204b with the recess portion 205 interposed therebetween, and the carrier supply layers 204a and 204b in the recess portion 205. A gate insulating film 208 formed so as to cover the surface of the lower semiconductor layer 210 and a gate electrode 209 formed on the gate insulating film 208 in the recess portion 205 constitute a MOS structure. The distance between the source electrode 206 and the drain electrode 207 is, for example, about 30 μm. The width of the recess portion 205 is, for example, about 2 μm.

  In this MOSFET 200, due to the difference in energy band gap between the carrier travel layers 203a and 203b and the carrier supply layers 204a and 204b, the carrier travels to the interface with the carrier supply layers 204a and 204b in the carrier travel layers 203a and 203b. Two-dimensional electron gases Ga and Gb having a high degree are generated. The MOSFET 200 operates at high speed by using the two-dimensional electron gases Ga and Gb as carriers.

  Further, in this MOSFET 200, the depth D2 from the upper surface of the carrier supply layers 204a and 204b of the recess portion 205 is not less than the total thickness of the carrier supply layers 204a and 204b and the carrier running layers 203a and 203b and not more than 200 nm. Has been. As a result, in this MOSFET 200, like the MOSFET 100, when a voltage is applied between the source and the drain, electric field concentration at the right corner formed by the bottom surface and the side wall of the recess portion 205 is prevented. In addition, since the lines of electric force generated from the drain electrode 207 terminate at the end of the two-dimensional electron gas Ga on the gate electrode 209 side, the two-dimensional electron gas Ga also functions as a RESURF layer. As a result, the source-drain withstand voltage of the MOSFET 200 is maintained at the same level as the inherent withstand voltage of the stacked structure of the semiconductor layers stacked on the substrate 201, so that a high withstand voltage can be realized.

  Further, regarding the off characteristics of the MOSFET 200, the on-resistance can be reduced by using the two-dimensional electron gas as a carrier, and the on-resistance can be increased by setting the depth D2 of the recess portion 205 to 200 nm or less. Is suppressed and the value is kept small. Therefore, the MOSFET 200 is a MOSFET that can operate at high speed and can achieve high withstand voltage and low on-resistance.

  The MOSFET 200 can be manufactured by a manufacturing method substantially similar to that of the MOSFET 100.

(Examples and comparative examples)
As Examples 1-1 and 1-2 of the present invention, MOSFETs according to the first embodiment were manufactured according to the manufacturing method described above. In each of Examples 1-1 and 1-2, the thickness of the carrier supply layer, which is an n-GaN layer, was 50 nm, and the depth of the recess was about 150 nm. On the other hand, as Comparative Examples 1-1 to 1-16, the depth of the recess portion was set to 210 to 390 nm. Otherwise, MOSFETs similar to Example 1-1 were manufactured.

  Further, as Examples 2-1 to 2-4, MOSFETs according to the second embodiment were manufactured. In all of Examples 2-1 to 2-4, the thickness of the carrier supply layer, which is an AlGaN layer, is 25 nm, and the thickness of the carrier travel layer, which is a u-GaN layer, is 25 nm. As for the length, Example 2-1 was about 110 nm, Examples 2-2 and 2-3 were about 150 nm, and Example 2-4 was about 180 nm. On the other hand, as Comparative Examples 2-1 to 2-15, the depth of the recess portion was set to 210 to 460 nm. Otherwise, MOSFETs similar to Example 2-1 were manufactured.

  On the other hand, as the reference sample 1, the buffer layer to the carrier supply layer are stacked on the substrate in the same manner as in Example 1-1. After that, without forming the recess, the gate insulating film, and the gate electrode, the source electrode and the drain are formed. A sample in which only the electrode was formed on the carrier supply layer was manufactured. In the reference sample 1, the source-drain distance is the same as in Example 1-1. Further, as the reference sample 2, the buffer layer to the carrier supply layer are stacked on the substrate in the same manner as in Example 2-1, but after that, without forming the recess, the gate insulating film, and the gate electrode, the source electrode and the drain are formed. A sample in which only the electrode was formed on the carrier supply layer was manufactured. In the reference sample 2, the source-drain distance is the same as in Example 2-1.

  And the voltage was applied between the source-drain of MOSFET which concerns on each manufactured said Example, comparative example, and reference | standard sample, and the proof pressure of each MOSFET was measured.

  FIG. 5 is a diagram showing the relationship between the recess depth of the MOSFETs according to the example and the comparative example and the normalized breakdown voltage. In FIG. 5, black circles indicate Examples 1-1 and 1-2 having an n-GaN layer and Comparative Examples 1-1 to 1-16, and white squares are examples having an AlGaN / u-GaN layer structure. 2-1 to 2-3 and Comparative Examples 2-1 to 2-15 are shown. In FIG. 5, the normalized withstand voltage is normalized with respect to the measured value of the withstand voltage of the reference sample 1 for Examples 1-1 and 1-2 and Comparative Examples 1-1 to 1-16. In Examples 2-1 to 2-3 and Comparative Examples 2-1 to 2-15, the measured values of the breakdown voltage are values normalized by the measured values of the breakdown voltage of the reference sample 2. Since these reference samples 1 and 2 do not have a recess, the measured value of the breakdown voltage indicates the breakdown voltage inherently provided in the stacked structure of the semiconductor layers on the substrate.

  As shown in FIG. 5, the normalized breakdown voltage of the MOSFET according to each example having a recess depth of 200 nm or less was close to 1, and had a breakdown voltage comparable to the original breakdown voltage of the stacked structure. On the other hand, the normalized breakdown voltage of the MOSFET according to each comparative example having a recess depth of 200 nm or more was 0.6 or less, which was greatly reduced from the original breakdown voltage.

  Next, MOSFETs according to the first embodiment were manufactured as Examples 3-1 to 3-3 of the present invention. In all of Examples 3-1 to 3-3, the thickness of the carrier supply layer, which is an n-GaN layer, was 50 nm, but the depths of the recess portions were about 113 nm, about 150 nm, and about 170 nm, respectively. did. On the other hand, as Comparative Examples 3-1 to 3-8, the depth of the recess portion was set to 210 to 470 nm. Otherwise, MOSFETs similar to Example 3-1 were manufactured. And on-resistance was measured about MOSFET which concerns on each Example and a comparative example. FIG. 6 is a diagram showing the relationship between the recess depth of the MOSFET and the normalized on-resistance according to the example and the comparative example. In FIG. 6, the normalized on-resistance is a value obtained by normalizing the measured value of on-resistance with the measured value of on-resistance in Example 3-1. Further, the solid line in FIG. 6 is an approximate straight line by the least square method. As shown in FIG. 6, it is confirmed that the recess depth and the normalized on-resistance are substantially proportional, but if the recess depth is about 200 nm, the normalized on-resistance can be lowered to about 1.5 or less. .

  In the first embodiment, GaN is used as the nitride compound semiconductor. However, the present invention can also be applied to a field effect transistor using other nitride compound semiconductors such as InGaN and AlN. In the second embodiment, GaN is used as the carrier transit layer and AlGaN is used as the carrier supply layer. However, as long as the nitride compound semiconductors have different band gap energies as the carrier transit layer and the carrier supply layer, there is a particular limitation. Not done.

100, 200 MOSFET
101, 201 Substrate 102, 202 Buffer layer 103, 203a, 203b Carrier running layer 104a, 104b, 204a, 204b Carrier supply layer 105, 205 Recessed portion 106, 206 Source electrode 107, 207 Drain electrode 108, 208 Gate insulating film 109, 209 Gate electrode 210 Lower semiconductor layer D1, D2 Depth g Groove Ga, Gb Two-dimensional electron gas

Claims (3)

A field effect transistor made of a nitride compound semiconductor,
A lower semiconductor layer formed on the substrate;
An undoped carrier traveling layer formed on the lower semiconductor layer and separated by a recess formed to a depth reaching the inside of the lower semiconductor layer;
A carrier supply layer formed on each of the separated carrier running layers, and having a different band gap energy from each of the carrier running layers;
A source electrode and a drain electrode formed on each of the carrier supply layers with the recess portion interposed therebetween;
A gate insulating film formed on the carrier supply layer so as to cover the surface of the lower semiconductor layer in the recess portion;
A gate electrode formed on the gate insulating film in the recess,
With
The lower semiconductor layer has a p-type conductivity,
The lower semiconductor layer and the carrier running layer are made of GaN, the carrier supply layer is made of AlGaN,
The depth of the recess portion from the upper surface of the carrier supply layer is greater than the total thickness of the carrier supply layer and the carrier travel layer, and is 200 nm or less. The field effect transistor according to claim 1 , wherein a depth of the recess portion from an upper surface of the carrier supply layer is larger than 110 nm . Field effect transistor according to claim 1 or 2, characterized in that said recessed portion and is formed by etching.

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