TWI748225B - Enhancement mode hemt device - Google Patents

Enhancement mode hemt device Download PDF

Info

Publication number
TWI748225B
TWI748225B TW108128739A TW108128739A TWI748225B TW I748225 B TWI748225 B TW I748225B TW 108128739 A TW108128739 A TW 108128739A TW 108128739 A TW108128739 A TW 108128739A TW I748225 B TWI748225 B TW I748225B
Authority
TW
Taiwan
Prior art keywords
layer
gallium nitride
electron mobility
mobility transistor
type gallium
Prior art date
Application number
TW108128739A
Other languages
Chinese (zh)
Other versions
TW202107702A (en
Inventor
陳智偉
溫文瑩
Original Assignee
新唐科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新唐科技股份有限公司 filed Critical 新唐科技股份有限公司
Priority to TW108128739A priority Critical patent/TWI748225B/en
Priority to CN201911334570.3A priority patent/CN112397583B/en
Publication of TW202107702A publication Critical patent/TW202107702A/en
Application granted granted Critical
Publication of TWI748225B publication Critical patent/TWI748225B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Abstract

An enhancement mode HEMT device is provided, including a channel layer disposed on a substrate, a barrier layer, a p-type gallium nitride layer, a protection layer, a gate, a source and a drain. The barrier layer is disposed on the channel layer, the p-type gallium nitride layer is disposed on the barrier layer, and the protection layer is disposed on the p-type gallium nitride layer. The gate is disposed in the protection layer, and an upper surface of the gate protrudes from an upper surface of the protection layer. The source and the drain are disposed at two sides of the gate separately, and disposed in the channel layer, the barrier layer, the p-type gallium nitride layer and the protection layer. The upper surfaces of the source and the drain protrude from the upper surface of the protection layer.

Description

增強型高電子遷移率電晶體元件Enhanced High Electron Mobility Transistor Element

本發明是有關於一種高電子遷移率電晶體（HEMT），且特別是有關於一種增強型（E-mode）高電子遷移率電晶體元件。The present invention relates to a high electron mobility transistor (HEMT), and particularly relates to an enhanced (E-mode) high electron mobility transistor element.

近年來，以III-V族化合物半導體為基礎的HEMT元件因為其低阻值、高崩潰電壓以及快速開關切換頻率等特性，在高功率電子元件領域被廣泛地應用。一般來說，HEMT元件可分為空乏型或常開型電晶體元件（D-mode），以及增強型或常關型電晶體元件（E-mode）。增強型（E-mode）電晶體元件因為其提供的附加安全性以及其更易於由簡單、低成本的驅動電路來控制，因而在業界獲得相當大的關注，p-GaN增強型（E-mode）電晶體元件已成為目前電子元件領域主流。In recent years, HEMT components based on III-V compound semiconductors have been widely used in the field of high-power electronic components due to their low resistance, high breakdown voltage, and fast switching frequency. Generally speaking, HEMT components can be divided into depletion type or normally-on type transistor components (D-mode), and enhanced or normally-off type transistor components (E-mode). Enhanced (E-mode) transistor components have gained considerable attention in the industry because of the additional safety they provide and their easier control by simple, low-cost drive circuits. ) Transistor components have become the mainstream in the field of electronic components.

在習知的p-GaN增強型（E-mode）電晶體元件製程中，主要是將鎂（Mg）摻雜進入GaN本體使其轉換成P型半導體，藉由p-GaN來空乏通道（2DEG）。此製程技術目前面臨的一大關卡是交叉污染問題，在進行p-GaN蝕刻製程及熱製程中，可能會使鎂（Mg）散逸出來而導致產線汙染。因此，如何有效地防止p-GaN增強型（E-mode）電晶體元件製程中可能導致的鎂（Mg）汙染問題，為目前所需研究的重要方向。In the conventional p-GaN enhancement mode (E-mode) transistor device manufacturing process, magnesium (Mg) is doped into the GaN body to convert it into a P-type semiconductor, and p-GaN is used to deplete the channel (2DEG). ). A major obstacle facing this process technology is the problem of cross-contamination. During the p-GaN etching process and thermal process, magnesium (Mg) may escape and cause production line pollution. Therefore, how to effectively prevent the magnesium (Mg) pollution problem that may be caused in the manufacturing process of p-GaN enhancement mode (E-mode) transistor components is an important research direction currently needed.

本發明提供一種增強型高電子遷移率電晶體元件，包括配置於P型氮化鎵層上的保護層，可在此保護層上進行金屬連線、蝕刻製程及熱製程，而不會接觸到P型氮化鎵層，因此，可有效地防止鎂汙染問題。The present invention provides an enhanced high electron mobility transistor including a protective layer disposed on a P-type gallium nitride layer, and metal wiring, etching processes and thermal processes can be performed on the protective layer without contacting The P-type gallium nitride layer, therefore, can effectively prevent magnesium contamination problems.

本發明的增強型高電子遷移率電晶體元件包括配置於基板上的通道層、阻障層、P型氮化鎵層、保護層、閘極以及源極與汲極。阻障層配置於通道層上，P型氮化鎵層配置於阻障層上，保護層配置於P型氮化鎵層上。閘極配置於保護層中，閘極的上表面從保護層的上表面凸出。源極與汲極分別位於閘極的兩側，且配置於通道層、阻障層、P型氮化鎵層及保護層中，源極與汲極的上表面從保護層的上表面凸出。The enhanced high electron mobility transistor device of the present invention includes a channel layer, a barrier layer, a P-type gallium nitride layer, a protective layer, a gate electrode, a source electrode and a drain electrode arranged on a substrate. The barrier layer is configured on the channel layer, the P-type gallium nitride layer is configured on the barrier layer, and the protective layer is configured on the P-type gallium nitride layer. The gate is arranged in the protective layer, and the upper surface of the gate protrudes from the upper surface of the protective layer. The source electrode and the drain electrode are located on both sides of the gate electrode, and are arranged in the channel layer, the barrier layer, the P-type gallium nitride layer and the protective layer. The upper surface of the source electrode and the drain electrode protrude from the upper surface of the protective layer .

在本發明的一實施例中，增強型高電子遷移率電晶體元件更包括介電層，配置於閘極與保護層之間。In an embodiment of the present invention, the enhanced high electron mobility transistor further includes a dielectric layer disposed between the gate electrode and the protective layer.

在本發明的一實施例中，閘極下方的保護層的厚度為1 nm至10 nm。In an embodiment of the present invention, the thickness of the protective layer under the gate is 1 nm to 10 nm.

在本發明的一實施例中，P型氮化鎵層的厚度為至少40 nm。In an embodiment of the present invention, the thickness of the P-type gallium nitride layer is at least 40 nm.

在本發明的一實施例中，P型氮化鎵層的厚度為40 nm至80 nm。In an embodiment of the present invention, the thickness of the P-type gallium nitride layer is 40 nm to 80 nm.

在本發明的一實施例中，保護層的材料包括氮化鋁鎵（AlGaN）或氮化鋁銦鎵（InAlGaN）。In an embodiment of the present invention, the material of the protective layer includes aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (InAlGaN).

在本發明的一實施例中，保護層的材料包括AlX Ga1-X N，且X為0.05至0.3。In an embodiment of the present invention, the material of the protective layer includes Al X Ga 1-X N, and X is 0.05 to 0.3.

在本發明的一實施例中，P型氮化鎵層的摻質為鎂。In an embodiment of the present invention, the dopant of the P-type gallium nitride layer is magnesium.

在本發明的一實施例中，通道層的材料包括氮化鎵（GaN）。In an embodiment of the present invention, the material of the channel layer includes gallium nitride (GaN).

在本發明的一實施例中，阻障層的材料包括氮化鋁鎵（AlGaN）。In an embodiment of the present invention, the material of the barrier layer includes aluminum gallium nitride (AlGaN).

基於上述，本發明提供一種增強型高電子遷移率電晶體元件，包括配置於P型氮化鎵層上的保護層，可在此保護層上進行金屬連線、蝕刻製程及熱製程，而不會接觸到P型氮化鎵層，因此，可有效地防止鎂汙染問題，且可形成雙通道，使電流效率上升並保有增強型高電子遷移率電晶體元件的特性。Based on the above, the present invention provides an enhanced high electron mobility transistor including a protective layer disposed on a P-type gallium nitride layer, and metal wiring, etching processes and thermal processes can be performed on the protective layer. It will touch the P-type gallium nitride layer, therefore, it can effectively prevent the magnesium pollution problem, and can form a dual channel, so that the current efficiency is increased and the characteristics of the enhanced high electron mobility transistor are maintained.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

下文列舉實施例並配合所附圖式來進行詳細地說明，但所提供之實施例並非用以限制本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖。為了方便理解，下述說明中相同的元件將以相同之符號標示來說明。The following examples are listed in conjunction with the accompanying drawings for detailed description, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn in accordance with the original dimensions. To facilitate understanding, the same elements in the following description will be described with the same symbols.

圖1為依照本發明的第一實施例的一種增強型高電子遷移率電晶體元件的剖面示意圖。FIG. 1 is a schematic cross-sectional view of an enhanced high electron mobility transistor device according to a first embodiment of the present invention.

請參照圖1，本實施例的增強型高電子遷移率電晶體元件包括配置於基板（未繪示）上的通道層10、阻障層20、P型氮化鎵層30、保護層40、閘極50以及源極60與汲極70。基板的材料例如藍寶石、矽（Si）或碳化矽（SiC），但本發明並不以此為限。更詳細而言，阻障層20配置於通道層10上，P型氮化鎵層30配置於阻障層20上，保護層40配置於P型氮化鎵層30上。閘極50配置於保護層40中，閘極50的上表面從保護層40的上表面凸出。源極60與汲極70位於閘極50的兩側，且配置於通道層10、阻障層20、P型氮化鎵層30及保護層40中，源極60與汲極70的上表面從保護層40的上表面凸出。1, the enhanced high electron mobility transistor of this embodiment includes a channel layer 10, a barrier layer 20, a P-type gallium nitride layer 30, a protective layer 40, which are disposed on a substrate (not shown), The gate 50, the source 60 and the drain 70. The material of the substrate is, for example, sapphire, silicon (Si) or silicon carbide (SiC), but the invention is not limited to this. In more detail, the barrier layer 20 is configured on the channel layer 10, the P-type gallium nitride layer 30 is configured on the barrier layer 20, and the protective layer 40 is configured on the P-type gallium nitride layer 30. The gate electrode 50 is disposed in the protective layer 40, and the upper surface of the gate electrode 50 protrudes from the upper surface of the protective layer 40. The source 60 and the drain 70 are located on both sides of the gate 50, and are arranged in the channel layer 10, the barrier layer 20, the P-type gallium nitride layer 30, and the protective layer 40. The upper surfaces of the source 60 and the drain 70 It protrudes from the upper surface of the protective layer 40.

請參照圖1，通道層10的材料可包括氮化鎵（GaN），阻障層20的材料可包括氮化鋁鎵（AlGaN），但本發明並不以此為限。P型氮化鎵層30的材料例如是摻雜有摻質（例如鎂）的氮化鎵。保護層40的材料可包括氮化鋁鎵（AlGaN）或氮化鋁銦鎵（InAlGaN）。如此一來，除了在通道層10及阻障層20的介面形成主要通道之外，更可在P型氮化鎵層30及保護層40的介面形成次要通道，雙通道可使電流效率上升。此外，透過P型氮化鎵層30及保護層40介面，更可藉由p-n阻障防止漏電流。1, the material of the channel layer 10 may include gallium nitride (GaN), and the material of the barrier layer 20 may include aluminum gallium nitride (AlGaN), but the present invention is not limited thereto. The material of the P-type gallium nitride layer 30 is, for example, gallium nitride doped with dopants (for example, magnesium). The material of the protective layer 40 may include aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (InAlGaN). In this way, in addition to forming the main channel at the interface of the channel layer 10 and the barrier layer 20, a secondary channel can be formed at the interface of the P-type gallium nitride layer 30 and the protective layer 40. The dual channel can increase the current efficiency. . In addition, through the interface of the P-type gallium nitride layer 30 and the protective layer 40, the leakage current can be prevented by the p-n barrier.

請參照圖1，閘極50下方的保護層40的厚度例如是1 nm至10 nm，使此主動區的主要通道和次要通道一併被空乏，在非主動區則仍能保持主要通道和次要通道導通，以保持增強型高電子遷移率電晶體元件的特性。P型氮化鎵層30的厚度例如是至少40 nm，較佳例如是40 nm至80 nm。當P型氮化鎵層30的厚度在此範圍內時，可保持增強型高電子遷移率電晶體元件的特性。保護層40的材料例如是AlX Ga1-X N，且X例如是0.05至0.3。當X的數值在此範圍內時，可保持增強型高電子遷移率電晶體元件的特性。Please refer to FIG. 1, the thickness of the protective layer 40 under the gate 50 is, for example, 1 nm to 10 nm, so that the main channel and the secondary channel in the active area are all depleted, while the main channel and the secondary channel can still be maintained in the non-active area. The secondary channel is turned on to maintain the characteristics of the enhanced high electron mobility transistor element. The thickness of the P-type gallium nitride layer 30 is, for example, at least 40 nm, preferably, for example, 40 nm to 80 nm. When the thickness of the P-type gallium nitride layer 30 is within this range, the characteristics of the enhanced high electron mobility transistor can be maintained. The material of the protective layer 40 is, for example, Al X Ga 1-X N, and X is, for example, 0.05 to 0.3. When the value of X is within this range, the characteristics of the enhanced high electron mobility transistor can be maintained.

圖1的增強型高電子遷移率電晶體元件之製造方法可包括以下步驟。首先，透過磊晶成長在基板上形成通道層10、阻障層20、P型氮化鎵層30及保護層40。之後，利用蝕刻製程選擇性地移除主動區部分的保護層40，再進行閘極50的金屬沉積，並形成源極60與汲極70。The manufacturing method of the enhanced high electron mobility transistor device of FIG. 1 may include the following steps. First, the channel layer 10, the barrier layer 20, the P-type gallium nitride layer 30, and the protective layer 40 are formed on the substrate through epitaxial growth. Afterwards, an etching process is used to selectively remove the protective layer 40 in the active region, and then metal deposition of the gate electrode 50 is performed, and the source electrode 60 and the drain electrode 70 are formed.

圖2為依照本發明的第二實施例的一種增強型高電子遷移率電晶體元件的剖面示意圖。圖2所示的第二實施例相似於圖1所示的第一實施例，故相同元件以相同標號表示且在此不予贅述。2 is a schematic cross-sectional view of an enhanced high electron mobility transistor device according to a second embodiment of the present invention. The second embodiment shown in FIG. 2 is similar to the first embodiment shown in FIG.

請參照圖2，本實施例與上述第一實施例不同之處在於，本實施例的增強型高電子遷移率電晶體元件，更包括配置於閘極50與保護層40之間的介電層80。透過在閘極50與保護層40之間配置介電層80，可進一步調整裝置的臨界電壓(Vth)及Ron，更可降低漏電流。Referring to FIG. 2, the difference between this embodiment and the above-mentioned first embodiment is that the enhanced high electron mobility transistor of this embodiment further includes a dielectric layer disposed between the gate electrode 50 and the protective layer 40 80. By disposing the dielectric layer 80 between the gate electrode 50 and the protective layer 40, the threshold voltage (Vth) and Ron of the device can be further adjusted, and the leakage current can be reduced.

綜上所述，本發明提供一種增強型高電子遷移率電晶體元件，包括配置於P型氮化鎵層上的保護層，可在此保護層上進行金屬連線、蝕刻製程及熱製程，而不會接觸到P型氮化鎵層，因此，可有效地防止鎂汙染問題，無須在蝕刻製程後進行機台維護或設立獨立專屬機台來防止汙染，故可降低成本且有利於產出。同時，可形成雙通道，使電流效率上升並保有增強型高電子遷移率電晶體元件的特性，更可藉由P型氮化鎵層與保護層介面的p-n阻障防止漏電流。In summary, the present invention provides an enhanced high electron mobility transistor including a protective layer disposed on a P-type gallium nitride layer, and metal connections, etching processes, and thermal processes can be performed on the protective layer. It does not touch the P-type gallium nitride layer, so it can effectively prevent magnesium pollution. There is no need to maintain the machine after the etching process or set up an independent dedicated machine to prevent pollution, so it can reduce costs and is beneficial to output . At the same time, a dual channel can be formed to increase the current efficiency and maintain the characteristics of an enhanced high electron mobility transistor element. It can also prevent leakage current through the p-n barrier at the interface between the P-type gallium nitride layer and the protective layer.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

10:通道層 20:阻障層 30:P型氮化鎵層 40:保護層 50:閘極 60:源極 70:汲極 80:介電層10: Channel layer 20: Barrier layer 30: P-type gallium nitride layer 40: protective layer 50: gate 60: Source 70: Dip pole 80: Dielectric layer

圖1為依照本發明的第一實施例的一種增強型高電子遷移率電晶體元件的剖面示意圖。 圖2為依照本發明的第二實施例的一種增強型高電子遷移率電晶體元件的剖面示意圖。FIG. 1 is a schematic cross-sectional view of an enhanced high electron mobility transistor device according to a first embodiment of the present invention. 2 is a schematic cross-sectional view of an enhanced high electron mobility transistor device according to a second embodiment of the present invention.

10:通道層 10: Channel layer

20:阻障層 20: Barrier layer

30:P型氮化鎵層 30: P-type gallium nitride layer

40:保護層 40: protective layer

50:閘極 50: gate

60:源極 60: Source

70:汲極 70: Dip pole

Claims (10)

一種增強型高電子遷移率電晶體元件，包括：通道層，配置於基板上；阻障層，配置於所述通道層上，其中所述通道層及所述阻障層的介面具有主要通道；P型氮化鎵層，配置於所述阻障層上；保護層，配置於所述P型氮化鎵層上，其中所述P型氮化鎵層及所述保護層的介面具有次要通道；閘極，配置於所述保護層中，所述閘極的上表面從所述保護層的上表面凸出；以及源極與汲極，分別位於所述閘極的兩側，且配置於所述通道層、所述阻障層、所述P型氮化鎵層及所述保護層中，所述源極與所述汲極的上表面從所述保護層的上表面凸出。 An enhanced high electron mobility transistor element, comprising: a channel layer arranged on a substrate; a barrier layer arranged on the channel layer, wherein the interface between the channel layer and the barrier layer has a main channel; A p-type gallium nitride layer is configured on the barrier layer; a protection layer is configured on the p-type gallium nitride layer, wherein the interface between the p-type gallium nitride layer and the protection layer has a secondary Channel; gate, arranged in the protective layer, the upper surface of the gate protruding from the upper surface of the protective layer; and source and drain, respectively located on both sides of the gate, and are configured In the channel layer, the barrier layer, the P-type gallium nitride layer, and the protective layer, the upper surfaces of the source electrode and the drain electrode protrude from the upper surface of the protective layer. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，更包括介電層，配置於所述閘極與所述保護層之間。 The enhanced high-electron mobility transistor device described in the first item of the scope of the patent application further includes a dielectric layer disposed between the gate electrode and the protective layer. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中所述閘極下方的所述保護層的厚度為1nm至10nm。 In the enhanced high electron mobility transistor device described in the first item of the scope of patent application, the thickness of the protective layer under the gate electrode is 1 nm to 10 nm. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中所述P型氮化鎵層的厚度為至少40nm。 In the enhanced high electron mobility transistor device described in the first item of the scope of patent application, the thickness of the P-type gallium nitride layer is at least 40 nm. 如申請專利範圍第4項所述的增強型高電子遷移率電晶體元件，其中所述P型氮化鎵層的厚度為40nm至80nm。 In the enhanced high electron mobility transistor device described in item 4 of the scope of patent application, the thickness of the P-type gallium nitride layer is 40 nm to 80 nm. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中所述保護層的材料包括氮化鋁鎵(AlGaN)或氮化鋁銦鎵(InAlGaN)。 In the enhanced high electron mobility transistor element described in the first item of the scope of patent application, the material of the protective layer includes aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (InAlGaN). 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中所述保護層的材料包括AlXGa1-XN，且X為0.05至0.3。 In the enhanced high electron mobility transistor device described in the first item of the scope of patent application, the material of the protective layer includes Al X Ga 1-X N, and X is 0.05 to 0.3. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中所述P型氮化鎵層的摻質為鎂。 In the enhanced high electron mobility transistor device described in the first item of the scope of patent application, the dopant of the P-type gallium nitride layer is magnesium. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中所述通道層的材料包括氮化鎵(GaN)。 In the enhanced high electron mobility transistor device described in the first item of the scope of patent application, the material of the channel layer includes gallium nitride (GaN). 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中所述阻障層的材料包括氮化鋁鎵(AlGaN)。 In the enhanced high electron mobility transistor device described in the first item of the scope of patent application, the material of the barrier layer includes aluminum gallium nitride (AlGaN).
TW108128739A 2019-08-13 2019-08-13 Enhancement mode hemt device TWI748225B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW108128739A TWI748225B (en) 2019-08-13 2019-08-13 Enhancement mode hemt device
CN201911334570.3A CN112397583B (en) 2019-08-13 2019-12-23 Enhanced high electron mobility transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108128739A TWI748225B (en) 2019-08-13 2019-08-13 Enhancement mode hemt device

Publications (2)

Publication Number Publication Date
TW202107702A TW202107702A (en) 2021-02-16
TWI748225B true TWI748225B (en) 2021-12-01

Family

ID=74603753

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108128739A TWI748225B (en) 2019-08-13 2019-08-13 Enhancement mode hemt device

Country Status (2)

Country Link
CN (1) CN112397583B (en)
TW (1) TWI748225B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI661554B (en) * 2017-12-28 2019-06-01 新唐科技股份有限公司 Enhancement mode hemt device and mehtod of forming the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7985986B2 (en) * 2008-07-31 2011-07-26 Cree, Inc. Normally-off semiconductor devices
KR102065115B1 (en) * 2010-11-05 2020-01-13 삼성전자주식회사 High Electron Mobility Transistor having E-mode and method of manufacturing the same
US9608085B2 (en) * 2012-10-01 2017-03-28 Cree, Inc. Predisposed high electron mobility transistor
CN107735863A (en) * 2015-07-01 2018-02-23 香港科技大学 Enhanced double channel HEMT

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI661554B (en) * 2017-12-28 2019-06-01 新唐科技股份有限公司 Enhancement mode hemt device and mehtod of forming the same

Also Published As

Publication number Publication date
CN112397583A (en) 2021-02-23
CN112397583B (en) 2023-07-28
TW202107702A (en) 2021-02-16

Similar Documents

Publication Publication Date Title
US20210320199A1 (en) Enhancement-mode semiconductor device and preparation method therefor
JP5785153B2 (en) Compensated gate MISFET and manufacturing method thereof
JP5323527B2 (en) Manufacturing method of GaN-based field effect transistor
JP6660975B2 (en) High electron mobility transistor
KR101092467B1 (en) Enhancement normally off nitride semiconductor device and manufacturing method thereof
TWI420664B (en) Enhancement-mode high-electron-mobility transistor and the manufacturing method thereof
US10199476B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2012231003A (en) Semiconductor device
US20150263155A1 (en) Semiconductor device
JP2010166027A (en) GaN-BASED FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
JP2010225979A (en) GaN-BASED FIELD-EFFECT TRANSISTOR
JP2009231458A (en) Field-effect transistor
JP2011210785A (en) Field-effect transistor and method for manufacturing the same
JP2011129607A (en) Gan-based mos field-effect transistor
JP2007250727A (en) Field effect transistor
JP2009239144A (en) Semiconductor device made of gallium-nitride compound semiconductor and manufacturing method thereof
US20220416070A1 (en) High electron mobility transistor and method of manufacturing the same
TWM508782U (en) Semiconductor device
JP2016181570A (en) Semiconductor device and manufacturing method of the same
TWI748225B (en) Enhancement mode hemt device
KR20190112523A (en) Heterostructure Field Effect Transistor and production method thereof
EP3772112A1 (en) High electron mobility transistor
WO2017126428A1 (en) Semiconductor device, electronic part, electronic apparatus, and method for fabricating semiconductor device
US20210210627A1 (en) Enhancement mode mishemt with gan channel regrowth under a gate area
US9240474B2 (en) Enhanced GaN transistor and the forming method thereof