CN110085675A - A kind of HEMT enhancement device and preparation method thereof - Google Patents

A kind of HEMT enhancement device and preparation method thereof Download PDF

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CN110085675A
CN110085675A CN201910189819.XA CN201910189819A CN110085675A CN 110085675 A CN110085675 A CN 110085675A CN 201910189819 A CN201910189819 A CN 201910189819A CN 110085675 A CN110085675 A CN 110085675A
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junctions
hetero
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electrode
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马晓华
何云龙
郝跃
杨凌
王冲
郑雪峰
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Xidian University
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Xidian University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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Abstract

The present invention provides a kind of HEMT enhancement device and preparation method thereof, and the device includes the substrate layer set gradually, buffer layer, barrier layer, P-GaN cap layers, passivation layer, gate electrode, source electrode and drain electrode;The source electrode and drain electrode is respectively arranged in the active area on the barrier layer;Buffer layer and barrier layer between the source electrode and drain electrode form nano-channel;The P-GaN cap layers cover the nano-channel perpendicular to two sides of the substrate layer and the face parallel with the substrate layer between source electrode and drain electrode;The gate electrode covers the P-GaN cap layers face parallel with the substrate layer perpendicular to two sides of the substrate layer and the P-GaN cap layers;The passivation layer covers the region between the source electrode and gate electrode and between gate electrode and drain electrode.

Description

A kind of HEMT enhancement device and preparation method thereof
Technical field
The present invention relates to electronic technology field more particularly to a kind of HEMT (High Electron Mobility Transistor, high electron mobility transistor) enhancement device and preparation method thereof.
Background technique
It is big with its forbidden bandwidth using SiC and GaN as the third generation wide bandgap semiconductor of representative in recent years, breakdown electric field is high, Thermal conductivity is high, saturated electrons speed is big and the characteristics such as heterojunction boundary two-dimensional electron gas height, receives significant attention it.Its In, AlGaN/GaN hetero-junctions high electron mobility transistor (HEMT) has been displayed in terms of high-temperature device and HIGH-POWERED MICROWAVES device Advantageous advantage is gone out, has pursued device high-frequency, high pressure, high power and attracted numerous research.
In recent years, due to the driving of high-voltage switch gear and high speed circuit, GaN enhancement device becomes the another research heat of concern Point.After the completion of the growth of AlGaN/GaN hetero-junctions, heterojunction boundary there is a large amount of two-dimensional electron gas 2DEG (2 Dimensional Electron Gas), 2DEG could be exhausted when material is fabricated to after device adds minus gate voltage and press from both sides channel Disconnected, i.e. routine AlGaN/GaN HEMT is depletion device.But enhancement device is needed when high-voltage switch gear field is applied, it is ensured that Only plus positive grid voltage just has operating current, so the demand to enhancement type high electron mobility transistor is more and more urgent.With right The research of AlGaN/GaN hetero-junctions gradually deeply, developed at present methods, such as fluorine etc. of a variety of production enhancement devices from Daughter processing structure, recessed gate dielectric layer structure, nano-channel structure, P-GaN cap layer structure etc..Wherein due to P-GaN cap layers knot Structure threshold voltage stabilization is convenient for volume production, is one of the main stream approach of current commercial enhanced power device.But the structure is in reality There are still some problems in the application of border have it is to be solved, such as breakdown voltage less, threshold voltage it is smaller etc..
Summary of the invention
To solve technological deficiency of the existing technology and deficiency, the invention proposes a kind of HEMT enhancement device, Be characterized in that, including set gradually substrate layer, buffer layer, barrier layer, P-GaN cap layers, passivation layer, gate electrode, source electrode and Drain electrode;
The source electrode and drain electrode is respectively arranged in the active area on the barrier layer;
Buffer layer and barrier layer between the source electrode and drain electrode form nano-channel;
The P-GaN cap layers cover the nano-channel perpendicular to the substrate layer between source electrode and drain electrode Two sides and the face parallel with the substrate layer;
The gate electrode covers two sides and the P-GaN cap of the P-GaN cap layers perpendicular to the substrate layer The layer face parallel with the substrate layer;
The passivation layer covers the region between the source electrode and gate electrode and between gate electrode and drain electrode.
Optionally, the substrate layer is Si substrate;The buffer layer is intrinsic GaN;The barrier layer is AlGaN, described Barrier layer and the buffer layer form AlGaN/GaN hetero-junctions.
Optionally, the buffer layer thickness is 1-3 μm;The Al ratio of the barrier layer is 20~40%, with a thickness of 10- 30nm;The P-GaN with a thickness of 20~60nm, p-type doping concentration is 1 × 1017cm-3~1 × 1019cm-3;The dielectric layer With a thickness of 60~120nm.
Optionally, the width of the nano-channel is 100~500nm, depth is 20~60nm.
Further, the present invention also provides a kind of production methods of HEMT enhancement device, comprising:
On substrate layer substrate, hetero-junctions is grown;
Source electrode and drain electrode is made respectively at the hetero-junctions both ends;
The hetero-junctions between the source electrode and drain electrode is etched, nano-channel is formed;In the source electrode and drain electrode Between, make P-GaN cap layers, the P-GaN cap layers cover the hetero-junctions perpendicular to the side of the substrate layer and described Hetero-junctions top surface;
Gate electrode is made in the P-GaN cap layers;
Passivation layer is made between the source electrode and the gate electrode and between gate electrode and the drain electrode;
Metal interconnection is made on the gate electrode.
Optionally, it is described on substrate layer substrate, growth hetero-junctions the step of specifically include:
On the substrate layer, grown buffer layer;
Barrier layer is grown on the buffer layer, forms two-dimentional electricity in the contact position of the buffer layer and the barrier layer Sub- gas obtains the hetero-junctions.
Optionally, the step of hetero-junctions between the etching source electrode and drain electrode, formation nano-channel is specific Include:
Mask is carried out to the hetero-junctions using electron beam lithography machine;
The hetero-junctions is performed etching in the plasma using inductively coupled plasma etching machine, is received described in formation Rice channel.
Optionally, described between the source electrode and drain electrode, make P-GaN cap layers the step of specifically include:
One layer of GaN layer for mixing Mg is grown on the hetero-junctions;
Using RTP500 rapid thermal anneler, in 900 DEG C of N220 minutes thermal annealings are carried out in atmosphere to activate doping Mg, obtain P-GaN layers.
It is optionally, described after the step of making gate electrode in the P-GaN cap layers, further includes:
P-GaN cap layers on all hetero-junctions other than etching removal gate region.
Optionally, described to include: the step of making metal interconnection on the gate electrode
Using sense coupling machine in CF4With the etch rate etching removal grid of setting in plasma The passivation layer in region forms interconnection aperture;
Ohmiker-50 electron beam evaporation platform is used in grid opening area to set evaporation rate to making mask Substrate carries out lead electrode evaporation of metal;
It is removed after the completion of lead electrode evaporation of metal, obtains complete lead electrode.
From the above it can be seen that HEMT device provided in an embodiment of the present invention is using three-dimensional PN nano junction channel junction Structure, above nano-channel and two sides form PN junction, and nano-channel is not only regulated and controled by top PN junction, while the PN by two sides Knot regulation, threshold voltage is higher, and stability is good.Meanwhile HEMT device provided in an embodiment of the present invention, gate electrode pass through three-dimensional PN junction regulation, reverse-biased blocking ability is stronger, and gate leakage current can be effectively reduced, and improves the breakdown voltage of device.In addition, The production method of HEMT device provided in an embodiment of the present invention, the either use of P-GaN cap layer structure or nano-channel knot The use of structure all has extraordinary process repeatability and temperature stability, helps to improve the job stability of device.
Through the following detailed description with reference to the accompanying drawings, other aspects of the invention and feature become obvious.But it should know Road, which is only the purpose design explained, not as the restriction of the scope of the present invention, this is because it should refer to Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale attached drawing, they merely attempt to concept Ground illustrates structure and process described herein.
Detailed description of the invention
Below in conjunction with attached drawing, specific embodiments of the present invention will be described in detail.
Fig. 1 is HEMT enhancement device chief component schematic diagram provided in an embodiment of the present invention;
Fig. 2 is HEMT enhancement device production method flow diagram provided in an embodiment of the present invention;
Fig. 3 A-3E is HEMT enhancement device gate electrode part provided in an embodiment of the present invention manufacturing process schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Present invention firstly provides a kind of HEMT enhancement device, structure is as shown in Figure 1, include the substrate layer set gradually 101, buffer layer 102, barrier layer 103, P-GaN cap layers 104, passivation layer, gate electrode 105, source electrode 106 and drain electrode 107;
The source electrode 106 and drain electrode 107 are respectively arranged in the active area on the barrier layer 103;
Buffer layer 102 and barrier layer 103 between the source electrode 106 and drain electrode 107 form nano-channel;
The P-GaN cap layers 104 cover the nano-channel perpendicular to institute between source electrode 106 and drain electrode 107 State two sides and the face parallel with the substrate layer 101 of substrate layer 101;
The gate electrode 106 covers the P-GaN cap layers 104 perpendicular to two sides of the substrate layer 101 and institute State the face parallel with the substrate layer 101 of P-GaN cap layers 106;
The passivation layer 105 covers between the source electrode 106 and gate electrode 105 and gate electrode 105 and drain electrode Region between 107.
HEMT device provided in an embodiment of the present invention forms receiving for three-dimensional rectangular shape between source electrode and drain electrode Rice channel structure, and P-GaN layers are formed on hetero-junctions surface, gate electrode is set on P-GaN layers.In this way, P-GaN layers not There is only, also in hetero-junctions two sides, being completely depleted in zero grid voltage lower channel electronics above hetero-junctions, enhancement device is formed.By It is modulated in the PN junction that the channel of the device is not only modulated by top P-GaN layers also by two sides, threshold voltage is higher.Meanwhile The reverse-biased of PN junction can effectively reduce gate leakage current, improve breakdown voltage.Nano-channel structure in the embodiment of the present invention Channel width should be rationally designed, so that device side PN junction be made to play control ability, threshold voltage is improved and improves breakdown potential simultaneously Pressure.
The substrate layer is Si substrate;The buffer layer is intrinsic GaN;The barrier layer be AlGaN, the barrier layer with The buffer layer forms AlGaN/GaN hetero-junctions.
In some embodiment of the invention, the buffer layer thickness is 1-3 μm;The Al ratio of the barrier layer be 20~ 40%, with a thickness of 10-30nm;The P-GaN with a thickness of 20~60nm, p-type doping concentration is 1 × 1017cm-3~1 × 1019cm-3;The thickness of dielectric layers is 60~120nm.
In some embodiment of the invention, the width of the nano-channel is 100~500nm, depth is 20~60nm.? Under conditions of this width and depth, gate leakage current can be effectively reduced, improves breakdown voltage.
Meanwhile the embodiment of the present invention also provides a kind of production method of HEMT enhancement device, as shown in Figure 2, comprising:
Step 101: on substrate layer substrate, growing hetero-junctions;Referring to Fig. 3 A, on substrate base, grown buffer layer 301 With barrier layer 302, GaN/ALGaN hetero-junctions is formed;
Step 102: making source electrode and drain electrode respectively at the hetero-junctions both ends;
Step 103: etching the hetero-junctions between the source electrode and drain electrode, form nano-channel, as shown in Figure 3B, carve Lose barrier layer 302 and portion of buffer layer 301;Between the source electrode and drain electrode, as shown in Figure 3 C, P-GaN cap layers are made 303, the P-GaN cap layers 303 cover the hetero-junctions perpendicular to the side and the hetero-junctions top surface of the substrate layer;
Step 104: gate electrode 304 is made in the P-GaN cap layers, as shown in Figure 3D;
Step 105: being made between the source electrode and the gate electrode and between gate electrode and the drain electrode blunt Change layer 305, as shown in figure E;Passivation layer can cover or not covering grid electrode;
Step 106: making metal interconnection on the gate electrode.
In some embodiment of the invention, it is described on substrate layer substrate, growth hetero-junctions the step of specifically include:
On the substrate layer, grown buffer layer;
Barrier layer is grown on the buffer layer, forms two-dimentional electricity in the contact position of the buffer layer and the barrier layer Sub- gas obtains the hetero-junctions.
In some embodiment of the invention, the hetero-junctions between the etching source electrode and drain electrode, formation nanometer The step of channel, specifically includes:
Mask is carried out to the hetero-junctions using electron beam lithography machine;
The hetero-junctions is performed etching in the plasma using inductively coupled plasma etching machine, is received described in formation Rice channel.
In some embodiment of the invention, described between the source electrode and drain electrode, make P-GaN cap layers the step of It specifically includes:
One layer of GaN layer for mixing Mg is grown on the hetero-junctions;
Using RTP500 rapid thermal anneler, in 900 DEG C of N220 minutes thermal annealings are carried out in atmosphere to activate doping Mg, obtain P-GaN layers.
In some embodiment of the invention, described after the step of making gate electrode in the P-GaN cap layers, also wrap It includes:
P-GaN cap layers on all hetero-junctions other than etching removal gate region.
In some embodiment of the invention, described to include: the step of making metal interconnection on the gate electrode
Using sense coupling machine in CF4With the etch rate etching removal grid of setting in plasma The passivation layer in region forms interconnection aperture;
Ohmiker-50 electron beam evaporation platform is used in grid opening area to set evaporation rate to making mask Substrate carries out lead electrode evaporation of metal;
It is removed after the completion of lead electrode evaporation of metal, obtains complete lead electrode.
Three kinds of specific embodiments of the present invention are given below:
Embodiment one: the AlGaN/GaN HEMT enhancement device that production PN junction channel width is 100nm.
Step 11: utilizing MOCVD technique, epitaxial growth hetero-junctions.Specifically comprise the following steps:
Step 111: on Si substrate base, growth thickness is 1 μm of intrinsic GaN layer;
Step 112: the AlGaN potential barrier of 10nm thickness is grown in intrinsic GaN layer, wherein Al component is 20%, intrinsic The contact position of GaN layer and AlGaN potential barrier forms two-dimensional electron gas, obtains AlGaN/GaN hetero-junctions;
Step 12: source-drain electrode production specifically comprises the following steps:
Step 21: use Ohmiker-50 electron beam evaporation platform to carry out source-drain electrode production with the evaporation rate of 0.1nm/s, Source-drain electrode metal successively selects Ti, Al, Ni, Au, and wherein Ti is with a thickness of 20nm, Al with a thickness of 120nm, Ni with a thickness of 45nm, Au is with a thickness of 55nm;Laggard row metal removing is completed in the evaporation of source-drain electrode metal ohmic contact;
Step 122: RTP500 rapid thermal anneler is used, in 870 DEG C of N2The rapid thermal annealing of 30s is carried out in atmosphere, Alloy is carried out to metal ohmic contact, completes the production in source, drain electrode.
Step 13:PN ties channel production.
Step 131: mask being carried out using electron beam lithography machine, photoetching channel width is 100nm;
Step 132: using inductively coupled plasma etching machine in Cl2In plasma to AlGaN/GaN hetero-junctions into Row etching, forms nano-channel, etching depth 20nm;
Step 133: utilizing MBE technique, one layer of GaN layer for mixing the 10nm of Mg is grown on AlGaN/GaN hetero-junctions.
Step 134: RTP500 rapid thermal anneler is used, in 900 DEG C of N2The thermal annealing carried out in atmosphere 20 minutes comes The Mg for activating doping, obtaining p-type doping concentration is 1 × 1017cm-3P-GaN layer.
Step 14: production gate electrode and passivation protection.Specifically comprise the following steps:
Step 141: Ohmiker-50 electron beam evaporation platform being used to carry out the steaming of grid metal with the evaporation rate of 0.1nm/s Hair, so that it is covered on the two side walls of the top of hetero-junctions and hetero-junctions, grid metal successively selects Ni/Au, wherein Ni with a thickness of With a thickness of 200nm, laggard row metal removing is completed in evaporation by 20nm, Au, obtains complete gate electrode.
Step 142: using inductively coupled plasma etching machine in Cl2In plasma to the p-GaN layer other than grid into Row etching, etch mask are gate electrode metal exposure mask, etching depth 10nm;
Step 143: using PECVD deposition apparatus with NH3For the source N, SiH4Source is the source Si, in top layer's AlGaN potential barrier Deposition thickness is the SiN passivation layer of 60nm, and deposition temperature is 300 DEG C.
Step 15: interconnection metal production.Specifically comprise the following steps:
Step 151: using sense coupling machine in CF4With the etch rate of 0.5nm/s in plasma The SiN layer of etching removal area of grid, forms interconnection aperture;
Step 152: using Ohmiker-50 electron beam evaporation platform with the evaporation rate pair of 0.3nm/s in grid opening area The substrate for making mask carries out lead electrode evaporation of metal, and metal selects Ti with a thickness of 20nm, and Au is with a thickness of 200nm;Finally It is removed after the completion of lead electrode evaporation of metal, obtains complete lead electrode.
Embodiment two: the AlGaN/GaN HEMT enhancement device that production PN junction channel width is 300nm.
Step 21: utilizing MOCVD technique, epitaxial growth hetero-junctions.
Step 211: on Si substrate base, growth thickness is 2 μm of intrinsic GaN layer;
Step 212: the AlGaN potential barrier of 20nm thickness is grown in intrinsic GaN layer, wherein Al component is 30%, intrinsic The contact position of GaN layer and AlGaN potential barrier forms two-dimensional electron gas, obtains AlGaN/GaN hetero-junctions;
Step 22: source-drain electrode production specifically comprises the following steps:
Step 221: Ohmiker-50 electron beam evaporation platform being used to carry out source-drain electrode system with the evaporation rate of 0.1nm/s Make, source and drain metal successively selects Ti, Al, Ni, Au, and wherein Ti is with a thickness of 20nm, and Al is with a thickness of 120nm, and Ni is with a thickness of 45nm, Au With a thickness of 55nm;Laggard row metal removing is completed in the evaporation of source and drain metal ohmic contact;
Step 222: RTP500 rapid thermal anneler is used, in 870 DEG C of N2The rapid thermal annealing of 30s is carried out in atmosphere, Alloy is carried out to metal ohmic contact, completes the production in source, drain electrode.
Step 33:PN ties channel production.
Step 331: mask being carried out using electron beam lithography machine, photoetching channel width is 300nm;
Step 332: using inductively coupled plasma etching machine in Cl2In plasma to AlGaN/GaN hetero-junctions into Row etching, forms nano-channel, etching depth 40nm;
Step 333: utilizing MBE technique, one layer of GaN layer for mixing the 20nm of Mg is grown on AlGaN/GaN hetero-junctions.
Step 334: RTP500 rapid thermal anneler is used, in 900 DEG C of N2The thermal annealing carried out in atmosphere 20 minutes comes The Mg for activating doping, obtaining p-type doping concentration is 1 × 1018cm-3P-GaN layer.
Step 34: production gate electrode and passivation protection.Specifically comprise the following steps:
Step 341: Ohmiker-50 electron beam evaporation platform being used to carry out the steaming of grid metal with the evaporation rate of 0.1nm/s Hair, so that it is covered on the two side walls of the top of hetero-junctions and hetero-junctions, grid metal successively selects Ni/Au, wherein Ni with a thickness of With a thickness of 200nm, laggard row metal removing is completed in evaporation by 20nm, Au, obtains complete gate electrode.
Step 342: using inductively coupled plasma etching machine in Cl2In plasma to the P-GaN layer other than grid into Row etching, etch mask are gate electrode metal exposure mask, etching depth 20nm;
Step 343: using PECVD deposition apparatus with NH3For the source N, SiH4Source is the source Si, in top layer's AlGaN potential barrier Deposition thickness is the SiN passivation layer of 90nm, and deposition temperature is 300 DEG C.
Step 35: interconnection metal production.Specifically comprise the following steps:
Step 351: using sense coupling machine in CF4With the etch rate of 0.5nm/s in plasma The SiN layer of etching removal area of grid, forms interconnection aperture;
Step 352: using Ohmiker-50 electron beam evaporation platform with the evaporation rate pair of 0.3nm/s in grid opening area The substrate for making mask carries out lead electrode evaporation of metal, and metal selects Ti with a thickness of 20nm, and Au is with a thickness of 200nm;Finally It is removed after the completion of lead electrode evaporation of metal, obtains complete lead electrode.
Embodiment three: the AlGaN/GaN HEMT enhancement device that production PN junction channel width is 500nm.
Step 31: utilizing MOCVD technique, epitaxial growth hetero-junctions.Specifically comprise the following steps:
Step 311: on Si substrate base, growth thickness is 3 μm of intrinsic GaN layer;
Step 312: the AlGaN potential barrier of 30nm thickness is grown in intrinsic GaN layer, wherein Al component is 40%, intrinsic The contact position of GaN layer and AlGaN potential barrier forms two-dimensional electron gas, obtains AlGaN/GaN hetero-junctions;
Step 32: source-drain electrode production.Specifically comprise the following steps:
Step 321: Ohmiker-50 electron beam evaporation platform being used to carry out source-drain electrode system with the evaporation rate of 0.1nm/s Make, source and drain metal successively selects Ti/Al/Ni/Au, and wherein Ti is with a thickness of 20nm, and Al is with a thickness of 120nm, and Ni is with a thickness of 45nm, Au With a thickness of 55nm;Laggard row metal removing is completed in the evaporation of source and drain metal ohmic contact;
Step 322: RTP500 rapid thermal anneler is used, in 870 DEG C of N2The rapid thermal annealing of 30s is carried out in atmosphere, Alloy is carried out to metal ohmic contact, completes the production in source, drain electrode.
Step 33: knot channel production.Specifically comprise the following steps:
Step 331: mask being carried out using electron beam lithography machine, photoetching channel width is 500nm;
Step 332: using inductively coupled plasma etching machine in Cl2In plasma to AlGaN/GaN hetero-junctions into Row etching, forms nano-channel, etching depth 60nm;
Step 333: utilizing MBE technique, one layer of GaN layer for mixing the 30nm of Mg is grown on AlGaN/GaN hetero-junctions.
Step 334: RTP500 rapid thermal anneler is used, in 900 DEG C of N2The thermal annealing carried out in atmosphere 20 minutes comes The Mg for activating doping, obtaining p-type doping concentration is 1 × 1019cm-3P-GaN layer.
Step 34: production gate electrode and passivation protection specifically comprise the following steps:
Step 341: Ohmiker-50 electron beam evaporation platform being used to carry out the steaming of grid metal with the evaporation rate of 0.1nm/s Hair, so that it is covered on the two side walls of the top of hetero-junctions and hetero-junctions, grid metal successively selects Ni/Au, wherein Ni with a thickness of With a thickness of 200nm, laggard row metal removing is completed in evaporation by 20nm, Au, obtains complete gate electrode.
Step 342: using inductively coupled plasma etching machine in Cl2 plasma to the p-GaN layer other than grid into Row etching, etch mask are gate electrode metal exposure mask, etching depth 30nm;
Step 343: using PECVD deposition apparatus with NH3For the source N, SiH4Source is the source Si, in top layer's AlGaN potential barrier Deposition thickness is the SiN passivation layer of 120nm, and deposition temperature is 300 DEG C.
Step 35: interconnection metal production.Specifically comprise the following steps:
Step 351: using sense coupling machine in CF4With the etch rate of 0.5nm/s in plasma The SiN layer of etching removal area of grid, forms interconnection aperture;
Step 352: using Ohmiker-50 electron beam evaporation platform with the evaporation rate pair of 0.3nm/s in grid opening area The substrate for making mask carries out lead electrode evaporation of metal, and metal selects Ti with a thickness of 20nm, and Au is with a thickness of 200nm;Finally It is removed after the completion of lead electrode evaporation of metal, obtains complete lead electrode.
HEMT device provided in an embodiment of the present invention using three-dimensional PN nano junction channel structure, above nano-channel and Two sides form PN junction, and nano-channel is not only regulated and controled by top PN junction, while being regulated and controled by the PN junction of two sides, and threshold voltage is more Height, stability are good.Meanwhile HEMT device provided in an embodiment of the present invention, gate electrode pass through three-dimensional PN junction regulation, reverse-biased resistance Cutting capacity is stronger, and gate leakage current can be effectively reduced, and improves the breakdown voltage of device.In addition, the embodiment of the present invention provides HEMT device production method, either P-GaN cap layer structure use or nano-channel structure use, all have it is non- Often good process repeatability and temperature stability, helps to improve the job stability of device.
To sum up, used herein a specific example illustrates the principle and implementation of the invention, the above implementation The explanation of example is merely used to help understand method and its core concept of the invention;Meanwhile for the general technology people of this field Member, according to the thought of the present invention, there will be changes in the specific implementation manner and application range, to sum up, in this specification Appearance should not be construed as limiting the invention, and protection scope of the present invention should be subject to the attached claims.

Claims (10)

1. a kind of HEMT enhancement device, which is characterized in that including substrate layer, buffer layer, barrier layer, the P-GaN set gradually Cap layers, passivation layer, gate electrode, source electrode and drain electrode;
The source electrode and drain electrode is respectively arranged in the active area on the barrier layer;
Buffer layer and barrier layer between the source electrode and drain electrode form nano-channel;
The P-GaN cap layers cover the nano-channel perpendicular to the two of the substrate layer between source electrode and drain electrode A side and the face parallel with the substrate layer;
The gate electrode cover the P-GaN cap layers perpendicular to two sides of the substrate layer and the P-GaN cap layers with The parallel face of the substrate layer;
The passivation layer covers the region between the source electrode and gate electrode and between gate electrode and drain electrode.
2. HEMT enhancement device according to claim 1, which is characterized in that the substrate layer is Si substrate;It is described slow Rushing layer is intrinsic GaN;The barrier layer is AlGaN, and the barrier layer and the buffer layer form AlGaN/GaN hetero-junctions.
3. HEMT enhancement device according to claim 2, which is characterized in that the buffer layer thickness is 1-3 μm;It is described The Al ratio of barrier layer is 20~40%, with a thickness of 10-30nm;The P-GaN with a thickness of 20~60nm, p-type doping concentration It is 1 × 1017cm-3~1 × 1019cm-3;The thickness of dielectric layers is 60~120nm.
4. HEMT enhancement device according to claim 1, which is characterized in that the width of the nano-channel be 100~ 500nm, depth are 20~60nm.
5. a kind of production method of HEMT enhancement device characterized by comprising
On substrate layer substrate, hetero-junctions is grown;
Source electrode and drain electrode is made respectively at the hetero-junctions both ends;
The hetero-junctions between the source electrode and drain electrode is etched, nano-channel is formed;Between the source electrode and drain electrode, P-GaN cap layers are made, the P-GaN cap layers cover side and the hetero-junctions of the hetero-junctions perpendicular to the substrate layer Top surface;
Gate electrode is made in the P-GaN cap layers;
Passivation layer is made between the source electrode and the gate electrode and between gate electrode and the drain electrode;
Metal interconnection is made on the gate electrode.
6. the production method of HEMT enhancement device according to claim 5, which is characterized in that described in substrate layer substrate Above, the step of growth hetero-junctions specifically includes:
On the substrate layer, grown buffer layer;
Barrier layer is grown on the buffer layer, forms Two-dimensional electron in the contact position of the buffer layer and the barrier layer Gas obtains the hetero-junctions.
7. the production method of HEMT enhancement device according to claim 5, which is characterized in that the etching is described Hetero-junctions between source electrode and drain electrode forms the step of nano-channel and specifically includes:
Mask is carried out to the hetero-junctions using electron beam lithography machine;
The hetero-junctions is performed etching in the plasma using inductively coupled plasma etching machine, forms the nanometer ditch Road.
8. the production method of HEMT enhancement device according to claim 5, which is characterized in that described in the source electrode Between drain electrode, make P-GaN cap layers the step of specifically include:
One layer of GaN layer for mixing Mg is grown on the hetero-junctions;
Using RTP500 rapid thermal anneler, in 900 DEG C of N220 minutes thermal annealings are carried out in atmosphere to activate the Mg of doping, Obtain P-GaN layers.
9. the production method of HEMT enhancement device according to claim 5, which is characterized in that described in the P-GaN After the step of making gate electrode in cap layers, further includes:
P-GaN cap layers on all hetero-junctions other than etching removal gate region.
10. the production method of HEMT enhancement device according to claim 5, which is characterized in that described in the grid electricity Extremely the step of upper production metal interconnection, includes:
Using sense coupling machine in CF4With the etch rate etching removal area of grid of setting in plasma Passivation layer, formed interconnection aperture;
Ohmiker-50 electron beam evaporation platform is used in grid opening area to set evaporation rate to the substrate for making mask Carry out lead electrode evaporation of metal;
It is removed after the completion of lead electrode evaporation of metal, obtains complete lead electrode.
CN201910189819.XA 2019-03-13 2019-03-13 A kind of HEMT enhancement device and preparation method thereof Pending CN110085675A (en)

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Application publication date: 20190802