WO2018045175A1 - Normally-off gallium oxide based vertical transistors with p-type algan blocking layers - Google Patents

Normally-off gallium oxide based vertical transistors with p-type algan blocking layers Download PDF

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WO2018045175A1
WO2018045175A1 PCT/US2017/049625 US2017049625W WO2018045175A1 WO 2018045175 A1 WO2018045175 A1 WO 2018045175A1 US 2017049625 W US2017049625 W US 2017049625W WO 2018045175 A1 WO2018045175 A1 WO 2018045175A1
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layer
base layer
source
aluminum
doping concentration
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PCT/US2017/049625
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French (fr)
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Yu Cao
Zijian LI
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Hrl Laboratories, Llc
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Publication of WO2018045175A1 publication Critical patent/WO2018045175A1/en

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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • aspects of embodiments of the present invention are directed toward a normally-off vertical transistor structure utilizing n-type gallium oxide as the drift layer, p-type Ill-nitride (such as aluminum gallium nitride and/or gallium nitride) as the blocking layer, and n-type Ill-nitride (such as gallium nitride) for source contacts. Further aspects are directed toward gallium oxide based vertical transistors having p-type aluminum gallium nitride layers, which avoid the lack of p-type dopant for gallium oxide. Still further aspects are directed toward three-terminal vertical transistors utilizing gallium oxide as the drift layer.
  • a field-effect transistor includes an n-type gallium oxide substrate having a first doping concentration, an n-type gallium oxide drift layer on a first side of the substrate and having a second doping concentration smaller than the first doping concentration, a p-type Ill-nitride first base layer on the drift layer, and an n-type Ill-nitride source layer on the first base layer and having a third doping concentration larger than the second doping concentration.
  • the field-effect transistor may include further include: a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer; and a gate electrode on the gate insulator layer.
  • the field-effect transistor may further include: a drain ohmic contact on a second side of the substrate, the second side facing away from the first side; and source ohmic contacts in contact with the source layer and the first base layer.
  • the first base layer may include aluminum gallium nitride.
  • the first base layer may include a constant composition of aluminum.
  • the first base layer may include a graded composition of aluminum having a greatest composition of aluminum at a boundary with the drift layer and a least composition of aluminum proximal to the source layer.
  • the greatest composition of aluminum may be at least 70% of the molar composition of aluminum and gallium in the first base layer.
  • the field-effect transistor may further include a p-type gallium nitride second base layer between the first base layer and the source layer.
  • the source layer may include gallium nitride.
  • a method of forming a field-effect transistor includes providing an n-type gallium oxide drift layer having a first doping concentration on a first side of an n-type gallium oxide substrate having a second doping concentration larger than the first doping concentration, forming a p-type Ill-nitride first base layer on the drift layer, and forming an n-type Ill-nitride source layer on the first base layer and having a third doping concentration larger than the first doping concentration.
  • the method may further include: forming a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer; and forming a gate electrode on the gate insulator layer.
  • the method may further include: forming a drain ohmic contact on a second side of the substrate, the second side facing opposite to the first side; and forming source ohmic contacts contacting the source layer and the first base layer.
  • the first base layer may include aluminum gallium nitride.
  • the forming of the first base layer may include grading a composition of aluminum such that a greatest composition of aluminum is at a boundary with the drift layer and a least composition of aluminum is proximal to the source layer.
  • the greatest composition of aluminum may be at least 70% of the molar composition of aluminum and gallium in the first base layer.
  • the method may further include forming a p-type gallium nitride second base layer between the first base layer and the source layer.
  • the forming of the first base layer may include selectively etching the drift layer, and regrowing the first base layer in the selectively etched drift layer.
  • the regrowing of the first base layer in the selectively etched drift layer may include regrowing an n-type Ill-nitride layer in the selectively etched drift layer, and regrowing the first base layer on the regrown n-type Ill-nitride layer.
  • the forming of the source layer may include selectively etching the first base layer, and regrowing the source layer in the selectively etched first base layer.
  • the method may further include regrowing a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer.
  • the method may further include: selectively etching the gate insulator layer; forming source ohmic contacts contacting the source layer, the first base layer, and the selectively etched gate insulator layer; and forming a gate electrode on the gate insulator layer.
  • the above and other embodiments of the present invention provide for gallium oxide based vertical transistors with p-type Ill-nitride layers that are capable of handling higher power density than comparable designs, and enabling better breakdown voltage (BV) scaling without increasing device footprint. Such transistors are useful for power electronics applications.
  • FIG. 1 is a schematic cross-section of an example gallium oxide-based vertical transistor according to an embodiment of the present invention.
  • FIG. 2 is a band diagram of a comparable Ga 2 O 3 /GaN junction.
  • FIG. 3 is a band diagram of an example Ga 2 O 3 /AIGaN junction according to an embodiment of the present invention.
  • FIG. 4 is a schematic cross-section of an example p-type AIGaN base layer design according to an embodiment of the present invention.
  • FIG. 5 is a schematic cross-section of an example p-type AIGaN and GaN base layer design according to an embodiment of the present invention.
  • FIG. 6 is a flow diagram of an example method of creating a gallium oxide- based vertical field-effect transistor according to an embodiment of the present invention.
  • FIGs. 7-32 are schematic cross-sections illustrating an example method of manufacturing a gallium oxide-based vertical field-effect transistor according to an embodiment of the present invention.
  • FIG. 33 is a transmission electron microscopy (TEM) image of a cross section of a comparable gallium nitride on gallium oxide substrate device.
  • TEM transmission electron microscopy
  • any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range.
  • a range of "1 .0 to 10.0" is intended to include all subranges between (and including) the recited minimum value of 1 .0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1 .0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6.
  • Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited herein.
  • any element in a claim that does not explicitly state "means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a "means” or “step” clause as specified in 35 U.S.C. ⁇ 1 1 2(f).
  • the use of "step of” or “act of” in the claims herein is not intended to invoke the provisions of 35 U.S.C. ⁇ 1 1 2(f).
  • Embodiments of the present invention are directed to utilizing p-type nitride materials (e.g., Ill-nitride materials such as aluminum gallium nitride and/or gallium nitride), that have established (or mature) p-doping techniques as well as high breakdown properties, in vertical transistor designs.
  • On-resistance is an important parameter for transistors. Lower on-resistance may lower power consumption, which may improve transistor design.
  • Embodiments of the present invention provide for a way to reduce the on-resistance utilizing the positive conduction band offset between aluminum gallium nitride and gallium oxide. Such transistors may play an important role in power electronics development.
  • a figure of merit is a quantity that characterizes a device's performance (relative to comparable devices).
  • the Baliga figure of merit may be used to measure how suitable a material is for high frequency devices based on the intrinsic properties of the material.
  • the FOM is defined as £ E g ' where ⁇ is the (static) dielectric constant, ⁇ is the electron mobility, and E is the band gap of the semiconductor.
  • gallium oxide e.g., Ga 2 O 3
  • gallium oxide substrates may be similar to that used for Si. Therefore, gallium oxide may be suitable to be used for low-cost high power electronics where low power consumption and relatively high frequency applications are desired.
  • gallium oxide for example, has potential to reduce energy loss by 50% in electric vehicle motor drives and may be used in modern electronics from battery chargers to smart-grid components.
  • embodiments of the present invention refers to "one or more embodiments of the present invention.”
  • FIG. 1 is a schematic cross-section of an example gallium oxide-based vertical transistor 100 according to an embodiment of the present invention.
  • the vertical transistor 100 uses lightly doped (such as ⁇ 10 17 /cm 3 doping concentration) n-type gallium oxide (such as gallium (III) oxide, e.g., Ga2O3) as a drift layer 1 10, which is grown on a first side (such as a front side) of a heavily doped (e.g., conductive or degenerate) n-type gallium oxide substrate 120 (for example, as available from commercial substrate vendors, such as a 500 ⁇ gallium oxide substrate).
  • the drift layer 1 10 may be at least 0.5 ⁇ thick, and as much as 12 ⁇ (or more) thick (the thicker the drift layer 1 10, the more voltage that can be processed by the transistor 100).
  • the drift layer thickness may determine the device breakdown voltage and the resistance of the device.
  • a thin drift layer may lead to low breakdown voltage and a low on-resistance.
  • the breakdown voltage may be selected based on the application requirement.
  • a low on-resistance may reduce the energy loss from power electronics. In general, there is not a fundamental limit for the drift layer thickness.
  • lightly doped may be ⁇ 10 17 /cm 3 doping concentration, while heavily doped may be enough to produce a degenerate (e.g., conductive) semiconductor.
  • the gallium oxide in the drift layer 1 10 may be a ternary or quaternary compound, such as tin gallium oxide.
  • the n-type gallium oxide drift layer 1 10 may be patterned and etched (e.g., selectively etched) for p-type blocking layer regrowth.
  • p-type Ill-nitride such as aluminum gallium nitride (e.g., AIGaN, such as Al x Gai_ x N, 0 ⁇ x ⁇ 1 , or an alloy of AIN and GaN in different proportions) may be grown or annealed as a blocking layer 130 (or base layer).
  • the blocking layer 130 may serve to block the vertical electron flow (such as from source to drain) when the transistor is turned off.
  • the thickness of the blocking or base layer 130 may be between 300 nm and 1 ⁇ (or more, such as 2 ⁇ or even 10 ⁇ , provided the processing technique allows such a base layer to be formed).
  • the blocking layer should not be too thin. Otherwise, there may be punch- through breakdown that may limit the device when working under high voltage. On the other hand, if the blocking layer is too thick, it may result in processing
  • the percentage composition (e.g., molar composition) of aluminum may be constant throughout the blocking layer 130 (e.g., a constant composition of aluminum).
  • the AIGaN blocking layer 130 may be an alloy of AIN and GaN graded from a high percentage or greatest composition of aluminum (e.g., 70%) at the bottom of the AIGaN blocking layer 130 (close to the drift layer 1 10) to a low percentage of aluminum (e.g., as low as 0%) at the top of the AIGaN blocking layer 130 to produce a graded composition of aluminum.
  • Al and Ga may be deposited together to form the AIGaN blocking layer 130, with the Al/Ga ratio adjusted during deposition.
  • the AIN and GaN are grown (such as by epitaxial growth) on the drift layer 1 10 (or in selectively etched portions of the drift layer 1 10).
  • the graded p-type AIGaN blocking layer 130 may even be all p-type GaN at the top, or a lightly doped p-type GaN layer may be present at the top of the AIGaN blocking layer 130.
  • the percentage of Al may be molar concentration with respect to the total metal (e.g., Al and Ga) content in the AIGaN blocking layer 130.
  • the AIGaN blocking layer 130 may be patterned and etched (e.g., selectively etched) and a heavily doped n-type Ill-nitride (e.g., GaN, or ternary Ill- nitride alloy such as AIGaN or InGaN, or quaternary Ill-nitride alloy) layer 140 (or source layer) regrown on or in the patterned and etched AIGaN blocking layer 130 to form a source for the transistor 100.
  • the source layer 140 may be at least 200 nm thick.
  • Ohmic metal e.g., metal forming an ohmic contact
  • Ohmic metal may be deposited on and contact both the heavily doped n-type GaN source layer 140 and the lightly doped p-type AIGaN blocking layer 130 to function as a source electrode 150.
  • An insulator layer 160 may be deposited on the n-type GaN source layer, the p-type AIGaN blocking layer 130, and the n-type Ga 2 O 3 drift layer 1 10 to serve as a dielectric layer 160 with gate metal 170 deposited on the top.
  • a drain electrode 180 may be formed by coating a second side (such as a back side, which faces away from or opposite to the front side) of the Ga 2 O 3 substrate 120 with ohmic metal 180 (e.g., metal forming an ohmic contact with the Ga 2 O 3 substrate 120).
  • ohmic metal 180 e.g., metal forming an ohmic contact with the Ga 2 O 3 substrate 120.
  • FIG. 2 is a band diagram 200 of a comparable Ga 2 O 3 /GaN junction.
  • FIG. 3 is a band diagram 300 of an example Ga 2 O 3 /AIGaN junction according to an embodiment of the present invention.
  • FIG. 2 illustrates an example conduction band offset, such as 0.1 eV, exhibited between gallium oxide (e.g., Ga 2 O 3 ) and gallium nitride (e.g., GaN) in a comparable circuit to the transistor 100 in FIG. 1 , but without any graded p-type AIGaN blocking layer 130.
  • FIG. 33 is a transmission electron microscopy (TEM) image of a cross section of such a comparable gallium nitride on gallium oxide substrate device. In FIG. 33, the location of where an AIGaN blocking layer would appear according to an embodiment of the present invention is shown.
  • TEM transmission electron microscopy
  • AIGaN aluminum gallium nitride
  • the comparable band diagram is shown in FIG. 3.
  • the conduction band of AIGaN is higher than that of Ga 2 O 3 and GaN (as illustrated in FIG. 2), indicating the conduction band offset A Ec becomes positive.
  • the electrons flow first from the heavily doped n- type GaN layer 140 into the lightly doped p-type graded AIGaN blocking layer 130 and then into the lightly doped n-type Ga 2 O 3 drift layer. Due to the positive A Ec, the electrons gain high velocity when they are injected into the Ga 2 O 3 drift layer, thereby resulting in low on-resistance.
  • FIG. 4 is a schematic cross-section of an example p-type AIGaN base layer design 400 according to an embodiment of the present invention.
  • the design 400 may include a p-type AIGaN base layer 410 between a Ga 2 O 3 drift layer 420 and a heavily doped n-type GaN source layer 430.
  • the AIGaN base layer 410 may be an alloy with, for example, constant Al composition
  • x may be larger than y in the graded AIGaN layer 410.
  • the composition y may be zero, in which case at the top of the p-type AIGaN base layer 410 (e.g., at interface 450), there may be a layer of p- type GaN that is adjacent to the heavily doped n-type GaN source layer 430. It should be noted that the band gap energy of the p-type AIGaN layer may increase in the direction from the Ga 2 O 3 drift layer to the n+ GaN source layer.
  • the critical electric field of Ga 2 O 3 is 8 MV/cm.
  • x should be at least 70% so that the breakdown property will not be limited at the AIGaN side 410 of the AIGaN/Ga 2 O 3 interface 440.
  • FIG. 5 is a schematic cross-section of an example p-type AIGaN and GaN base layer design 500 according to an embodiment of the present invention.
  • the design 500 may include a p-type GaN first base layer 510 (e.g., a lightly doped base layer) between an n-type Ga 2 O 3 drift layer 520 (e.g., a lightly doped drift layer) and a lightly doped p-type GaN second base layer 515.
  • a heavily doped n-type GaN source layer 530 may be formed on the p-type GaN second base layer 515.
  • the AIGaN first base layer 510 may be an alloy with, for example, constant Al composition throughout or graded Al composition from a higher Al percentage (such as 70% Al) at the AIGaN/Ga 2 O 3 interface 540 to a lower Al percentage (such as 0% or nearly 0% Al) at the p-type AIGaN/GaN interface 550.
  • a higher Al percentage such as 70% Al
  • a lower Al percentage such as 0% or nearly 0% Al
  • FIG. 6 is a flow diagram of an example method of creating a gallium oxide- based vertical field-effect transistor (such as the vertical transistor 100 of FIG. 1 ) according to an embodiment of the present invention.
  • a lightly doped n-type gallium oxide drift layer (such as the drift layer 1 10 of FIG. 1 ) is formed on a first side (e.g., a front side) of a heavily doped n-type gallium oxide substrate (such as the substrate 120 of FIG. 1 ).
  • a p-type Ill-nitride base layer (such as the AIGaN base layer 130 of FIG. 1 ) is formed on the drift layer.
  • a heavily doped n-type Ill-nitride source layer (such as the GaN source layer 140 of FIG. 1 ) is formed on the base layer.
  • a dielectric gate insulator layer (such as the gate insulator layer 160 of FIG. 1 ) is formed on the source layer, the base layer, and the drift layer.
  • source ohmic contacts (such as the source electrodes 150 of FIG. 1 ) are formed contacting the n-type source layer and the p-type base layer.
  • a gate electrode (such as the gate electrode 170 of FIG. 1 ) is formed on the gate insulator layer.
  • a drain ohmic contact (such as the drain electrode 180 of FIG. 1 ) is formed on a second side (e.g., a backside) of the substrate.
  • FIGs. 7-32 are schematic cross-sections illustrating an example method of manufacturing a gallium oxide-based vertical field-effect transistor according to an embodiment of the present invention.
  • a heavily doped gallium oxide substrate is provided, on which is grown (such as by epitaxy) a lightly doped gallium oxide drift layer.
  • a first mask is used to pattern and form an iso mark (illustrated schematically on the upper right corner of the drawing).
  • the iso-mark (or i-mark) may be a mark formed by etching into the wafer, and may be used for alignment purposes for the processing steps that follow (e.g., to help align the remaining masks to this mark, which helps make sure the device will be processed as designed.
  • a first layer of silicon dioxide (silica) is formed, such as by plasma-enhanced chemical vapor deposition (PECVD), on the drift layer.
  • PECVD plasma-enhanced chemical vapor deposition
  • a first layer of photoresist is formed on the silica layer, and a second mask is used to pattern and form (for example, by lithography) first openings in the first photoresist layer corresponding to the base layers to be formed later
  • the first openings are extended (e.g., by wet and dry etching) through the first silica layer and partially into the drift layer to form first channels for the base layers.
  • the first photoresist layer is removed (e.g., stripped) to reveal the remaining first silica layer.
  • lightly doped p-type aluminum gallium nitride base layers are grown, such as by metalorganic chemical vapor deposition (MOCVD), in the exposed first channels.
  • MOCVD metalorganic chemical vapor deposition
  • an n-type nitride layer such as gallium nitride or aluminum gallium nitride
  • FIG. 14 the remaining first silica layer is removed, while in FIG. 15, a second silica layer is formed on the drift and base layers, such as by the same PECVD process used to form the first silica layer.
  • a second photoresist layer is formed on the second silica layer, and a third mask is used to pattern and form (for example, by the same lithography process used to etch the first photoresist layer) second openings in the second photoresist layer corresponding to the source layers to be formed later.
  • the second openings are extended (e.g., by wet and dry etching) through the second silica layer and into the base layers to form second channels for the source layers.
  • the second photoresist layer is removed (e.g., stripped) to reveal the remaining second silica layer.
  • heavily doped n-type aluminum gallium nitride source layers are grown, such as by MOCVD, in the exposed second channels.
  • the remaining second silica layer is removed.
  • a gate dielectric layer is formed on the drift, base, and source layers.
  • a third photoresist layer is formed on the gate dielectric layer, and a fourth mask is used to pattern and form (for example, by the same lithography process used to etch the first and second photoresist layers) third openings in the third photoresist layer corresponding to the base ohmic contacts to be formed later.
  • the third openings are extended (e.g., by wet etching) through the gate dielectric layer to expose contacting surfaces of the base layers.
  • ohmic contacts are formed in the third openings, e.g., by depositing metal on the third photoresist layer and exposed contacting surfaces of the base layers, removing the exposed metal and remaining third photoresist layer (e.g., by lift-off) to reveal the metal formed in the third openings, and finishing the metal-semiconductor base ohmic contacts by heat treatment, such as rapid thermal annealing (RTA).
  • RTA rapid thermal annealing
  • a fourth photoresist layer is formed on the gate dielectric layer and base ohmic contacts, and a fifth mask is used to pattern and form (for example, by the same lithography process used to etch the first, second, and third photoresist layers) fourth openings in the fourth photoresist layer corresponding to the source ohmic contacts to be formed later, and the fourth openings are extended (e.g., by wet etching) through the gate dielectric layer to expose contacting surfaces of the source layers.
  • ohmic contacts are formed in the fourth openings, e.g., by depositing metal on the fourth photoresist layer and exposed contacting surfaces of the source layers, and removing the exposed metal and remaining fourth photoresist layer (e.g., by lift-off) to reveal the source ohmic contacts.
  • the n-metal contacts may be annealed after the metal is deposited.
  • a fifth photoresist layer is formed on the gate dielectric layer and base and source ohmic contacts, and a sixth mask is used to pattern and form (for example, by the same lithography process used to etch the first through fourth photoresist layers) fifth openings in the fifth photoresist layer corresponding to the ion implantation areas (e.g., areas of the drift layer outside of and not between the source layers) to be formed later.
  • ion implantation areas e.g., areas of the drift layer outside of and not between the source layers
  • doping is performed (for example, by ion implantation) on the fifth openings (the remaining areas being shielded by the fifth photoresist layer) to form the ion implantation areas in the drift and gate dielectric layers, and the fifth photoresist layer is removed (e.g., stripped) to reveal the ion implantation areas, leaving an l-mark (illustrated schematically on the upper right corner of the drawing).
  • a sixth photoresist layer is formed on the gate dielectric layer, base and source ohmic contacts, and ion implantation areas, and a seventh mask is used to pattern and form (for example, by the same lithography process used to etch the first through fifth photoresist layers) sixth openings in the sixth photoresist layer corresponding to the gate and source electrode areas to be formed later.
  • the gate and source electrodes are formed in the sixth openings, e.g., by depositing metal on the sixth photoresist layer and sixth openings, and removing the exposed metal and remaining sixth photoresist layer (e.g., by lift-off) to reveal the gate and source electrodes.
  • an eighth mask is used to metal plate the gate and source electrodes.
  • metal is applied to the backside of the gallium oxide substrate to form the drain electrode.
  • the backside metal may be annealed after it is applied to the backside of the gallium oxide substrate.

Abstract

A field-effect transistor includes an n-type gallium oxide substrate having a first doping concentration; an n-type gallium oxide drift layer on a first side of the substrate and having a second doping concentration smaller than the first doping concentration, a p-type Ill-nitride first base layer on the drift layer, and an n-type Ill- nitride source layer on the first base layer and having a third doping concentration larger than the second doping concentration. A method of forming the field-effect transistor includes providing an n-type gallium oxide drift layer having a first doping concentration on a first side of an n-type gallium oxide substrate having a second doping concentration larger than the first doping concentration, forming a p-type Ill- nitride first base layer on the drift layer, and forming an n-type Ill-nitride source layer on the first base layer and having a third doping concentration larger than the first doping concentration.

Description

NORMALLY-OFF GALLIUM OXIDE BASED VERTICAL
TRANSISTORS WITH P-TYPE AIGaN BLOCKING LAYERS
BACKGROUND
1 . Field
[0001] Aspects of embodiments of the present invention relate to Gallium oxide based vertical transistors.
2. Description of Related Art
[0002] Most semiconductor transistor designs feature a normally-on operation and with a lateral (or horizontal) layout. Transistors with vertical structures, however, have been developed in silicon-based technology. Vertical diodes having only two terminals have also been developed, but lack a transistor capability. SUMMARY
[0003] Aspects of embodiments of the present invention are directed toward a normally-off vertical transistor structure utilizing n-type gallium oxide as the drift layer, p-type Ill-nitride (such as aluminum gallium nitride and/or gallium nitride) as the blocking layer, and n-type Ill-nitride (such as gallium nitride) for source contacts. Further aspects are directed toward gallium oxide based vertical transistors having p-type aluminum gallium nitride layers, which avoid the lack of p-type dopant for gallium oxide. Still further aspects are directed toward three-terminal vertical transistors utilizing gallium oxide as the drift layer.
[0004] According to an embodiment of the present invention, a field-effect transistor is provided. The field-effect transistor includes an n-type gallium oxide substrate having a first doping concentration, an n-type gallium oxide drift layer on a first side of the substrate and having a second doping concentration smaller than the first doping concentration, a p-type Ill-nitride first base layer on the drift layer, and an n-type Ill-nitride source layer on the first base layer and having a third doping concentration larger than the second doping concentration.
[0005] The field-effect transistor may include further include: a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer; and a gate electrode on the gate insulator layer.
[0006] The field-effect transistor may further include: a drain ohmic contact on a second side of the substrate, the second side facing away from the first side; and source ohmic contacts in contact with the source layer and the first base layer.
[0007] The first base layer may include aluminum gallium nitride.
[0008] The first base layer may include a constant composition of aluminum. [0009] The first base layer may include a graded composition of aluminum having a greatest composition of aluminum at a boundary with the drift layer and a least composition of aluminum proximal to the source layer.
[0010] The greatest composition of aluminum may be at least 70% of the molar composition of aluminum and gallium in the first base layer.
[0011] The field-effect transistor may further include a p-type gallium nitride second base layer between the first base layer and the source layer.
[0012] The source layer may include gallium nitride.
[0013] According to another embodiment of the present invention, a method of forming a field-effect transistor is provided. The method includes providing an n-type gallium oxide drift layer having a first doping concentration on a first side of an n-type gallium oxide substrate having a second doping concentration larger than the first doping concentration, forming a p-type Ill-nitride first base layer on the drift layer, and forming an n-type Ill-nitride source layer on the first base layer and having a third doping concentration larger than the first doping concentration.
[0014] The method may further include: forming a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer; and forming a gate electrode on the gate insulator layer.
[0015] The method may further include: forming a drain ohmic contact on a second side of the substrate, the second side facing opposite to the first side; and forming source ohmic contacts contacting the source layer and the first base layer.
[0016] The first base layer may include aluminum gallium nitride.
[0017] The forming of the first base layer may include grading a composition of aluminum such that a greatest composition of aluminum is at a boundary with the drift layer and a least composition of aluminum is proximal to the source layer.
[0018] The greatest composition of aluminum may be at least 70% of the molar composition of aluminum and gallium in the first base layer.
[0019] The method may further include forming a p-type gallium nitride second base layer between the first base layer and the source layer.
[0020] The forming of the first base layer may include selectively etching the drift layer, and regrowing the first base layer in the selectively etched drift layer.
[0021] The regrowing of the first base layer in the selectively etched drift layer may include regrowing an n-type Ill-nitride layer in the selectively etched drift layer, and regrowing the first base layer on the regrown n-type Ill-nitride layer.
[0022] The forming of the source layer may include selectively etching the first base layer, and regrowing the source layer in the selectively etched first base layer.
[0023] The method may further include regrowing a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer. [0024] The method may further include: selectively etching the gate insulator layer; forming source ohmic contacts contacting the source layer, the first base layer, and the selectively etched gate insulator layer; and forming a gate electrode on the gate insulator layer.
[0025] The above and other embodiments of the present invention provide for gallium oxide based vertical transistors with p-type Ill-nitride layers that are capable of handling higher power density than comparable designs, and enabling better breakdown voltage (BV) scaling without increasing device footprint. Such transistors are useful for power electronics applications.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
[0027] The accompanying drawings, together with the specification, illustrate example embodiments of the present invention. These drawings, together with the description, serve to better describe aspects and principles of the present invention.
[0028] FIG. 1 is a schematic cross-section of an example gallium oxide-based vertical transistor according to an embodiment of the present invention.
[0029] FIG. 2 is a band diagram of a comparable Ga2O3/GaN junction.
[0030] FIG. 3 is a band diagram of an example Ga2O3/AIGaN junction according to an embodiment of the present invention.
[0031] FIG. 4 is a schematic cross-section of an example p-type AIGaN base layer design according to an embodiment of the present invention.
[0032] FIG. 5 is a schematic cross-section of an example p-type AIGaN and GaN base layer design according to an embodiment of the present invention.
[0033] FIG. 6 is a flow diagram of an example method of creating a gallium oxide- based vertical field-effect transistor according to an embodiment of the present invention.
[0034] FIGs. 7-32 are schematic cross-sections illustrating an example method of manufacturing a gallium oxide-based vertical field-effect transistor according to an embodiment of the present invention.
[0035] FIG. 33 is a transmission electron microscopy (TEM) image of a cross section of a comparable gallium nitride on gallium oxide substrate device.
DETAILED DESCRIPTION
[0036] The following description is provided to enable one of ordinary skill in the art to make and use embodiments of the present invention and to incorporate such embodiments in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the aspects, principles, and novel features disclosed herein.
[0037] As used herein, the term "substantially," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.
[0038] In addition, any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of "1 .0 to 10.0" is intended to include all subranges between (and including) the recited minimum value of 1 .0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1 .0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited herein.
[0039] In the detailed description that follows, numerous specific details are set forth in order to provide a more thorough understanding of some of the embodiments of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices may be shown in block diagram form, rather than in detail, in order to avoid obscuring aspects of the present invention.
[0040] The reader's attention is directed to all papers and documents that are filed concurrently with this specification and that are open to public inspection with this specification, and the contents of all such papers and documents are
incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is only one example of a generic series of equivalent or similar features. Similarly, unless indicated to the contrary, features of one embodiment may be incorporated into other embodiments without departing from the spirit and scope of the present invention.
[0041 ] Furthermore, any element in a claim that does not explicitly state "means for" performing a specified function, or "step for" performing a specific function, is not to be interpreted as a "means" or "step" clause as specified in 35 U.S.C. § 1 1 2(f). In particular, the use of "step of" or "act of" in the claims herein is not intended to invoke the provisions of 35 U.S.C. § 1 1 2(f).
[0042] By way of example, various embodiments of the present invention are directed toward normally-off gallium oxide based vertical transistors. However, these embodiments are presented as examples and the present invention is not limited thereto.
[0043] Embodiments of the present invention are directed to utilizing p-type nitride materials (e.g., Ill-nitride materials such as aluminum gallium nitride and/or gallium nitride), that have established (or mature) p-doping techniques as well as high breakdown properties, in vertical transistor designs. On-resistance is an important parameter for transistors. Lower on-resistance may lower power consumption, which may improve transistor design. Embodiments of the present invention provide for a way to reduce the on-resistance utilizing the positive conduction band offset between aluminum gallium nitride and gallium oxide. Such transistors may play an important role in power electronics development.
[0044] A figure of merit is a quantity that characterizes a device's performance (relative to comparable devices). In power semiconductor devices, the Baliga figure of merit (FOM) may be used to measure how suitable a material is for high frequency devices based on the intrinsic properties of the material. The FOM is defined as £ Eg ' where ε is the (static) dielectric constant, μ is the electron mobility, and E is the band gap of the semiconductor. Using this FOM, gallium oxide (e.g., Ga2O3) has the highest figure of merit compared to comparable materials, such as Si (more than 300x better), SiC (more than 4x better), and gallium nitride (e.g., GaN). The manufacturing method for the gallium oxide substrates may be similar to that used for Si. Therefore, gallium oxide may be suitable to be used for low-cost high power electronics where low power consumption and relatively high frequency applications are desired. Gallium oxide, for example, has potential to reduce energy loss by 50% in electric vehicle motor drives and may be used in modern electronics from battery chargers to smart-grid components.
[0045] Example embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals refer to the same or similar elements throughout.
Expressions such as "at least one of," "one of," or "selected from," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Herein, the use of the term "may," when describing
embodiments of the present invention, refers to "one or more embodiments of the present invention." In addition, the use of alternative language, such as "or," when describing embodiments of the present invention, refers to "one or more
embodiments of the present invention" for each corresponding item listed.
[0046] FIG. 1 is a schematic cross-section of an example gallium oxide-based vertical transistor 100 according to an embodiment of the present invention.
[0047] Referring to FIG. 1 , the vertical transistor 100 uses lightly doped (such as ≤ 1017/cm3 doping concentration) n-type gallium oxide (such as gallium (III) oxide, e.g., Ga2O3) as a drift layer 1 10, which is grown on a first side (such as a front side) of a heavily doped (e.g., conductive or degenerate) n-type gallium oxide substrate 120 (for example, as available from commercial substrate vendors, such as a 500 μιη gallium oxide substrate). The drift layer 1 10 may be at least 0.5 μιη thick, and as much as 12 μιη (or more) thick (the thicker the drift layer 1 10, the more voltage that can be processed by the transistor 100). The drift layer thickness may determine the device breakdown voltage and the resistance of the device. A thin drift layer may lead to low breakdown voltage and a low on-resistance. The breakdown voltage may be selected based on the application requirement. A low on-resistance may reduce the energy loss from power electronics. In general, there is not a fundamental limit for the drift layer thickness.
[0048] Herein, unless otherwise specified, the use of relative terms such as "lightly doped" and "heavily doped" are as would be interpreted by someone of ordinary skill in the art. For example, lightly doped may be < 1017/cm3 doping concentration, while heavily doped may be enough to produce a degenerate (e.g., conductive) semiconductor. In other embodiments, the gallium oxide in the drift layer 1 10 may be a ternary or quaternary compound, such as tin gallium oxide.
[0049] The n-type gallium oxide drift layer 1 10 may be patterned and etched (e.g., selectively etched) for p-type blocking layer regrowth. By applying regrowth techniques as known by those of ordinary skill in the art, p-type (e.g., lightly doped p- type) Ill-nitride, such as aluminum gallium nitride (e.g., AIGaN, such as AlxGai_xN, 0 < x < 1 , or an alloy of AIN and GaN in different proportions) may be grown or annealed as a blocking layer 130 (or base layer). The blocking layer 130 may serve to block the vertical electron flow (such as from source to drain) when the transistor is turned off. The thickness of the blocking or base layer 130 may be between 300 nm and 1 μιη (or more, such as 2 μιη or even 10 μιη, provided the processing technique allows such a base layer to be formed). [0050] The blocking layer should not be too thin. Otherwise, there may be punch- through breakdown that may limit the device when working under high voltage. On the other hand, if the blocking layer is too thick, it may result in processing
difficulties, such as having to etch very deeply into a gallium oxide (e.g., Ga2O3) epitaxial drift layer. However, as long as the processing technique allows such fabrication, a thicker drift should be possible.
[0051] In some embodiments, the percentage composition (e.g., molar composition) of aluminum may be constant throughout the blocking layer 130 (e.g., a constant composition of aluminum). In other embodiments, in order to enhance the p-type conductivity utilizing the nitride polarization effect, the AIGaN blocking layer 130 may be an alloy of AIN and GaN graded from a high percentage or greatest composition of aluminum (e.g., 70%) at the bottom of the AIGaN blocking layer 130 (close to the drift layer 1 10) to a low percentage of aluminum (e.g., as low as 0%) at the top of the AIGaN blocking layer 130 to produce a graded composition of aluminum. For example, Al and Ga may be deposited together to form the AIGaN blocking layer 130, with the Al/Ga ratio adjusted during deposition. In some embodiments, the AIN and GaN are grown (such as by epitaxial growth) on the drift layer 1 10 (or in selectively etched portions of the drift layer 1 10).
[0052] In some embodiments, the graded p-type AIGaN blocking layer 130 may even be all p-type GaN at the top, or a lightly doped p-type GaN layer may be present at the top of the AIGaN blocking layer 130. Here, the percentage of Al may be molar concentration with respect to the total metal (e.g., Al and Ga) content in the AIGaN blocking layer 130.
[0053] The AIGaN blocking layer 130 may be patterned and etched (e.g., selectively etched) and a heavily doped n-type Ill-nitride (e.g., GaN, or ternary Ill- nitride alloy such as AIGaN or InGaN, or quaternary Ill-nitride alloy) layer 140 (or source layer) regrown on or in the patterned and etched AIGaN blocking layer 130 to form a source for the transistor 100. The source layer 140 may be at least 200 nm thick.
[0054] Ohmic metal (e.g., metal forming an ohmic contact) may be deposited on and contact both the heavily doped n-type GaN source layer 140 and the lightly doped p-type AIGaN blocking layer 130 to function as a source electrode 150. An insulator layer 160 may be deposited on the n-type GaN source layer, the p-type AIGaN blocking layer 130, and the n-type Ga2O3 drift layer 1 10 to serve as a dielectric layer 160 with gate metal 170 deposited on the top. Meanwhile, a drain electrode 180 may be formed by coating a second side (such as a back side, which faces away from or opposite to the front side) of the Ga2O3 substrate 120 with ohmic metal 180 (e.g., metal forming an ohmic contact with the Ga2O3 substrate 120). [0055] FIG. 2 is a band diagram 200 of a comparable Ga2O3/GaN junction. FIG. 3 is a band diagram 300 of an example Ga2O3/AIGaN junction according to an embodiment of the present invention.
[0056] FIG. 2 illustrates an example conduction band offset, such as 0.1 eV, exhibited between gallium oxide (e.g., Ga2O3) and gallium nitride (e.g., GaN) in a comparable circuit to the transistor 100 in FIG. 1 , but without any graded p-type AIGaN blocking layer 130. FIG. 33 is a transmission electron microscopy (TEM) image of a cross section of such a comparable gallium nitride on gallium oxide substrate device. In FIG. 33, the location of where an AIGaN blocking layer would appear according to an embodiment of the present invention is shown.
[0057] When a portion of the gallium nitride (e.g., GaN) is replaced by aluminum gallium nitride (e.g., AIGaN, such as an alloy of AIN and GaN), however, such as in the transistor 100 of FIG. 1 , the comparable band diagram is shown in FIG. 3. As the molar concentration of Al in the AIGaN alloy increases, the conduction band of AIGaN is higher than that of Ga2O3 and GaN (as illustrated in FIG. 2), indicating the conduction band offset A Ec becomes positive. During the transistor operation (such as with the transistor 100 of FIG. 1 ), the electrons flow first from the heavily doped n- type GaN layer 140 into the lightly doped p-type graded AIGaN blocking layer 130 and then into the lightly doped n-type Ga2O3 drift layer. Due to the positive A Ec, the electrons gain high velocity when they are injected into the Ga2O3 drift layer, thereby resulting in low on-resistance.
[0058] FIG. 4 is a schematic cross-section of an example p-type AIGaN base layer design 400 according to an embodiment of the present invention.
[0059] The design 400 may include a p-type AIGaN base layer 410 between a Ga2O3 drift layer 420 and a heavily doped n-type GaN source layer 430. The AIGaN base layer 410 may be an alloy with, for example, constant Al composition
throughout or graded Al composition (e.g., continuously varying composition) from a higher Al percentage (Al%=x) at the AIGaN/Ga2O3 interface 440 to a lower Al percentage (Al%=y) at the AIGaN/GaN interface 450, as shown in FIG. 4 (e.g., x>y>0). In embodiments of the base layer design 400, x may be larger than y in the graded AIGaN layer 410. The composition y may be zero, in which case at the top of the p-type AIGaN base layer 410 (e.g., at interface 450), there may be a layer of p- type GaN that is adjacent to the heavily doped n-type GaN source layer 430. It should be noted that the band gap energy of the p-type AIGaN layer may increase in the direction from the Ga2O3 drift layer to the n+ GaN source layer.
[0060] The critical electric field of Ga2O3 is 8 MV/cm. To match this breakdown field, in some embodiments of the base layer design 400, x should be at least 70% so that the breakdown property will not be limited at the AIGaN side 410 of the AIGaN/Ga2O3 interface 440.
[0061] FIG. 5 is a schematic cross-section of an example p-type AIGaN and GaN base layer design 500 according to an embodiment of the present invention.
[0062] The design 500 may include a p-type GaN first base layer 510 (e.g., a lightly doped base layer) between an n-type Ga2O3 drift layer 520 (e.g., a lightly doped drift layer) and a lightly doped p-type GaN second base layer 515. A heavily doped n-type GaN source layer 530 may be formed on the p-type GaN second base layer 515. The AIGaN first base layer 510 may be an alloy with, for example, constant Al composition throughout or graded Al composition from a higher Al percentage (such as 70% Al) at the AIGaN/Ga2O3 interface 540 to a lower Al percentage (such as 0% or nearly 0% Al) at the p-type AIGaN/GaN interface 550.
[0063] FIG. 6 is a flow diagram of an example method of creating a gallium oxide- based vertical field-effect transistor (such as the vertical transistor 100 of FIG. 1 ) according to an embodiment of the present invention.
[0064] Referring to FIG. 6, in step 610, a lightly doped n-type gallium oxide drift layer (such as the drift layer 1 10 of FIG. 1 ) is formed on a first side (e.g., a front side) of a heavily doped n-type gallium oxide substrate (such as the substrate 120 of FIG. 1 ). In step 620, a p-type Ill-nitride base layer (such as the AIGaN base layer 130 of FIG. 1 ) is formed on the drift layer. In step 630, a heavily doped n-type Ill-nitride source layer (such as the GaN source layer 140 of FIG. 1 ) is formed on the base layer.
[0065] In step 640, a dielectric gate insulator layer (such as the gate insulator layer 160 of FIG. 1 ) is formed on the source layer, the base layer, and the drift layer. In step 650, source ohmic contacts (such as the source electrodes 150 of FIG. 1 ) are formed contacting the n-type source layer and the p-type base layer. In step 660, a gate electrode (such as the gate electrode 170 of FIG. 1 ) is formed on the gate insulator layer. In step 670, a drain ohmic contact (such as the drain electrode 180 of FIG. 1 ) is formed on a second side (e.g., a backside) of the substrate.
[0066] FIGs. 7-32 are schematic cross-sections illustrating an example method of manufacturing a gallium oxide-based vertical field-effect transistor according to an embodiment of the present invention.
[0067] In FIG. 7, a heavily doped gallium oxide substrate is provided, on which is grown (such as by epitaxy) a lightly doped gallium oxide drift layer. In FIG. 8, a first mask is used to pattern and form an iso mark (illustrated schematically on the upper right corner of the drawing). The iso-mark (or i-mark) may be a mark formed by etching into the wafer, and may be used for alignment purposes for the processing steps that follow (e.g., to help align the remaining masks to this mark, which helps make sure the device will be processed as designed. In FIG. 9, a first layer of silicon dioxide (silica) is formed, such as by plasma-enhanced chemical vapor deposition (PECVD), on the drift layer. In FIG. 10, a first layer of photoresist is formed on the silica layer, and a second mask is used to pattern and form (for example, by lithography) first openings in the first photoresist layer corresponding to the base layers to be formed later.
[0068] In FIG. 1 1 , the first openings are extended (e.g., by wet and dry etching) through the first silica layer and partially into the drift layer to form first channels for the base layers. In FIG.12, the first photoresist layer is removed (e.g., stripped) to reveal the remaining first silica layer. In FIG. 13, lightly doped p-type aluminum gallium nitride base layers are grown, such as by metalorganic chemical vapor deposition (MOCVD), in the exposed first channels. In other embodiments, an n-type nitride layer (such as gallium nitride or aluminum gallium nitride) may be grown in the exposed first channels before growing the p-type aluminum gallium nitride base layers.
[0069] In FIG. 14, the remaining first silica layer is removed, while in FIG. 15, a second silica layer is formed on the drift and base layers, such as by the same PECVD process used to form the first silica layer. In FIG. 16, a second photoresist layer is formed on the second silica layer, and a third mask is used to pattern and form (for example, by the same lithography process used to etch the first photoresist layer) second openings in the second photoresist layer corresponding to the source layers to be formed later.
[0070] In FIG. 17, the second openings are extended (e.g., by wet and dry etching) through the second silica layer and into the base layers to form second channels for the source layers. In FIG.18, the second photoresist layer is removed (e.g., stripped) to reveal the remaining second silica layer. In FIG. 19, heavily doped n-type aluminum gallium nitride source layers are grown, such as by MOCVD, in the exposed second channels.
[0071] In FIG. 20, the remaining second silica layer is removed. In FIG. 21 , a gate dielectric layer is formed on the drift, base, and source layers. In FIG. 22, a third photoresist layer is formed on the gate dielectric layer, and a fourth mask is used to pattern and form (for example, by the same lithography process used to etch the first and second photoresist layers) third openings in the third photoresist layer corresponding to the base ohmic contacts to be formed later.
[0072] In FIG. 23, the third openings are extended (e.g., by wet etching) through the gate dielectric layer to expose contacting surfaces of the base layers. In FIG. 24, ohmic contacts are formed in the third openings, e.g., by depositing metal on the third photoresist layer and exposed contacting surfaces of the base layers, removing the exposed metal and remaining third photoresist layer (e.g., by lift-off) to reveal the metal formed in the third openings, and finishing the metal-semiconductor base ohmic contacts by heat treatment, such as rapid thermal annealing (RTA). In FIG. 25, a fourth photoresist layer is formed on the gate dielectric layer and base ohmic contacts, and a fifth mask is used to pattern and form (for example, by the same lithography process used to etch the first, second, and third photoresist layers) fourth openings in the fourth photoresist layer corresponding to the source ohmic contacts to be formed later, and the fourth openings are extended (e.g., by wet etching) through the gate dielectric layer to expose contacting surfaces of the source layers.
[0073] In FIG. 26, ohmic contacts are formed in the fourth openings, e.g., by depositing metal on the fourth photoresist layer and exposed contacting surfaces of the source layers, and removing the exposed metal and remaining fourth photoresist layer (e.g., by lift-off) to reveal the source ohmic contacts. In some embodiments, the n-metal contacts may be annealed after the metal is deposited. In FIG. 27, a fifth photoresist layer is formed on the gate dielectric layer and base and source ohmic contacts, and a sixth mask is used to pattern and form (for example, by the same lithography process used to etch the first through fourth photoresist layers) fifth openings in the fifth photoresist layer corresponding to the ion implantation areas (e.g., areas of the drift layer outside of and not between the source layers) to be formed later. In FIG. 28, doping is performed (for example, by ion implantation) on the fifth openings (the remaining areas being shielded by the fifth photoresist layer) to form the ion implantation areas in the drift and gate dielectric layers, and the fifth photoresist layer is removed (e.g., stripped) to reveal the ion implantation areas, leaving an l-mark (illustrated schematically on the upper right corner of the drawing).
[0074] In FIG. 29, a sixth photoresist layer is formed on the gate dielectric layer, base and source ohmic contacts, and ion implantation areas, and a seventh mask is used to pattern and form (for example, by the same lithography process used to etch the first through fifth photoresist layers) sixth openings in the sixth photoresist layer corresponding to the gate and source electrode areas to be formed later. In FIG. 30, the gate and source electrodes are formed in the sixth openings, e.g., by depositing metal on the sixth photoresist layer and sixth openings, and removing the exposed metal and remaining sixth photoresist layer (e.g., by lift-off) to reveal the gate and source electrodes. In FIG. 31 , an eighth mask is used to metal plate the gate and source electrodes.
[0075] In FIG. 32, metal is applied to the backside of the gallium oxide substrate to form the drain electrode. In some embodiments, the backside metal may be annealed after it is applied to the backside of the gallium oxide substrate. [0076] While the present invention has been described in connection with certain example embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, and equivalents thereof.

Claims

WHAT IS CLAIMED IS:
1 . A field-effect transistor comprising:
an n-type gallium oxide substrate having a first doping concentration;
an n-type gallium oxide drift layer on a first side of the substrate and having a second doping concentration smaller than the first doping concentration;
a p-type Ill-nitride first base layer on the drift layer; and
an n-type Ill-nitride source layer on the first base layer and having a third doping concentration larger than the second doping concentration.
2. The field-effect transistor of claim 1 , further comprising:
a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer; and
a gate electrode on the gate insulator layer.
3. The field-effect transistor of claim 2, further comprising:
a drain ohmic contact on a second side of the substrate, the second side facing away from the first side; and
source ohmic contacts in contact with the source layer and the first base layer.
4. The field-effect transistor of claim 1 , wherein the first base layer comprises aluminum gallium nitride.
5. The field-effect transistor of claim 4, wherein the first base layer comprises a constant composition of aluminum.
6. The field-effect transistor of claim 4, wherein the first base layer comprises a graded composition of aluminum having a greatest composition of aluminum at a boundary with the drift layer and a least composition of aluminum proximal to the source layer.
7. The field-effect transistor of claim 6, wherein the greatest composition of aluminum is at least 70% of the molar composition of aluminum and gallium in the first base layer.
8. The field-effect transistor of claim 4, further comprising a p-type gallium nitride second base layer between the first base layer and the source layer.
9. The field-effect transistor of claim 1 , wherein the source layer comprises gallium nitride.
10. A method of forming a field-effect transistor, the method comprising: providing an n-type gallium oxide drift layer having a first doping concentration on a first side of an n-type gallium oxide substrate having a second doping concentration larger than the first doping concentration;
forming a p-type Ill-nitride first base layer on the drift layer; and
forming an n-type Ill-nitride source layer on the first base layer and having a third doping concentration larger than the first doping concentration.
1 1 . The method of claim 10, further comprising:
forming a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer; and
forming a gate electrode on the gate insulator layer.
12. The method of claim 1 1 , further comprising:
forming a drain ohmic contact on a second side of the substrate, the second side facing opposite to the first side; and
forming source ohmic contacts contacting the source layer and the first base layer.
13. The method of claim 10, wherein the first base layer comprises aluminum gallium nitride.
14. The method of claim 13, wherein the forming of the first base layer comprises grading a composition of aluminum such that a greatest composition of aluminum is at a boundary with the drift layer and a least composition of aluminum is proximal to the source layer.
15. The method of claim 14, wherein the greatest composition of aluminum is at least 70% of the molar composition of aluminum and gallium in the first base layer.
16. The method of claim 13, further comprising forming a p-type gallium nitride second base layer between the first base layer and the source layer.
17. The method of claim 10, wherein the forming of the first base layer comprises:
selectively etching the drift layer; and
regrowing the first base layer in the selectively etched drift layer.
18. The method of claim 17, wherein the regrowing of the first base layer in the selectively etched drift layer comprises:
regrowing an n-type Ill-nitride layer in the selectively etched drift layer; and regrowing the first base layer on the regrown n-type Ill-nitride layer.
19. The method of claim 17, wherein the forming of the source layer comprises:
selectively etching the first base layer; and
regrowing the source layer in the selectively etched first base layer.
20. The method of claim 10, further comprising regrowing a dielectric gate insulator layer on the source layer, the first base layer, and the drift layer.
21 . The method of claim 20, further comprising:
selectively etching the gate insulator layer;
forming source ohmic contacts contacting the source layer, the first base layer, and the selectively etched gate insulator layer; and
forming a gate electrode on the gate insulator layer.
PCT/US2017/049625 2016-09-01 2017-08-31 Normally-off gallium oxide based vertical transistors with p-type algan blocking layers WO2018045175A1 (en)

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109904239A (en) * 2019-03-19 2019-06-18 南方科技大学 A kind of PIN diode and preparation method thereof
CN109920857A (en) * 2019-03-19 2019-06-21 南方科技大学 A kind of Schottky diode and preparation method thereof
CN110120425A (en) * 2019-05-22 2019-08-13 西安电子科技大学 The high-voltage MOSFET device and production method of vertical-type
CN110164976A (en) * 2019-05-22 2019-08-23 西安电子科技大学 Strain type gallium oxide MOSFET element structure and preparation method
WO2019191465A1 (en) * 2018-03-28 2019-10-03 Cornell University VERTICAL GALLIUM OXIDE (Ga2O3) POWER FETS
CN111696698A (en) * 2020-06-22 2020-09-22 厦门理工学院 Gallium oxide Schottky isotope battery and preparation method thereof
CN111785776A (en) * 2020-07-16 2020-10-16 西安电子科技大学 Vertical structure Ga2O3Preparation method of metal oxide semiconductor field effect transistor
WO2021176833A1 (en) * 2020-03-03 2021-09-10 ローム株式会社 Semiconductor device, semicnductor package comprising same, and method for producing semiconductor device
CN113555286A (en) * 2021-07-05 2021-10-26 浙江芯国半导体有限公司 Gallium oxide super-junction Schottky diode and preparation method thereof
CN113555442A (en) * 2021-07-05 2021-10-26 浙江芯国半导体有限公司 Three-gate Ga2O3Transverse MOSFET power device and preparation method thereof
DE102020215006A1 (en) 2020-11-30 2022-06-02 Robert Bosch Gesellschaft mit beschränkter Haftung Vertical power semiconductor device and method for manufacturing a vertical power semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080197405A1 (en) * 2007-02-21 2008-08-21 Infineon Technologies Ag Trench diffusion isolation in power transistors
US20100123167A1 (en) * 2008-11-17 2010-05-20 Yong Tae Moon Method for manufacturing gallium oxide based substrate, light emitting device, and method for manufacturing the light emitting device
US20140217405A1 (en) * 2011-09-08 2014-08-07 Tamura Corporation Ga2O3 SEMICONDUCTOR ELEMENT
US8957462B2 (en) * 2010-12-09 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an N-type transistor with an N-type semiconductor containing nitrogen as a gate
US9245749B2 (en) * 2013-12-24 2016-01-26 Tamura Corporation Method of forming Ga2O3-based crystal film and crystal multilayer structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080197405A1 (en) * 2007-02-21 2008-08-21 Infineon Technologies Ag Trench diffusion isolation in power transistors
US20100123167A1 (en) * 2008-11-17 2010-05-20 Yong Tae Moon Method for manufacturing gallium oxide based substrate, light emitting device, and method for manufacturing the light emitting device
US8957462B2 (en) * 2010-12-09 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an N-type transistor with an N-type semiconductor containing nitrogen as a gate
US20140217405A1 (en) * 2011-09-08 2014-08-07 Tamura Corporation Ga2O3 SEMICONDUCTOR ELEMENT
US9245749B2 (en) * 2013-12-24 2016-01-26 Tamura Corporation Method of forming Ga2O3-based crystal film and crystal multilayer structure

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019191465A1 (en) * 2018-03-28 2019-10-03 Cornell University VERTICAL GALLIUM OXIDE (Ga2O3) POWER FETS
US11715774B2 (en) 2018-03-28 2023-08-01 Cornell University Vertical gallium oxide (GA2O3) power FETs
CN109920857B (en) * 2019-03-19 2021-11-30 珠海镓未来科技有限公司 Schottky diode and preparation method thereof
CN109904239A (en) * 2019-03-19 2019-06-18 南方科技大学 A kind of PIN diode and preparation method thereof
CN109920857A (en) * 2019-03-19 2019-06-21 南方科技大学 A kind of Schottky diode and preparation method thereof
CN110164976B (en) * 2019-05-22 2020-09-08 西安电子科技大学 Strain gallium oxide MOSFET device structure and preparation method
CN110164976A (en) * 2019-05-22 2019-08-23 西安电子科技大学 Strain type gallium oxide MOSFET element structure and preparation method
CN110120425B (en) * 2019-05-22 2020-08-11 西安电子科技大学 Vertical high-voltage MOSFET device and manufacturing method
CN110120425A (en) * 2019-05-22 2019-08-13 西安电子科技大学 The high-voltage MOSFET device and production method of vertical-type
WO2021176833A1 (en) * 2020-03-03 2021-09-10 ローム株式会社 Semiconductor device, semicnductor package comprising same, and method for producing semiconductor device
CN111696698A (en) * 2020-06-22 2020-09-22 厦门理工学院 Gallium oxide Schottky isotope battery and preparation method thereof
CN111785776A (en) * 2020-07-16 2020-10-16 西安电子科技大学 Vertical structure Ga2O3Preparation method of metal oxide semiconductor field effect transistor
CN111785776B (en) * 2020-07-16 2022-06-03 西安电子科技大学 Vertical structure Ga2O3Preparation method of metal oxide semiconductor field effect transistor
DE102020215006A1 (en) 2020-11-30 2022-06-02 Robert Bosch Gesellschaft mit beschränkter Haftung Vertical power semiconductor device and method for manufacturing a vertical power semiconductor device
CN113555286A (en) * 2021-07-05 2021-10-26 浙江芯国半导体有限公司 Gallium oxide super-junction Schottky diode and preparation method thereof
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CN113555286B (en) * 2021-07-05 2023-12-05 浙江芯科半导体有限公司 Gallium oxide super junction Schottky diode and preparation method thereof

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