CN113555442A - Three-gate Ga2O3Transverse MOSFET power device and preparation method thereof - Google Patents
Three-gate Ga2O3Transverse MOSFET power device and preparation method thereof Download PDFInfo
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- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims abstract description 75
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Abstract
The invention discloses a tri-gate Ga2O3Lateral MOSFET power device and method of making the same, the device comprising Ga2O3Substrate, Ga2O3An epitaxial layer, two P-type well regions, a P-type control region, an n + type source region, a channel region, a grid, a source electrode and a drain electrode, wherein Ga2O3A substrate groove is arranged on the substrate, Ga2O3The epitaxial layer is arranged in the substrate groove;two P-type well regions and P-type control regions are respectively arranged in Ga2O3The upper surface of the epitaxial layer, the P-type control region is arranged between the two P-type well regions, and the n + type source region and the channel region are distributed on the upper surface of the P-type well region at intervals; the grid electrode comprises a top grid and two side grids, the two side grids are respectively arranged at two sides of the channel region, the top grid is arranged above the channel region, and two ends of the top grid are respectively contacted with the two side grids; the drain electrode is arranged on Ga2O3The lower surface of the substrate and the source electrode cover the upper surface of the whole device. The invention adopts heavily doped N-type Ga2O3As the substrate, the high-power semiconductor device has better thermal stability, and can obviously improve the power borne by the device and the operating temperature.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a tri-gate Ga2O3A lateral MOSFET power device and a method for manufacturing the same are provided.
Background
SiC is the most advantageous semiconductor material for manufacturing high-temperature, high-power electronic devices due to its excellent physicochemical and electrical properties, and has a power device quality factor much greater than that of Si materials. The development of Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs) of SiC power devices began in the 90 th 20 th century, and the MOSFETs have a series of advantages such as high input impedance, fast switching speed, high operating frequency, high temperature and high voltage resistance, and have been widely used in switching regulated power supplies, high frequency heating, automotive electronics, power amplifiers, and the like.
In order to realize higher application reliability, from the perspective of device technology, SiC materials have technical and economic problems of more defects, lower channel mobility, higher cost, and the like, which severely restricts the development of SiC power devices.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a tri-gate Ga2O3A lateral MOSFET power device and a method for manufacturing the same are provided. The technical problem to be solved by the invention is realized by the following technical scheme:
one aspect of the present invention provides a tri-gate Ga2O3Lateral MOSFET power devices comprising Ga2O3Substrate, Ga2O3An epitaxial layer, two P-type well regions, a P-type control region, an n + type source region, a channel region, a gate, a source and a drain, wherein,
the Ga is2O3A substrate groove is arranged on the substrate, and the Ga2O3The epitaxial layer is arranged in the substrate groove;
the two P-type well regions and the P-type control region are respectively arranged in the Ga2O3The P-type control region is arranged between the two P-type well regions, and the n + type source region and the channel region are distributed on the upper surface of the P-type well region at intervals;
the grid electrode comprises a top grid and two side grids, the two side grids are respectively arranged at two sides of the channel region, the top grid is arranged above the channel region, the lower surfaces at two ends of the top grid are respectively contacted with the upper surfaces of the two side grids, the channel region is separated from the top grid and the two side grids through a high-k dielectric layer, and the high-k dielectric layer is respectively arranged at the outer sides of the two side grids so as to be in contact with the n + type source region or the Ga + type source region2O3The epitaxial layers are spaced apart;
the drain electrode is arranged on the Ga2O3A lower surface of the substrate, and the drain electrode and the Ga2O3And an ohmic contact metal layer is also arranged between the substrates, and the source electrode covers the upper surface of the whole device and is separated from the grid electrode through the high-k dielectric layer.
In one embodiment of the invention, one end of the top gate in the horizontal direction is located above the n + type source region, and the other end extends to above a region between the P-type control region and the P-type well region.
In one embodiment of the present invention, the Ga is2O3The substrate is heavily doped N-type Ga2O3Substrate with doping concentration greater than 1 × 1019cm-3。
In one embodiment of the invention, the doping concentration of the n + type source region is more than 1 × 1019cm-3。
In one embodiment of the invention, the material of the high-K dielectric layer is Si3N4、Al2O3、SiO2、HfO2And HfSiO.
In one embodiment of the present invention, the doping concentration of the P-type control region is higher than that of the P-type well region.
Another aspect of the invention provides a tri-gate Ga2O3Method for manufacturing a lateral MOSFET power device for manufacturing a tri-gate Ga as described in any of the above embodiments2O3The preparation method of the lateral MOSFET power device comprises the following steps:
s1: selecting Ga2O3A substrate and in said Ga2O3Forming a substrate groove on the substrate;
s2: growing Ga in the cleaned substrate groove2O3An epitaxial layer;
s3: in the Ga2O3A plurality of P-type well regions are formed on the upper surface of the epitaxial layer;
s4: forming a P-type control region between two adjacent P-type well regions;
s5: growing an n + type source region above the P type well region;
s6: forming a grid electrode above the P-type well region, wherein the grid electrode is of a tri-grid structure consisting of a top grid and two side grids;
s7: in the Ga2O3Depositing an ohmic contact metal layer on the lower surface of the substrate, and annealing to form ohmic contact;
s8: forming a drain electrode on the ohmic contact metal layer;
s9: a source is formed on the upper surface of the device.
In an embodiment of the present invention, the S6 includes:
s61: forming a dielectric groove on the P-type well region and on the inner side of the n + type source region;
s62: and depositing a triple-gate structure wrapped with a high-K medium in the medium groove.
In an embodiment of the present invention, two side gates are respectively disposed at two sides of a channel region located in the middle of the dielectric trench, the top gate is disposed above the channel region, lower surfaces at two ends of the top gate are respectively in contact with upper surfaces of the two side gates, the channel region is separated from the top gate and the two side gates by a high-k dielectric layer, the high-k dielectric layer is respectively disposed at outer sides of the two side gates to be in contact with the n + -type source region or the Ga + -type source region2O3The epitaxial layers are spaced apart.
In an embodiment of the present invention, the S7 includes:
in the Ga2O3Depositing a carbon layer of 1-50nm and a nickel layer of 10-500nm on the lower surface of the substrate in sequence, and then realizing ohmic contact by annealing at the temperature of 700-950 ℃.
Compared with the prior art, the invention has the beneficial effects that:
1. triple gate Ga of the invention2O3The transverse MOSFET power device adopts heavily doped N-type Ga2O3As a substrate, Ga2O3The high-power semiconductor device can bear higher temperature, has better thermal stability, can obviously improve the power borne by the device and the operating temperature, and has stronger stability; in addition, Ga is compared with the conventional 4H-SiC substrate material2O3The Baliga quality factor (Baliga quality factor) is more than 8 times of that of 4H-SiC, and the manufacturing method is more convenient, so that the problems of higher economic cost and low channel mobility of a device made of 4H-SiC material are solved, the channel mobility is improved, and the power consumption of the device is obviously reduced.
2. Triple gate Ga of the invention2O3The transverse MOSFET power device utilizes the highly doped P-type control region to reduce the electric field of the gate oxide and effectively reduce the saturation current density under high drain-source voltage, thereby improving the short circuit tolerance of the device and the reliability of the device.
3. By optimizing the distance between the split gate electrode and the P-type control region positioned between the split gate electrodes, the gate-drain capacitance of the device is reduced, and the conduction loss of the device under low drain-source voltage is reduced.
4. The invention adoptsWith lattice constants less than Ga2O3The GaN material is used as a source region and can pass through GaN and Ga2O3The lattice mismatch between the two leads in tensile stress in the horizontal direction in the conductive channel, so that the energy band structure of the gallium oxide material in the conductive channel is changed, the mobility of electrons in the conductive channel is improved, and the device has larger output current.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic cross-sectional view of a tri-gate Ga2O3 lateral MOSFET power device according to an embodiment of the present invention;
fig. 2 is a partial top view of a tri-gate Ga2O3 lateral MOSFET power device according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing a tri-gate Ga2O3 lateral MOSFET power device according to an embodiment of the present invention.
Description of reference numerals:
1-Ga2O3a substrate; 2-Ga2O3An epitaxial layer; a 3-P type well region; a 4-P type control region; a 5-n + type source region; 6-a channel region; 7-a grid; 71-top gate; 72-side gates; an 8-source electrode; 9-a drain electrode; a 10-high k dielectric layer.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, a tri-gate Ga according to the present invention is provided in the following with reference to the accompanying drawings and the detailed description2O3A lateral MOSFET power device and a method for fabricating the same are described in detail.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element.
Example one
Referring to fig. 1 and 2, fig. 1 shows a triple-gate Ga according to an embodiment of the present invention2O3A cross-sectional schematic of a lateral MOSFET power device; FIG. 2 shows a triple-gate Ga according to an embodiment of the present invention2O3Partial top view of lateral MOSFET power devices. The triple-gate Ga2O3Lateral MOSFET power devices comprising Ga2O3Substrate 1, Ga2O3 Epitaxial layer 2, two P type well regions 3, P type control region 4, n + type source region 5, channel region 6, gate 7, source 8 and drain 9. In this embodiment, heavily doped N-type Ga is selected2O3The material is used as substrate and has doping concentration greater than 1 × 1019cm-3。Ga2O3A substrate groove is arranged on the substrate 1, Ga2O3An epitaxial layer 2 is arranged in the substrate recess. In this example, Ga2O3The height of the epitaxial layer 2 is equal to the depth of the substrate recess, Ga2O3The epitaxial layer 2 is N-type lightly doped with a doping concentration of 1 × 1014-1×1017cm-3。
Further, two P-type well regions 3 and P-type control regions 4 are provided in Ga2O3The upper surface of epitaxial layer 2, and P type control region 4 sets up between two P type well regions 3, and two P type well regions 3 are about the axis symmetry of P type control region 4. In this embodiment, the doping concentration of the P-type control region 4 is higher than that of the P-type well region3, the doping concentration of the P-type well region 3 is gradually increased from top to bottom, and preferably, the doping concentration of the upper surface of the P-type well region 3 is 1 × 1016cm-3-5×1017cm-3The doping concentration of the lower surface of the P-type well region 3 is 5 multiplied by 1017cm-3-1×1019cm-3. The n + type source region 5 and the channel region 6 are distributed at intervals on the upper surface of the P-type well region 3. In the present embodiment, the thickness of the material of the n + type source region 5 is less than 500nm, and the doping concentration is greater than 1 × 1019cm-3The material is one or more of GaN, SiC and AlN.
The gate 7 of the present embodiment includes a top gate 71 and two side gates 72, the two side gates 72 are respectively disposed at two sides of the channel region 4, the top gate 71 is disposed above the channel region 6, and lower surfaces of two ends of the top gate 71 are respectively in contact with upper surfaces of the two side gates 72, so as to form an inverted U-shaped structure. The channel region 6 is separated from the top gate 71 and the two side gates 72 by the high-k dielectric layer 10, and the high-k dielectric layer 10 is arranged outside the two side gates 72 respectively to be connected with the n + type source region 5 or Ga2O3The epitaxial layers 2 are spaced apart. In other words, the top gate 71 and the side gate 72 are surrounded by the high-k dielectric layer 10 except for the surfaces that are in contact with each other.
Further, one end of the top gate 71 in the horizontal direction is located above the n + type source region 5, and the other end extends above the region between the P-type control region 4 and the P-type well region 3. That is, the inverted U-shaped structure is disposed in the dielectric trench, protrudes out of the dielectric trench, and extends to a region between the P-type control region 4 and the P-type well region 3. Preferably, the material of the gate 7 is at least one of TiN, Ni and Al, and the material of the high-K dielectric layer 10 is Si3N4、Al2O3、SiO2、HfO2And HfSiO, and the thickness of the high-k gate dielectric layer is 5-80 nm.
In this embodiment, an n + type source region 5, a channel region 6, and a gate 7 are respectively and correspondingly disposed above the two P-type well regions 3, and the formed structure is symmetric about the central axis of the P-type control region 4.
A drain electrode 6 arranged on Ga2O3The lower surface of the substrate 1, and the drain electrode 6 and Ga2O3The substrate 1 further includes an ohmic contact metal layer therebetween, and the preparation process of the ohmic contact metal layer of this embodiment is as follows: in the Ga2O3Depositing a carbon layer of 1-50nm and a nickel layer of 10-500nm on the lower surface of the substrate in sequence, and then realizing ohmic contact by annealing at the temperature of 700-950 ℃.
The source 7 overlies the upper surface of the entire device and is spaced from the gate 7 by a high-k dielectric layer 10. The source electrode and the drain electrode are made of one or more of Pt, Ti, Al, Ni and Au.
Triple gate Ga of the present embodiment2O3The transverse MOSFET power device adopts heavily doped N-type Ga2O3As a substrate, Ga2O3The high-power semiconductor device can bear higher temperature, has better thermal stability, can obviously improve the power borne by the device and the operating temperature, and has stronger stability; in addition, Ga is compared with the conventional 4H-SiC substrate material2O3The Baliga quality factor is more than 8 times of that of 4H-SiC, and the manufacturing method is more convenient, so the problems of higher economic cost and low channel mobility of a device made of 4H-SiC material are solved, the channel mobility is improved, and the power consumption of the device is obviously reduced. The triple-gate Ga2O3The transverse MOSFET power device utilizes the highly doped P-type control region to reduce the electric field of the gate oxide and effectively reduce the saturation current density under high drain-source voltage, thereby improving the short circuit tolerance of the device and the reliability of the device. In addition, the distance between the split gate electrode and the P-type control region positioned between the split gate electrodes is optimized, so that the gate-drain capacitance of the device is reduced, and the conduction loss of the device under low drain-source voltage is reduced.
Example two
On the basis of the above embodiments, the present embodiment provides a tri-gate Ga2O3A method for manufacturing a lateral MOSFET power device. Referring to fig. 3, fig. 3 is a schematic view of a triple-gate Ga according to an embodiment of the present invention2O3A flow chart of a preparation method of a transverse MOSFET power device. The preparation method comprises the following steps:
s1: selecting Ga2O3A substrate and in said Ga2O3Formation on a substrateAnd (6) substrate grooves.
Specifically, heavily doped N-type Ga is selected2O3The material is used as a substrate, and the Ga is etched by using an etching process2O3Forming a substrate groove on the upper surface of the substrate, cleaning the substrate, specifically cleaning the substrate with acetone and isopropanol solutions for 30-60s respectively, washing the substrate with deionized water, and finally blowing the substrate with high-purity nitrogen.
Preferably, Ga2O3The doping concentration of the substrate is 1 x 1016-1×1021cm-3The thickness is 200-400 μm.
S2: growing Ga in the cleaned substrate groove2O3An epitaxial layer.
Specifically, the cleaned Ga is2O3The substrate was placed in an MOCVD (Metal organic chemical vapor deposition) apparatus at a TMGa (trimethyl gallium) flow rate of 6.0X 10-6mol/min，O2Flow 2.2X 10-2Growing Ga in the substrate groove under the process conditions of mol/min, 850 ℃ and 500Pa pressure2O3An epitaxial layer.
In this example, Ga is grown2O3The epitaxial layer is N-type lightly doped with a doping concentration of 1 × 1014-1×1017cm-3The thickness is 5-30 μm.
Then to Ga-containing2O3Cleaning the substrate of the epitaxial layer, wherein the cleaning process in the step comprises the following steps: standard RCA cleaning; for Ga2O3And carrying out high-temperature oxidation on the epitaxial wafer to form a sacrificial oxide layer, and then corroding the sacrificial oxide layer until the surface oxide layer is completely removed.
S3: in the Ga2O3A plurality of P-type well regions are formed on the upper surface of the epitaxial layer.
Specifically, Ga after washing2O3And forming a plurality of P-type well regions on two sides of the upper surface of the epitaxial layer by adopting an ion implantation method. The doping concentration of the formed P-type well region is gradually increased from top to bottom, and in this embodiment, the doping concentration of the upper surface of the P-type well region is 1 × 1016cm-3-5×1017cm-3Lower surface of P-type well regionHas a doping concentration of 5X 1017cm-3-1×1019cm-3。
S4: and a P-type control region is formed between two adjacent P-type well regions.
In particular, Ga between two adjacent P well regions2O3And forming a P-type control region on the upper surface of the epitaxial layer by adopting a nitrogen ion implantation method.
In this embodiment, the doping concentration of the P-type control region is higher than that of the P-well region, so as to form a highly doped control region.
S5: and growing an n + type source region above the P type well region.
Specifically, photoetching is carried out on the cleaned sample wafer, a source region groove is formed above the P-type well region and is used for forming a source region in the groove subsequently, and then the source region is placed into reactive ion etching equipment, wherein the gas flow is Cl2：BCl3Etching to remove Ga in the area under the process conditions of 10:10sccm, RF power of 200W and pressure of 10mTorr2O3And putting the etched sample wafer into H2O2:H2SO4Washing in a solution with the ratio of 1:3 for 1min, washing with deionized water, and finally blowing with high-purity nitrogen.
Putting the cleaned sample wafer into PECVD (plasma enhanced chemical vapor deposition) equipment and adding NH3Flow rate 160sccm, SiH4Growing a silicon nitride mask for 30min under the process conditions that the flow is 80scccm, the pressure is 800mTorr and the radio frequency power is 20W; photoetching the sample wafer after mask growth, and placing the sample wafer into reactive ion etching equipment with gas flow of CH3F：O2Etching under the process conditions of 25:40sccm, the radio frequency power bit of 150W and the pressure of 67Pa to remove the silicon nitride mask of the source region; putting the etched sample wafer into H2O2:H2SO4Cleaning in a solution with the ratio of 1:3, washing with flowing deionized water, and finally drying by using high-purity nitrogen; putting the cleaned sample wafer into an MBE (molecular beam epitaxy) device, and adding NH3The GaN grows under the process conditions that the flow is 50sccm, the Si source temperature is 1240 ℃ and the growth cavity temperature is 700 DEG CAn epitaxial layer; photoetching the sample wafer after epitaxial growth, and placing the sample wafer into etching equipment with gas flow of CH3F：O2Etching under the process conditions of 25:40sccm, the radio frequency power of 150W and the pressure of 67Pa to remove the silicon nitride mask;
and cleaning the etched sample wafer for 3min by using TMAH solution at the temperature of 90 ℃, cleaning by using flowing deionized water, blow-drying by using high-purity nitrogen, and then photoetching to form the heavily doped source region.
Forming a mask layer on the upper surface of the epitaxial layer by adopting a chemical vapor deposition or physical vapor deposition method; forming an n + type source region between two adjacent P well regions by using the mask layer as a mask through an ion implantation method; the ions injected by the ion injection in the step are N ions, P ions or Al ions.
S6: forming a gate over the P-well region.
It must be noted that a dielectric trench is formed in the P-well region, inside which a gate electrode is deposited that encapsulates the high-K dielectric. In this embodiment, a thin film deposition technique is adopted to deposit a gate electrode with a preset thickness on the high-K dielectric layer, and then the gate electrode is split by an etching method, wherein one end of the gate electrode is located on the n + type source region, and the other end of the gate electrode is located above a region between the P-type control region and the P-well region, and is not crossed with the P-type control region; and then, depositing a high-k gate dielectric layer in the source region except for the junction of the side gate and the top gate.
S7: in the Ga2O3And depositing an ohmic contact metal layer on the lower surface of the substrate, and annealing to form ohmic contact.
In particular, heavily doped N-type Ga2O3And depositing a low-temperature ohmic contact metal layer at the bottom of the substrate, and annealing to form ohmic contact. Specifically, sequentially depositing a carbon layer with the thickness of 1-50nm and a nickel layer with the thickness of 10-500nm, and realizing ohmic contact through annealing, wherein the deposition method comprises chemical vapor deposition, magnetron sputtering or electron beam evaporation, and the annealing temperature is 700-950 ℃. It should be noted that the method for forming a thick drain electrode of ohmic contact in this step is actually because the SiC/Ni structure needs to be subjected to high temperature in the conventional silicon carbide ohmic contact manufacturing processRapid annealing of [ 1000℃ ]]Such high temperature may cause crystallization of the high-k gate dielectric, resulting in large leakage current. Therefore, the embodiment reduces the schottky barrier height between metal semiconductors by introducing carbon into the nickel-based ohmic contact, and realizes the preparation of the ohmic contact under the relatively low-temperature annealing condition.
S8: and forming a drain electrode on the low-temperature ohmic contact metal layer.
Specifically, metal is continuously deposited on the lower surface of the low-temperature ohmic contact metal layer, and the optional deposition method is magnetron sputtering or electron beam evaporation. In this step, the metal is any one of Ti, Al, and Ni or a stacked metal thereof, and a drain electrode having a thickness of about 50nm is formed on the back surface of the substrate.
S9: and forming a source electrode on the upper surface of the device.
Specifically, a plurality of layers of metals such as nickel (Ni), titanium (Ti), aluminum (Al), and the like are sequentially deposited over the entire sample wafer by a thin film deposition method such as electron beam evaporation or sputtering, and a source electrode is formed by patterning.
In the preparation method of the tri-gate Ga2O3 lateral MOSFET power device in the embodiment, the heavily doped N-type Ga2O3 is used as the substrate, and Ga2O3 can bear higher temperature, has better thermal stability, can significantly improve the power borne by the device and the operating temperature, and has stronger stability; by introducing carbon into the nickel-based ohmic contact, the Schottky barrier height between metal semiconductors is reduced, and the ohmic contact is prepared under the relatively low-temperature annealing condition. In addition, a lattice constant smaller than Ga is used2O3The GaN material is used as a source region and can pass through GaN and Ga2O3The lattice mismatch between the two leads in tensile stress in the horizontal direction in the conductive channel, so that the energy band structure of the gallium oxide material in the conductive channel is changed, the mobility of electrons in the conductive channel is improved, and the device has larger output current.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. Three-gate Ga2O3Lateral MOSFET power device, characterized in that it comprises Ga2O3Substrate (1), Ga2O3An epitaxial layer (2), two P-type well regions (3), a P-type control region (4), an n + -type source region (5), a channel region (6), a gate (7), a source (8) and a drain (9), wherein,
the Ga is2O3A substrate groove is arranged on the substrate (1), and the Ga2O3The epitaxial layer (2) is arranged in the substrate groove;
the two P-type well regions (3) and the P-type control region (4) are respectively arranged in the Ga2O3The upper surface of the epitaxial layer (2), the P-type control region (4) is arranged between the two P-type well regions (3), and the n + type source region (5) and the channel region (6) are distributed on the upper surface of the P-type well region (3) at intervals;
the grid (7) comprises a top grid (71) and two side grids (72), the two side grids (72) are arranged on two sides of the channel region (4) respectively, the top grid (71) is arranged above the channel region (6), lower surfaces of two ends of the top grid (71) are in contact with upper surfaces of the two side grids (72) respectively, the channel region (6) is separated from the top grid (71) and the two side grids (72) through a high-k dielectric layer (10), and the outer sides of the two side grids (72) are provided with the high-k dielectric layer (10) respectively so as to be in contact with the n + type source region (5) or the Ga + type source region2O3The epitaxial layers (2) are spaced apart;
the drain electrode (6) is arranged on the Ga2O3A lower surface of the substrate (1), and the drain electrode (6) and the Ga2O3An ohmic contact metal layer is further arranged between the substrates (1), the source electrode (7) covers the upper surface of the whole device and is separated from the grid electrode (7) through the high-k dielectric layer (10).
2. Triple-gate Ga according to claim 12O3Lateral MOSFET power devices characterized byOne end of the top gate (71) in the horizontal direction is positioned above the n + type source region (5), and the other end of the top gate extends to the upper part of the region between the P-type control region (4) and the P-type well region (3).
3. Triple-gate Ga according to claim 12O3Lateral MOSFET power device, characterized in that said Ga2O3The substrate (1) is heavily doped N-type Ga2O3Substrate with doping concentration greater than 1 × 1019cm-3。
4. Triple-gate Ga according to claim 12O3Lateral MOSFET power device, characterized in that the doping concentration of the n + -type source region (5) is larger than 1 x 1019cm-3。
5. Triple-gate Ga according to claim 12O3The transverse MOSFET power device is characterized in that the material of the high-K dielectric layer (10) is Si3N4、Al2O3、SiO2、HfO2And HfSiO.
6. Triple-gate Ga according to claim 12O3Lateral MOSFET power device, characterized in that the doping concentration of the P-type control region (4) is higher than the doping concentration of the P-type well region (3).
7. Three-gate Ga2O3Method for the production of a lateral MOSFET power device, characterized in that it is used for the production of a tri-gate Ga as claimed in any one of claims 1 to 62O3The preparation method of the lateral MOSFET power device comprises the following steps:
s1: selecting Ga2O3A substrate and in said Ga2O3Forming a substrate groove on the substrate;
s2: growing Ga in the cleaned substrate groove2O3An epitaxial layer;
s3: in the Ga2O3A plurality of P-type well regions are formed on the upper surface of the epitaxial layer;
s4: forming a P-type control region between two adjacent P-type well regions;
s5: growing an n + type source region above the P type well region;
s6: forming a grid electrode above the P-type well region, wherein the grid electrode is of a tri-grid structure consisting of a top grid and two side grids;
s7: in the Ga2O3Depositing an ohmic contact metal layer on the lower surface of the substrate, and annealing to form ohmic contact;
s8: forming a drain electrode on the ohmic contact metal layer;
s9: a source is formed on the upper surface of the device.
8. Triple-gate Ga according to claim 72O3The method for manufacturing a lateral MOSFET power device, wherein the S6 includes:
s61: forming a dielectric groove on the P-type well region and on the inner side of the n + type source region;
s62: and depositing a triple-gate structure wrapped with a high-K medium in the medium groove.
9. Triple-gate Ga according to claim 82O3The preparation method of the transverse MOSFET power device is characterized in that two side gates are respectively arranged at two sides of a channel region positioned in the middle of the dielectric groove, the top gate is arranged above the channel region, the lower surfaces of two ends of the top gate are respectively contacted with the upper surfaces of the two side gates, the channel region is separated from the top gate and the two side gates through a high-k dielectric layer, and the high-k dielectric layer is respectively arranged at the outer sides of the two side gates to be separated from the n + type source region or the Ga + type source region2O3The epitaxial layers are spaced apart.
10. Triple gate Ga according to any one of claims 7 to 92O3The method for manufacturing a lateral MOSFET power device, wherein the S7 includes:
in the Ga2O3Depositing a carbon layer of 1-50nm and a nickel layer of 10-500nm on the lower surface of the substrate in sequence, and then realizing ohmic contact by annealing at the temperature of 700-950 ℃.
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