CN114823891A - GaN-based double-layer passivated groove gate enhanced MIS-HEMT device and preparation method thereof - Google Patents
GaN-based double-layer passivated groove gate enhanced MIS-HEMT device and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device and a preparation method thereof, wherein the device comprises a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, wherein a first isolation region and a second isolation region are respectively arranged on two sides of the barrier layer; the inner sides of the first isolation region and the second isolation region are respectively provided with a drain electrode and a source electrode, at least one part of the drain electrode and at least one part of the source electrode are embedded in the barrier layer, and the lower surfaces of the drain electrode and the source electrode are both contacted with the channel layer; a gate region groove is formed in the barrier layer between the drain electrode and the source electrode, and a double-layer passivation layer is coated on the inner surface of the gate region groove and the upper surface of the barrier layer; and a gate electrode is arranged on the double-layer passivation layer positioned in the groove of the gate region. According to the invention, the double-layer passivation layer forms the insulating layer in the direction vertical to the channel, so that the transport of current carriers in the vertical direction is blocked, and the device has the characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a GaN-based double-layer passivated groove gate enhanced MIS-HEMT device and a preparation method thereof.
Background
An AlGaN/GaN-based High Electron Mobility Transistor (HEMT) has excellent characteristics of High temperature resistance and High voltage resistance, and is widely used in the fields of power electronics, wireless communication, and radio frequency. With the continuous improvement of the requirements of various application fields on the performance of devices, the reliability of the AlGaN/GaN-based HEMT device still has some gate electrodes to be solved urgently.
The gate electrode of the conventional GaN-based schottky HEMT has a serious leakage current, and due to the existence of a large number of dislocations and defects in the GaN material itself, charges are recombined by a surface state, thereby causing a serious current collapse phenomenon. To solve this problem, it has been proposed to use Al 2 O 3 、SiN 4 And MIS (metal-insulator-semiconductor) -HEMT method using a dielectric passivation layer such as SiO2 as a gate insulation layer, although the leakage of the gate electrode of the device is suppressed to a certain extent and the current collapse problem is improved, the insulation layer dielectric below the gate electrode also causes the device to have a certain reliability problem, which leads to the reduction of the current cut-off frequency of the device and the increase of the PBTI (positive bias temperature instability) effect, thus limiting the wide application of the GaN-based MIS-HEMT device.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a GaN-based double-layer passivated groove gate enhanced MIS-HEMT device and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
one aspect of the invention provides a GaN-based double-layer passivated notch gate enhanced MIS-HEMT device, which comprises a substrate, a nucleating layer, a buffer layer, a channel layer and a barrier layer which are arranged from bottom to top in sequence, wherein,
a first isolation region and a second isolation region are respectively arranged on two sides of the barrier layer, and extend from the upper surface of the barrier layer to the upper surface of the buffer layer;
a drain electrode and a source electrode are respectively arranged on the inner sides of the first isolation region and the second isolation region, at least one part of the drain electrode and at least one part of the source electrode are embedded in the barrier layer, and the lower surfaces of the drain electrode and the source electrode are in contact with the channel layer and form ohmic contact;
a gate region groove is formed in the barrier layer between the drain electrode and the source electrode, and the inner surface of the gate region groove and the upper surface of the barrier layer are coated with a double-layer passivation layer; and a gate electrode is arranged on the double-layer passivation layer positioned in the gate region groove.
In one embodiment of the invention, the bi-layer passivation layer comprises a Si passivation layer and SiO 2 A passivation layer, wherein,
the Si passivation layer is positioned in the gate region groove and grows outwards along the table top of the gate region groove, so that the cross section is U-shaped;
the SiO 2 The passivation layer covers the upper surface of the Si passivation layer and the upper surface of the barrier layer between the drain electrode and the source electrode, and two sides of the passivation layer are respectively contacted with the source electrode and the drain electrode.
In one embodiment of the invention, the thickness of the Si passivation layer is 1-5 nm, and the thickness of the SiO2 passivation layer is 5-100 nm.
In one embodiment of the present invention, a lower end of the gate region recess extends to an upper surface of the channel layer.
In one embodiment of the invention, the barrier layer is Al with the thickness of 10-30 nm x Ga 1-x And an N barrier layer, wherein x is 0.1 to 0.5.
In one embodiment of the invention, the nucleation layer is an AlN nucleation layer with the thickness of 50-400 nm, the buffer layer is an AlGaN buffer layer with the thickness of 200-8000 nm, and the channel layer is a GaN channel layer with the thickness of 50-500 nm.
The invention provides a preparation method of a GaN-based double-layer passivated groove gate enhanced MIS-HEMT device, which comprises the following steps:
s1: selecting a substrate and growing a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate in sequence;
s2: performing ion implantation on two sides of the barrier layer to respectively form a first isolation region and a second isolation region which extend to the upper surface of the buffer layer;
s3: etching the middle part of the upper surface of the barrier layer to form a gate region groove extending to the upper surface of the channel layer;
s4: growing a double-layer passivation layer in the gate region groove and the rest upper surface area of the barrier layer;
s5: performing gate electrode metal deposition on the double-layer passivation layer above the gate region groove to form a gate electrode;
s6: and respectively forming a source electrode and a drain electrode on two sides of the gate electrode, wherein the lower surface of the source electrode and the lower surface of the drain electrode are both in contact with the upper surface of the channel layer.
In an embodiment of the present invention, the S1 includes:
s11: selecting a Si, SiC or sapphire substrate, and carrying out plasma cleaning and surface pretreatment on the surface of the substrate to keep the surface of the substrate clean;
s12: an AlN nucleating layer with the thickness of 50-500 nm, an AlGaN buffer layer with the thickness of 200-8000 nm, an intrinsic GaN channel layer with the thickness of 50-500 nm and Al with the thickness of 10-30 nm are epitaxially grown on the substrate in sequence x Ga 1-x And an N barrier layer, wherein x is 0.1 to 0.5.
In an embodiment of the present invention, the S4 includes:
s41: growing a 1-5 nm Si passivation layer on the upper surface of the barrier layer and in the gate region groove by using a CVD (chemical vapor deposition) technology;
s42: etching away the Si passivation layer on the surface of the barrier layer far away from the gate region groove to form the Si passivation layer which is positioned in the gate region groove and has a U-shaped section;
s43: depositing a layer of 5-100 nm SiO on the upper surfaces of the Si passivation layer and the barrier layer by using a PECVD (plasma enhanced chemical vapor deposition) process 2 Formation of SiO 2 And a passivation layer.
In an embodiment of the present invention, the S6 includes:
s61: respectively etching a source electrode region groove and a drain electrode region groove which extend to the upper surface of the channel layer on two sides of the gate electrode by utilizing a photoetching process;
s62: and performing metal deposition on the source region groove and the drain region groove by using a sputtering or electron beam evaporation process, and then performing a stripping process and annealing to form a source electrode and a drain electrode.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention provides a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device which comprises a substrate, a nucleation layer, a buffer layer, a device isolation region, a channel layer, a barrier layer, a double-layer passivation layer, a gate electrode, a source electrode and a drain electrode, wherein the double-layer passivation layer consists of a Si passivation layer and a SiO2 passivation layer, a groove of a gate region is arranged on the side, close to the source electrode, of the barrier layer, the Si passivation layer grows in the groove and grows outwards along the groove table surface of the barrier layer, the cross section of the Si passivation layer is U-shaped, and the SiO is in a U shape 2 The passivation layer is grown on the upper surfaces of the Si passivation layer and the barrier layer. The structure comprises a Si passivation layer and SiO layers, wherein the Si passivation layer is formed in a barrier layer groove and grows along the outer part of the barrier layer groove surface, and the SiO layers are arranged on the upper surfaces of the barrier layer and the Si passivation layer 2 And forming a double-layer passivation layer structure. According to the structure, the insulating layer is formed in the direction vertical to the channel through the double passivation layers, so that the transport of current carriers in the vertical direction is blocked, and the device has the remarkable characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.
2. The invention provides a preparation method of a GaN-based double-layer passivated groove gate enhanced MIS-HEMT device, which uses Si and SiO 2 Is a double-layer passivation layer, thereby avoiding the conventional gateThe electrode insulating layer has the problems of high surface trap concentration, reduced device output current, current collapse effect and the like caused by a series of interface state problems, and the withstand voltage of the gate electrode and the reliability of the device are effectively improved.
3. The invention provides a preparation method of a GaN-based double-layer passivated groove gate enhanced MIS-HEMT device, which comprises the following steps of forming a Si passivation layer and a SiO 2 The double-layer passivation structure of the passivation layer enables the surface state of the passivation layer to be reduced, and the passivation effect is better than that of a HEMT structure without the passivation layer and a single-layer passivation layer structure.
4. The invention has simple process and is compatible with the traditional GaN HEMT process.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a GaN-based double-layer passivated notch-gate enhanced MIS-HEMT device according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for manufacturing a GaN-based double-layer passivated notch gate enhanced MIS-HEMT device according to an embodiment of the invention;
fig. 3a to fig. 3h are schematic diagrams illustrating a process of manufacturing a GaN-based double-layer passivated notch-gate enhanced MIS-HEMT device according to an embodiment of the present invention.
Description of reference numerals:
1-a substrate; 2-a nucleation layer; 3-a buffer layer; 4-a channel layer; 5-a first isolation region; 6-barrier layer; 7-a drain electrode; 8-a gate electrode; 9-a source electrode; 10-a double passivation layer; 101-Si passivation layer; 102-SiO2 passivation layer; 11-a second isolation region; 12-gate region recess.
Detailed Description
In order to further illustrate the technical means and effects of the present invention adopted to achieve the predetermined invention purpose, the following detailed description is made with reference to the accompanying drawings and the detailed description to provide a GaN-based double-layer passivated notched gate enhanced MIS-HEMT device and a method for manufacturing the same according to the present invention.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a GaN-based double-layer passivated notch-gate enhanced MIS-HEMT device according to an embodiment of the present invention. The device comprises a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4 and a barrier layer 6 which are sequentially arranged from bottom to top, wherein a first isolation region 5 and a second isolation region 11 are respectively arranged on two sides of the barrier layer 6, and the first isolation region 5 and the second isolation region 11 extend from the upper surface of the barrier layer 6 to the upper surface of the buffer layer 3; the inner sides of the first isolation region 5 and the second isolation region 11 are respectively provided with a drain electrode 7 and a source electrode 9, at least one part of the drain electrode 7 and at least one part of the source electrode 9 are embedded in the barrier layer 6, and the lower surfaces of the drain electrode 7 and the source electrode 9 are both in contact with the channel layer 4 and form ohmic contact; a gate region groove 12 is formed in the barrier layer 6 between the drain electrode 7 and the source electrode 9, and a double-layer passivation layer 10 is coated on the inner surface of the gate region groove 12 and the upper surface of the barrier layer 6; a gate electrode 8 is disposed on the bi-layer passivation layer 10 within the gate region recess 12.
In the present embodiment, the material of the substrate 1Material is n + -GaN, SiC, sapphire or Si. Furthermore, the nucleation layer 2 is an AlN nucleation layer with the thickness of 50-400 nm, the buffer layer 3 is an AlGaN buffer layer with the thickness of 200-8000 nm, the channel layer 4 is a GaN channel layer with the thickness of 50-500 nm, and the barrier layer 5 is Al with the thickness of 10-30 nm x Ga 1-x And an N barrier layer, wherein x is 0.1 to 0.5.
The first isolation region 5 and the second isolation region 11 are N ion implantation regions formed by performing N ion implantation in the barrier layer 6 and the channel layer 4. And N ions are injected into the first isolation region 5 and the second isolation region 11 to form a high-resistance region so as to realize device isolation.
Further, the bi-layer passivation layer 10 includes a Si passivation layer 101 and SiO 2 A passivation layer 102, wherein the Si passivation layer 101 is located in the gate region recess 12 and is grown outward along the mesa of the gate region recess 12 to have a U-shaped cross-section; SiO2 2 The passivation layer 102 covers the upper surface of the Si passivation layer 101 and the upper surface of the barrier layer 6 between the drain electrode 7 and the source electrode 9, and both sides thereof are in contact with the source electrode 9 and the drain electrode 7, respectively. Preferably, the thickness of the Si passivation layer 101 is 1-5 nm, and the thickness of the SiO2 passivation layer is 5-100 nm.
Further, the lower end of the gate region recess 12 extends to the upper surface of the channel layer 4. The outer side of the drain electrode 7 is in contact with the inner surface of the first isolation region 5, and the outer side of the source electrode 9 is in contact with the inner surface of the second isolation region 11. The lower surface of the drain electrode 7 forms an ohmic contact with the channel layer 4 through the barrier layer 6, and the lower surface of the source electrode 9 forms an ohmic contact with the channel layer 4 through the barrier layer 6.
Preferably, the source electrode 9, the gate electrode 8 and the drain electrode 7 are made of the same material and are a metal combination containing Ti/Al.
The embodiment of the invention provides a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device which comprises a substrate, a nucleation layer, a buffer layer, a device isolation region, a channel layer, a barrier layer, a double-layer passivation layer, a gate electrode, a source electrode and a drain electrode, wherein the double-layer passivation layer consists of a Si passivation layer and a SiO2 passivation layer, a groove of a gate region is arranged on the side, close to the source electrode, of the barrier layer, the Si passivation layer grows in the groove and grows outwards along the groove surface of the barrier layer, the cross section of the Si passivation layer is U-shaped, and the SiO is in a U shape 2 The passivation layer is grown on the upper surfaces of the Si passivation layer and the barrier layer. The structure comprises a Si passivation layer and SiO layers, wherein the Si passivation layer is formed in a barrier layer groove and grows along the outer part of the barrier layer groove surface, and the SiO layers are arranged on the upper surfaces of the barrier layer and the Si passivation layer 2 And forming a double-layer passivation layer structure. According to the structure, the insulating layer is formed in the direction vertical to the channel through the double passivation layers, so that the transport of current carriers in the vertical direction is blocked, and the device has the remarkable characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.
Example two
On the basis of the first embodiment, the present embodiment provides a method for manufacturing a GaN-based double-layer passivated notch-gate enhancement type MIS-HEMT device, please refer to fig. 2 and fig. 3a to fig. 3g, and the method includes:
s1: selecting a substrate and growing a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate in sequence.
Selecting n + A GaN, Si, SiC or sapphire substrate 1, and carrying out plasma cleaning and surface pretreatment on the surface of the substrate 1 to keep the surface of the substrate clean; then, an AlN nucleating layer 2 with the thickness of 50-500 nm, an AlGaN buffer layer 3 with the thickness of 200-8000 nm, an intrinsic GaN channel layer 4 with the thickness of 50-500 nm and Al with the thickness of 10-30 nm are epitaxially grown on the substrate 1 in sequence x Ga 1-x And an N barrier layer 6, wherein x is 0.1 to 0.5, as shown in fig. 3 a.
S2: and performing ion implantation on two sides of the barrier layer to respectively form a first isolation region and a second isolation region which extend to the upper surface of the buffer layer.
Specifically, N ions are implanted into the barrier layer 6 and the isolation region of the intrinsic GaN channel layer 4 on both sides of the upper surface of the barrier layer 6 by an ion implantation process, wherein the implantation concentration of the N ions is 10 18 ～10 20 cm -3 And high-resistance regions, namely, the first isolation region 5 and the second isolation region 11 are formed to realize device isolation, as shown in fig. 3 b.
S3: and etching the middle part of the upper surface of the barrier layer to form a gate region groove extending to the upper surface of the channel layer.
Specifically, a gate region groove 12 is formed in the gate region of the barrier layer 6 close to the second isolation region 11 by slow etching, and the gate region groove 12 extends downwards to the upper surface of the GaN channel layer 4 through the barrier layer 6, as shown in fig. 3b, the interface state phenomenon caused by etching is suppressed to a certain extent by slow etching.
S4: and growing a double-layer passivation layer in the gate region groove and the rest upper surface area of the barrier layer.
In the present embodiment, step S4 includes:
s41: and growing a 1-5 nm Si passivation layer on the upper surface of the barrier layer 6 and in the gate region groove 12 by using a CVD (chemical vapor deposition) technology.
In particular, SF is utilized 6 Cleaning the epitaxial wafer obtained in the step S3 by plasma, and introducing NH into the CVD reaction chamber 3 、SiH 4 And N 2 And depositing a layer of dense Si film with the thickness of 1-5 nm on the surface of the epitaxial wafer as a Si passivation layer 101 by using the reaction gas, as shown in FIG. 3 d.
S42: and etching away the Si passivation layer on the surface of the barrier layer away from the gate region groove at a low speed to form a U-shaped Si passivation layer 101 in the gate region groove, as shown in FIG. 3 e.
S43: depositing a layer of 5-100 nm SiO on the upper surfaces of the Si passivation layer and the barrier layer by using a PECVD (plasma enhanced chemical vapor deposition) process 2 Formation of SiO 2 And a passivation layer.
Specifically, the epitaxial wafer after the above steps is placed into a PECVD reaction chamber and NH is added 3 、SiH 4 、N 2 Depositing a layer of 5-100 nm SiO on the surface of the epitaxial wafer as a reaction gas 2 As SiO 2 Passivation layer as shown in fig. 3 f.
S5: and depositing gate electrode metal on the double-layer passivation layer above the gate region groove to form a gate electrode 8, and further forming a gate MIS (metal-insulator-semiconductor) structure, as shown in FIG. 3 g.
S6: a source electrode and a drain electrode are respectively formed on both sides of the gate electrode 9, and the lower surface of the source electrode and the lower surface of the drain electrode are both in contact with the upper surface of the channel layer.
Specifically, a source region groove and a drain region groove extending to the upper surface of the channel layer are respectively etched on both sides of the gate electrode 9 by using a photolithography process; and performing metal deposition on the source region groove and the drain region groove by using a sputtering or electron beam evaporation process to form a source electrode 9 and a drain electrode 7, and then performing a stripping process and annealing to realize low-resistance ohmic contact of the source electrode and the drain electrode, as shown in fig. 3 h. Preferably, the source electrode 9 and the drain electrode 7 are made of the same material and are made of a metal combination containing Ti/Al.
The embodiment provides a preparation method of a GaN-based double-layer passivated groove gate enhanced MIS-HEMT device, which comprises the following steps of forming a Si passivation layer and a SiO 2 The double-layer passivation structure of the passivation layer enables the surface state of the passivation layer to be reduced, and the passivation effect is better than that of a HEMT structure without the passivation layer and a single-layer passivation layer structure. The method of the embodiment has a simple process and is compatible with the conventional GaN HEMT process.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.
Claims (10)
1. A GaN-based double-layer passivation groove gate enhanced MIS-HEMT device is characterized by comprising a substrate (1), a nucleation layer (2), a buffer layer (3), a channel layer (4) and a barrier layer (6) which are arranged from bottom to top in sequence, wherein,
a first isolation region (5) and a second isolation region (11) are respectively arranged on two sides of the barrier layer (6), and the first isolation region (5) and the second isolation region (11) extend from the upper surface of the barrier layer (6) to the upper surface of the buffer layer (3);
a drain electrode (7) and a source electrode (9) are respectively arranged on the inner sides of the first isolation region (5) and the second isolation region (11), at least one part of the drain electrode (7) and at least one part of the source electrode (9) are embedded in the barrier layer (6), and the lower surfaces of the drain electrode (7) and the source electrode (9) are in contact with the channel layer (4) and form ohmic contact;
a gate region groove (12) is formed in the barrier layer (6) between the drain electrode (7) and the source electrode (9), and the inner surface of the gate region groove (12) and the upper surface of the barrier layer (6) are coated with a double-layer passivation layer (10); and a gate electrode (8) is arranged on the double-layer passivation layer (10) positioned in the gate region groove (12).
2. The GaN-based bi-layer passivated groove-gate enhanced MIS-HEMT device of claim 1, wherein said bi-layer passivation layer (10) comprises a Si passivation layer (101) and SiO 2 A passivation layer (102) in which,
the Si passivation layer (101) is positioned in the gate region groove (12) and grows outwards along the table top of the gate region groove (12) so as to enable the cross section to be in a U shape;
the SiO 2 The passivation layer (102) covers the upper surface of the Si passivation layer (101) and the upper surface of the barrier layer (6) between the drain electrode (7) and the source electrode (9), and two sides of the passivation layer are respectively contacted with the source electrode (9) and the drain electrode (7).
3. The GaN-based double-layer passivated groove gate enhanced MIS-HEMT device according to claim 2, wherein the thickness of the Si passivation layer (101) is 1-5 nm, and the thickness of the SiO2 passivation layer is 5-100 nm.
4. The GaN-based double-layer passivated groove-gate enhanced MIS-HEMT device of claim 1, wherein the lower end of the gate region groove (12) extends to the upper surface of the channel layer (4).
5. The GaN-based double-layer passivated groove-gate enhanced MIS-HEMT device according to claim 1, wherein the barrier layer (5) is Al with a thickness of 10-30 nm x Ga 1-x And an N barrier layer, wherein x is 0.1-0.5.
6. The GaN-based double-layer passivated notch-gate enhanced MIS-HEMT device according to any of claims 1 to 5, wherein the nucleation layer (2) is an AlN nucleation layer with a thickness of 50 to 400nm, the buffer layer (3) is an AlGaN buffer layer with a thickness of 200 to 8000nm, and the channel layer (4) is a GaN channel layer with a thickness of 50 to 500 nm.
7. A preparation method of a GaN-based double-layer passivated groove gate enhanced MIS-HEMT device is characterized by comprising the following steps:
s1: selecting a substrate and growing a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate in sequence;
s2: performing ion implantation on two sides of the barrier layer to respectively form a first isolation region and a second isolation region which extend to the upper surface of the buffer layer;
s3: etching the middle part of the upper surface of the barrier layer to form a gate region groove extending to the upper surface of the channel layer;
s4: growing a double-layer passivation layer in the gate region groove and the rest upper surface area of the barrier layer;
s5: performing gate electrode metal deposition on the double-layer passivation layer above the gate region groove to form a gate electrode;
s6: and respectively forming a source electrode and a drain electrode on two sides of the gate electrode, wherein the lower surface of the source electrode and the lower surface of the drain electrode are both in contact with the upper surface of the channel layer.
8. The method of claim 7, wherein the step of S1 comprises:
s11: selecting a Si, SiC or sapphire substrate, and carrying out plasma cleaning and surface pretreatment on the surface of the substrate to keep the surface of the substrate clean;
s12: an AlN nucleating layer with the thickness of 50-500 nm, an AlGaN buffer layer with the thickness of 200-8000 nm, an intrinsic GaN channel layer with the thickness of 50-500 nm and a thick layer are epitaxially grown on the substrate in sequenceAl with a degree of 10-30 nm x Ga 1-x And an N barrier layer, wherein x is 0.1 to 0.5.
9. The method of claim 7, wherein the step of S4 comprises:
s41: growing a 1-5 nm Si passivation layer on the upper surface of the barrier layer and in the gate region groove by using a CVD (chemical vapor deposition) technology;
s42: etching away the Si passivation layer on the surface of the barrier layer far away from the gate region groove to form the Si passivation layer which is positioned in the gate region groove and has a U-shaped section;
s43: depositing a layer of 5-100 nm SiO on the upper surfaces of the Si passivation layer and the barrier layer by using a PECVD (plasma enhanced chemical vapor deposition) process 2 Formation of SiO 2 And a passivation layer.
10. The method of claim 7, wherein the S6 comprises:
s61: respectively etching a source electrode region groove and a drain electrode region groove which extend to the upper surface of the channel layer on two sides of the gate electrode by utilizing a photoetching process;
s62: and performing metal deposition on the source region groove and the drain region groove by using a sputtering or electron beam evaporation process, and then performing a stripping process and annealing to form a source electrode and a drain electrode.
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