CN114823891A - A kind of GaN-based double-layer passivation groove gate enhancement mode MIS-HEMT device and preparation method thereof - Google Patents

Abstract

The invention discloses a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device and a preparation method thereof, wherein the device comprises a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, wherein a first isolation region and a second isolation region are respectively arranged on two sides of the barrier layer; the inner sides of the first isolation region and the second isolation region are respectively provided with a drain electrode and a source electrode, at least one part of the drain electrode and at least one part of the source electrode are embedded in the barrier layer, and the lower surfaces of the drain electrode and the source electrode are both contacted with the channel layer; a gate region groove is formed in the barrier layer between the drain electrode and the source electrode, and a double-layer passivation layer is coated on the inner surface of the gate region groove and the upper surface of the barrier layer; and a gate electrode is arranged on the double-layer passivation layer positioned in the groove of the gate region. According to the invention, the double-layer passivation layer forms the insulating layer in the direction vertical to the channel, so that the transport of current carriers in the vertical direction is blocked, and the device has the characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.

Description

A kind of GaN-based double-layer passivation groove gate enhancement mode MIS-HEMT device and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor devices, in particular to a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device and a preparation method thereof.

Background technique

High Electron Mobility Transistor (HEMT) based on AlGaN/GaN has excellent characteristics of high temperature resistance and high voltage resistance, and is widely used in the fields of power electronics, wireless communication and radio frequency. With the continuous improvement of device performance requirements in various application fields, there are still some gate electrode reliability problems in AlGaN/GaN-based HEMT devices that need to be solved urgently.

The gate electrode of the conventional GaN-based Schottky HEMT has serious leakage, and due to the existence of a large number of dislocations and defects in the GaN material, the charges are recombined by the surface states, resulting in a serious current collapse phenomenon. In order to solve this problem, a method of MIS (Metal-Insulator-Semiconductor)-HEMT using dielectric passivation layers such as Al ₂ O ₃ , SiN ₄ and SiO2 as the gate insulating layer has been proposed, although it inhibits the device to a certain extent The leakage of the gate electrode improves the problem of current collapse, but the insulating layer dielectric under the gate electrode also causes certain reliability problems of the device, resulting in a decrease in the current cut-off frequency of the device, PBTI (positive bias temperature instability, positive bias temperature instability, positive bias temperature instability) The effect of temperature instability) increases, thus limiting the wide application of GaN-based MIS-HEMT devices.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a GaN-based double-layer passivation groove gate enhancement type MIS-HEMT device and a preparation method thereof. The technical problem to be solved by the present invention is realized by the following technical solutions:

One aspect of the present invention provides a GaN-based double-layer passivation groove gate enhancement type MIS-HEMT device, comprising a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer sequentially arranged from bottom to top ,in,

Two sides of the barrier layer are respectively provided with a first isolation region and a second isolation region, and the first isolation region and the second isolation region extend from the upper surface of the barrier layer to the buffer layer. upper surface;

The inner side of the first isolation region and the second isolation region are respectively provided with a drain electrode and a source electrode, and at least a part of the drain electrode and at least a part of the source electrode are embedded in the barrier layer, so lower surfaces of the drain electrode and the source electrode are both in contact with the channel layer and form ohmic contact;

A gate region groove is opened on the barrier layer between the drain electrode and the source electrode, and the inner surface of the gate region groove and the upper surface of the barrier layer are coated with double layers A passivation layer; a gate electrode is arranged on the double-layer passivation layer located in the groove of the gate region.

In one embodiment of the present invention, the double-layer passivation layer includes a Si passivation layer and a SiO ₂ passivation layer, wherein,

The Si passivation layer is located in the gate region groove, and grows outward along the mesa surface of the gate region groove, so that the cross section is U-shaped;

The SiO ₂ passivation layer covers the upper surface of the Si passivation layer and the upper surface of the barrier layer between the drain electrode and the source electrode, and two sides are respectively connected to the source electrode and the source electrode. Drain electrode contacts.

In an embodiment of the present invention, the thickness of the Si passivation layer is 1-5 nm, and the thickness of the SiO 2 passivation layer is 5-100 nm.

In one embodiment of the present invention, the lower end of the gate region recess extends to the upper surface of the channel layer.

In an embodiment of the present invention, the barrier layer is an AlxGa1 _{-xN barrier} layer with a thickness of 10-30 nm, wherein x=0.1-0.5.

In an embodiment of the present invention, the nucleation layer is an AlN nucleation layer with a thickness of 50-400 nm, the buffer layer is an AlGaN buffer layer with a thickness of 200-8000 nm, and the channel layer is a thickness of 50-500 nm GaN channel layer.

Another aspect of the present invention provides a preparation method of a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device, comprising:

S1: select a substrate and sequentially grow a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate;

S2: performing ion implantation on both sides of the barrier layer to respectively form a first isolation region and a second isolation region extending to the upper surface of the buffer layer;

S3: performing etching in the middle of the upper surface of the barrier layer to form a gate region groove extending to the upper surface of the channel layer;

S4: growing a double-layer passivation layer in the gate region groove and the remaining upper surface region of the barrier layer;

S5: performing gate electrode metal deposition on the double-layer passivation layer above the gate region groove to form a gate electrode;

S6: A source electrode and a drain electrode are respectively formed on both sides of the gate electrode, and both the lower surface of the source electrode and the lower surface of the drain electrode are in contact with the upper surface of the channel layer.

In an embodiment of the present invention, the S1 includes:

S11: Select a Si, SiC or sapphire substrate, and perform plasma cleaning and surface pretreatment on the substrate surface to keep the substrate surface clean;

S12: epitaxially grow an AlN nucleation layer with a thickness of 50-500 nm, an AlGaN buffer layer with a thickness of 200-8000 nm, an intrinsic GaN channel layer with a thickness of 50-500 nm, and a thickness of 10-30 nm on the substrate in sequence The AlxGa1 _{-xN barrier} layer, where x=0.1-0.5.

In an embodiment of the present invention, the S4 includes:

S41: on the upper surface of the barrier layer and in the groove of the gate region, use CVD technology to grow a Si passivation layer of 1-5 nm;

S42: Etching away the Si passivation layer on the surface of the barrier layer far from the gate region groove, forming a Si passivation layer located in the gate region groove and having a U-shaped cross section;

S43: Using a PECVD process, deposit a layer of SiO ₂ with a thickness of 5-100 nm on the upper surfaces of the Si passivation layer and the barrier layer to form a SiO ₂ passivation layer.

In an embodiment of the present invention, the S6 includes:

S61: etching source region grooves and drain region grooves extending to the upper surface of the channel layer on both sides of the gate electrode by using a photolithography process;

S62: Metal deposition is performed on the source region grooves and the drain region grooves by a sputtering or electron beam evaporation process, followed by a lift-off process and annealing to form source electrodes and drain electrodes.

Compared with the prior art, the beneficial effects of the present invention are:

1. The present invention provides a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device including a substrate, a nucleation layer, a buffer layer, a device isolation region, a channel layer, a barrier layer, and a double-layer passivation layer, gate electrode, source electrode and drain electrode, the double-layer passivation layer is composed of Si passivation layer and SiO2 passivation layer, there is a gate area groove on the side of the barrier layer near the source electrode, and the Si passivation layer grows The SiO ₂ passivation layer is grown on the upper surface of the Si passivation layer and the barrier layer. This structure forms a double passivation layer by forming a Si passivation layer in the groove of the barrier layer and growing along the outer part of the mesa of the groove of the barrier layer, and the _SiO2 layer on the upper surface of the barrier layer and the Si passivation layer, respectively. Layer passivation layer structure. This structure forms an insulating layer in the vertical channel direction through a double passivation layer, thereby blocking the transport of carriers in the vertical direction, so that the device has the remarkable characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.

2. The present invention proposes a preparation method of a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device, using Si and SiO ₂ as the double-layer passivation layer, avoiding the traditional gate electrode insulating layer due to a series of interface states The problems such as high surface trap concentration, reduced device output current, and current collapse effect caused by the problem effectively improve the gate electrode withstand voltage and the reliability of the device.

3. The present invention proposes a method for preparing a GaN-based double-layer passivation groove-gate enhanced MIS-HEMT device. Through the double-layer passivation structure of the Si passivation layer and the SiO ₂ passivation layer, the surface state of the passivation layer is improved. It has better passivation effect than HEMT structure without passivation layer and single-layer passivation layer structure.

4. The process of the present invention is relatively simple, and is compatible with the current traditional GaN HEMT process.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

Description of drawings

1 is a schematic structural diagram of a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device provided by an embodiment of the present invention;

2 is a flow chart of a preparation method of a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device provided by an embodiment of the present invention;

3a to 3h are schematic diagrams of a fabrication process of a GaN-based double-layer passivation groove gate enhancement type MIS-HEMT device according to an embodiment of the present invention.

Description of reference numbers:

1-substrate; 2-nucleation layer; 3-buffer layer; 4-channel layer; 5-first isolation region; 6-barrier layer; 7-drain electrode; 8-gate electrode; 9-source electrode; 10-double-layer passivation layer; 101-Si passivation layer; 102-SiO2 passivation layer; 11-second isolation region; 12-gate region groove.

Detailed ways

In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following describes a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device according to the present invention with reference to the accompanying drawings and specific embodiments. and its preparation method are described in detail.

The foregoing and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description of the specific implementation with the accompanying drawings. Through the description of the specific embodiments, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and description, not for the technical means of the present invention. program is restricted.

It should be noted that, herein, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists. Moreover, the terms "comprising", "comprising" or any other variation are intended to encompass a non-exclusive inclusion such that an article or device comprising a list of elements includes not only those elements, but also other elements not expressly listed. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device that includes the element.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a GaN-based double-layer passivation groove gate enhancement type MIS-HEMT device provided by an embodiment of the present invention. The device includes a substrate 1 , a nucleation layer 2 , a buffer layer 3 , a channel layer 4 and a barrier layer 6 arranged in sequence from bottom to top, wherein first isolation regions 5 are respectively provided on both sides of the barrier layer 6 and the second isolation region 11, the first isolation region 5 and the second isolation region 11 extend from the upper surface of the barrier layer 6 to the upper surface of the buffer layer 3; the inner sides of the first isolation region 5 and the second isolation region 11 are respectively provided There are a drain electrode 7 and a source electrode 9, at least a part of the drain electrode 7 and at least a part of the source electrode 9 are embedded in the barrier layer 6, and the lower surfaces of the drain electrode 7 and the source electrode 9 are in contact with the channel layer 4 and form Ohmic contact; the barrier layer 6 between the drain electrode 7 and the source electrode 9 is provided with a gate region groove 12, and the inner surface of the gate region groove 12 and the upper surface of the barrier layer 6 are coated with double-layer passivation A gate electrode 8 is provided on the double-layer passivation layer 10 in the groove 12 of the gate region.

In this embodiment, the material of the substrate 1 is n ⁺ -GaN, SiC, sapphire or Si. Further, the nucleation layer 2 is an AlN nucleation layer with a thickness of 50-400 nm, the buffer layer 3 is an AlGaN buffer layer with a thickness of 200-8000 nm, the channel layer 4 is a GaN channel layer with a thickness of 50-500 nm, and the barrier layer 5 It is an AlxGa1 _{-xN barrier} layer with a thickness of 10-30 nm, wherein x=0.1-0.5.

The first isolation region 5 and the second isolation region 11 are N ion implanted regions formed by N ion implantation in the barrier layer 6 and the channel layer 4 . N ion implantation is performed in the first isolation region 5 and the second isolation region 11 to form high resistance regions to achieve device isolation.

Further, the double-layer passivation layer 10 includes a Si passivation layer 101 and a SiO ₂ passivation layer 102 , wherein the Si passivation layer 101 is located in the gate region recess 12 and faces along the mesa of the gate region recess 12 Outer growth, so that the cross section is U-shaped; the SiO ₂ passivation layer 102 covers the upper surface of the Si passivation layer 101 and the upper surface of the barrier layer 6 between the drain electrode 7 and the source electrode 9, and the two sides are respectively connected to the source electrode. 9 is in contact with the drain electrode 7 . Preferably, the thickness of the Si passivation layer 101 is 1˜5 nm, and the thickness of the SiO 2 passivation layer is 5˜100 nm.

Further, the lower end of the gate region recess 12 extends to the upper surface of the channel layer 4 . The outer side of the drain electrode 7 is in contact with the inner surface of the first isolation region 5 , and the outer side of the source electrode 9 is in contact with the inner surface of the second isolation region 11 . The lower surface of the drain electrode 7 passes through the barrier layer 6 and the channel layer 4 to form an ohmic contact, and the lower surface of the source electrode 9 passes through the barrier layer 6 and the channel layer 4 to form an ohmic contact.

Preferably, the source electrode 9 , the gate electrode 8 and the drain electrode 7 are made of the same material, which is a metal combination containing Ti/Al.

Embodiments of the present invention provide a GaN-based double-layer passivation groove gate enhancement mode MIS-HEMT device, comprising a substrate, a nucleation layer, a buffer layer, a device isolation region, a channel layer, a barrier layer, and a double-layer passivation layer, gate electrode, source electrode and drain electrode, the double-layer passivation layer is composed of Si passivation layer and SiO2 passivation layer, there is a gate area groove on the side of the barrier layer near the source electrode, and the Si passivation layer grows The SiO ₂ passivation layer is grown on the upper surface of the Si passivation layer and the barrier layer. This structure forms a double passivation layer by forming a Si passivation layer in the groove of the barrier layer and growing along the outer part of the mesa of the groove of the barrier layer, and the _SiO2 layer on the upper surface of the barrier layer and the Si passivation layer, respectively. Layer passivation layer structure. This structure forms an insulating layer in the vertical channel direction through a double passivation layer, thereby blocking the transport of carriers in the vertical direction, so that the device has the remarkable characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.

Embodiment 2

On the basis of Embodiment 1, this embodiment provides a preparation method of a GaN-based double-layer passivation groove gate enhancement mode MIS-HEMT device, please refer to FIG. 2, FIG. 3a to FIG. 3g, the preparation method includes :

S1: Select a substrate and sequentially grow a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate.

Select an n ⁺ -GaN, Si, SiC or sapphire substrate 1, and perform plasma cleaning and surface pretreatment on the surface of the substrate 1 to keep the surface of the substrate clean; subsequently, epitaxially grow on the substrate 1 to a thickness of 50 ~500nm AlN nucleation layer 2, 200~8000nm thick AlGaN buffer layer 3, 50~500nm thick intrinsic GaN channel layer 4, 10~30nm thick AlxGa1 _{-xN barrier} layer 6, where x=0.1-0.5, as shown in Figure 3a.

S2: performing ion implantation on both sides of the barrier layer to form a first isolation region and a second isolation region extending to the upper surface of the buffer layer, respectively.

Specifically, using an ion implantation process, on both sides of the upper surface of the barrier layer 6, N ions are implanted into the isolation region between the barrier layer 6 and the intrinsic GaN channel layer 4, and the N ion implantation concentration is 10 ¹⁸ -10 ²⁰ cm ^-3 , forming high-resistance regions, ie, the first isolation region 5 and the second isolation region 11, to achieve device isolation, as shown in FIG. 3b.

S3: Etching is performed in the middle of the upper surface of the barrier layer to form a gate region groove extending to the upper surface of the channel layer.

Specifically, the gate region recess 12 is formed by slow etching in the gate region of the barrier layer 6 close to the second isolation region 11 , and the gate region recess 12 extends downward through the barrier layer 6 to the GaN channel On the upper surface of layer 4, as shown in Fig. 3b, slow etching inhibits the interface state phenomenon caused by etching to a certain extent.

S4: Growing a double-layer passivation layer in the gate region recess and the remaining upper surface region of the barrier layer.

In this embodiment, step S4 includes:

S41: On the upper surface of the barrier layer 6 and in the groove 12 of the gate region, a Si passivation layer of 1-5 nm is grown by CVD (chemical vapor deposition) technology.

Specifically, the epitaxial wafer obtained in step S3 is cleaned by SF ₆ plasma, and NH ₃ , SiH ₄ and N ₂ reactive gases are introduced into the CVD reaction chamber, and a dense Si thin film of 1-5 nm is deposited on the surface of the epitaxial wafer, As the Si passivation layer 101, as shown in FIG. 3d.

S42: Slowly etch away the Si passivation layer on the surface of the barrier layer far from the gate region groove, and form the Si passivation layer 101 located in the gate region groove and having a U-shaped cross section, as shown in the figure 3e is shown.

S43: Using a PECVD (plasma-enhanced chemical vapor deposition) process, deposit a layer of SiO ₂ with a thickness of 5-100 nm on the upper surfaces of the Si passivation layer and the barrier layer to form a SiO ₂ passivation layer.

Specifically, put the epitaxial wafer after the above steps into a PECVD reaction chamber, and use NH ₃ , SiH ₄ , and N ₂ as reactive gases to deposit a layer of SiO ₂ with a thickness of 5-100 nm on the surface of the epitaxial wafer, as SiO ₂ passivation layer, as shown in Figure 3f.

S5: perform gate electrode metal deposition on the double-layer passivation layer above the gate region groove to form a gate electrode 8, and then form a gate MIS (metal-insulator-semiconductor) structure, as shown in FIG. 3g.

S6: A source electrode and a drain electrode are respectively formed on both sides of the gate electrode 9, and the lower surface of the source electrode and the lower surface of the drain electrode are both in contact with the upper surface of the channel layer.

Specifically, the source region groove and the drain region groove extending to the upper surface of the channel layer are etched respectively on both sides of the gate electrode 9 by a photolithography process; Metal deposition is performed on the electrode groove and the drain groove to form the source electrode 9 and the drain electrode 7, followed by a lift-off process and annealing to achieve low-resistance ohmic contact between the source electrode and the drain electrode, as shown in Figure 3h. Preferably, the source electrode 9 and the drain electrode 7 are made of the same material, which is a metal combination containing Ti/Al.

This embodiment proposes a preparation method of a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device. Through the double-layer passivation structure of the Si passivation layer and the SiO ₂ passivation layer, the surface state of the passivation layer is reduced , which has better passivation effect than HEMT structure without passivation layer and single-layer passivation layer structure. The process of the method in this embodiment is relatively simple, and is compatible with the current traditional GaN HEMT process.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device, is characterized in that, comprises the substrate (1), the nucleation layer (2), the buffer layer (3) that are arranged sequentially from bottom to top , a channel layer (4) and a barrier layer (6), wherein, A first isolation region (5) and a second isolation region (11) are respectively provided on both sides of the barrier layer (6), and the first isolation region (5) and the second isolation region (11) are self-contained. the upper surface of the barrier layer (6) extends to the upper surface of the buffer layer (3); A drain electrode (7) and a source electrode (9) are respectively provided inside the first isolation region (5) and the second isolation region (11), at least a part of the drain electrode (7) and the source At least a part of the electrode (9) is embedded in the barrier layer (6), and the lower surfaces of the drain electrode (7) and the source electrode (9) are both in contact with the channel layer (4) and form an ohmic contact; A gate region groove (12) is opened on the potential barrier layer (6) between the drain electrode (7) and the source electrode (9), and a gate region groove (12) is provided inside the gate region groove (12). The surface and the upper surface of the barrier layer (6) are coated with a double-layer passivation layer (10); a gate is provided on the double-layer passivation layer (10) located in the gate region groove (12) electrode (8). 2. The GaN-based double-layer passivation groove-gate enhanced MIS-HEMT device according to claim 1, wherein the double-layer passivation layer (10) comprises a Si passivation layer (101) and SiO ₂ a passivation layer (102), wherein, The Si passivation layer (101) is located in the gate region recess (12), and grows outward along the mesa surface of the gate region recess (12), so that the cross section is U-shaped; The _SiO2 passivation layer (102) covers the upper surface of the Si passivation layer (101) and the barrier layer (6) between the drain electrode (7) and the source electrode (9) The upper surface is in contact with the source electrode (9) and the drain electrode (7) on both sides respectively. 3. The GaN-based double-layer passivation groove-gate enhanced MIS-HEMT device according to claim 2, wherein the Si passivation layer (101) has a thickness of 1-5 nm, and the SiO2 passivation layer has a thickness of 1-5 nm. The thickness of the layer is 5 to 100 nm. 4. The GaN-based double-layer passivation groove gate enhancement type MIS-HEMT device according to claim 1, wherein the lower end of the gate region groove (12) extends to the channel layer (4) ) on the top surface. 5. The GaN-based double-layer passivation groove-gate enhanced MIS-HEMT device according to claim 1, wherein the barrier layer (5) is AlxGa1 _{-xN with} a thickness of 10-30nm barrier layer, wherein x=0.1-0.5. 6 . The GaN-based double-layer passivation groove-gate enhanced MIS-HEMT device according to claim 1 , wherein the nucleation layer ( 2 ) is AlN with a thickness of 50-400 nm Nucleation layer, the buffer layer (3) is an AlGaN buffer layer with a thickness of 200-8000 nm, and the channel layer (4) is a GaN channel layer with a thickness of 50-500 nm. 7. a preparation method of GaN-based double-layer passivation groove gate enhanced MIS-HEMT device, is characterized in that, comprising: S1: select a substrate and sequentially grow a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate; S2: performing ion implantation on both sides of the barrier layer to respectively form a first isolation region and a second isolation region extending to the upper surface of the buffer layer; S3: performing etching in the middle of the upper surface of the barrier layer to form a gate region groove extending to the upper surface of the channel layer; S4: growing a double-layer passivation layer in the gate region groove and the remaining upper surface region of the barrier layer; S5: performing gate electrode metal deposition on the double-layer passivation layer above the gate region groove to form a gate electrode; S6: A source electrode and a drain electrode are respectively formed on both sides of the gate electrode, and both the lower surface of the source electrode and the lower surface of the drain electrode are in contact with the upper surface of the channel layer. 8. The method for preparing a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device according to claim 7, wherein the S1 comprises: S11: Select a Si, SiC or sapphire substrate, and perform plasma cleaning and surface pretreatment on the substrate surface to keep the substrate surface clean; S12: epitaxially grow an AlN nucleation layer with a thickness of 50-500 nm, an AlGaN buffer layer with a thickness of 200-8000 nm, an intrinsic GaN channel layer with a thickness of 50-500 nm, and a thickness of 10-30 nm on the substrate in sequence The AlxGa1 _{-xN barrier} layer, where x=0.1-0.5. 9. The preparation method of the GaN-based double-layer passivation groove gate enhanced MIS-HEMT device according to claim 7, wherein the S4 comprises: S41: on the upper surface of the barrier layer and in the groove of the gate region, use CVD technology to grow a Si passivation layer of 1-5 nm; S42: Etching away the Si passivation layer on the surface of the barrier layer far from the gate region groove, forming a Si passivation layer located in the gate region groove and having a U-shaped cross section; S43: Using a PECVD process, deposit a layer of SiO ₂ with a thickness of 5-100 nm on the upper surfaces of the Si passivation layer and the barrier layer to form a SiO ₂ passivation layer. 10. The method for preparing a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device according to claim 7, wherein the S6 comprises: S61: etching source region grooves and drain region grooves extending to the upper surface of the channel layer on both sides of the gate electrode by using a photolithography process; S62: Metal deposition is performed on the source region grooves and the drain region grooves by a sputtering or electron beam evaporation process, followed by a lift-off process and annealing to form source electrodes and drain electrodes.

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