CN104701363A - Transistor based on enhanced grid structure and preparation method of transistor - Google Patents
Transistor based on enhanced grid structure and preparation method of transistor Download PDFInfo
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- CN104701363A CN104701363A CN201510057880.0A CN201510057880A CN104701363A CN 104701363 A CN104701363 A CN 104701363A CN 201510057880 A CN201510057880 A CN 201510057880A CN 104701363 A CN104701363 A CN 104701363A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 7
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 21
- 238000001704 evaporation Methods 0.000 claims description 19
- 230000008020 evaporation Effects 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000005036 potential barrier Methods 0.000 description 5
- 229910003460 diamond Inorganic materials 0.000 description 4
- 239000010432 diamond Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000539 two dimensional gel electrophoresis Methods 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000002269 spontaneous effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a transistor based on an enhanced grid structure. The transistor comprises a substrate, a buffer layer, a GaN (gallium nitride) layer, a barrier layer, a source electrode, a drain electrode and a grid electrode, wherein the substrate, the buffer layer, the GaN layer and the barrier layer are sequentially stacked from bottom to top, the source electrode is arranged on an aluminum gallium nitride layer, the grid electrode is positioned between the source electrode and the drain electrode, and the barrier layer is AlGaN or InAlGaN, and the grid electrode is p-type Al1-xGaxN (0<=x<=1) or p-type In1-y-zGayAlzN (0<=y<=1; 0<=z<=1). A DLC (Diamond-like carbon) layer is arranged on the grid electrode, and the content of sp2 keys of DLC is higher than 50%. According to the transistor, enhanced operation is realized, the self-heating effect of a transistor device can be reduced by diamond-like carbon, and stability is improved. The invention further provides a preparation method of the transistor.
Description
Technical field
The present invention relates to semiconductor device, particularly relate to a kind of transistor based on enhanced grid structure and preparation method thereof.
Background technology
High Electron Mobility Transistor (HEMT) is the Two-dimensional electron gas-bearing formation (2-DGE) utilizing heterojunction boundary to exist, and by changing the electron concentration of grid pressurized control 2-DGE between source electrode and drain electrode, thus controls operating state.HEMT is the transistor of a new generation, and the performance due to its excellence becomes the first-selection of high frequency, high pressure, high temperature and high-power applications aspect.
In current HEMT, the metal material that the many employings of grid material are common.Because it operates under high electric current and high-tension state, the thermally-stabilised and thermal diffusivity of grid always is important research theme.But the at present normal metal used, as tungsten (W) though there is good thermal stability, fusing point can reach more than 3400 DEG C, but due to work function too low, cause Schottky contacts (Schottky contact) not good.And molybdenum (Mo) is as often by the metal used, fusing point can reach more than 2600 DEG C, but its thermal stability is not good, is difficult to reach demand.
In addition, HEMT is generally depletion type work, realize enhancement mode work, has the process of employing fluorine (F) electricity slurry, N at present
2the process of O electricity slurry, but electricity slurry processes the electricity slurry injury caused, and the stability of assembly can be caused not enough; Also have and use the mode of Cascode, but make process complexity, encapsulate special, technological requirement is high, yield is low, is difficult to practical application.In addition, for enhancement mode HEMT, the change at area of grid with structure is mostly, the thermal stability urgent problem especially of its grid.
Summary of the invention
The object of the invention is to the deficiency overcoming prior art, a kind of transistor based on enhanced grid structure and preparation method thereof is provided.
The technical solution adopted for the present invention to solve the technical problems is: a kind of transistor based on enhanced grid structure, include the substrate, resilient coating, gallium nitride (GaN) layer, the barrier layer that stack gradually from the bottom to top, and be arranged at source electrode on aluminum gallium nitride, drain and be positioned at grid between the two, described barrier layer is AlGaN or InAlGaN, and described grid is p-type Al
1-xga
xn (0≤x≤1) or p-type In
1-y-zga
yal
zn (0≤y≤1; 0≤z≤1), on described grid, be also provided with a class bore carbon (Diamond-like carbon; DLC) layer, in described DLC, the content of sp2 key is greater than 50%.
Preferably, described DLC layer is p-type doping DLC, doped with the one be less than in the boron (B) of 5wt%, aluminium (Al), indium (In) or its combination.
Preferably, also comprise one and to be arranged at above described barrier layer and at least to cover the passivation layer of described source electrode, drain electrode, grid and conduction DLC layer part surface, described passivation layer is SiO
2, SiN or insulation DLC, in wherein said insulation DLC, the content of sp2 key is less than 20%.
Preferably, described source electrode, drain electrode and DLC layer top are respectively arranged with and add thick electrode, described in add many metal levels that thick electrode is selected from Ti/Au, Ti/Al, Ti/Pt/Au or Cr/Au.
Preferably, the upper surface of described DLC layer is also provided with metal electrode layer, described in add thick electrode and be arranged on metal electrode layer, wherein said metal electrode layer is the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal.
Preferably, the upper surface portion concave of described barrier layer becomes groove, and described grid is arranged on described groove.
Based on a preparation method for the transistor of enhanced grid structure, comprise the following steps:
(1) on a substrate, extension forms resilient coating, gallium nitride (GaN) layer and barrier layer successively;
(2) source electrode and drain electrode is formed on the surface in barrier layer;
(3) the area deposition grid extension on barrier layer between source electrode and drain electrode, wherein said grid is p-type Al
1-xga
xn (0≤x≤1) or p-type In
1-y-zga
yal
zn (0≤y≤1; 0≤z≤1);
(4) on grid, form DLC layer, in wherein said DLC, the content of sp2 key is greater than 50%;
(5) deposit a passivation layer, described passivation layer is covered in the superstructure that step (4) is formed;
(6) window to plate in the top of described source electrode, drain electrode and DLC layer and add thick electrode.
Preferably, step (2) specifically comprises the following steps:
By the method for electron beam evaporation plating two regions many metal levels of Ti/Al/Ni/Au on evaporation successively respectively in described barrier layer surface, the thickness of wherein said Ti/Al/Ni/Au is 25/125/45/55nm respectively;
The 5-45 that anneals at 800-950 DEG C forms ohmic contact second, forms described source electrode and drain electrode.
Preferably, described DLC layer be adopt magnetic control sputtering plating, ion evaporation, the method for arc ions evaporation or chemical vapour deposition (CVD) is formed at described gate surface.
Preferably, on the surface being also included in described barrier layer, dry etching forms the step of a groove, and described grid is formed on described groove.
Preferably, in step (4), be also included in the sub-step that DLC layer top deposits a metal electrode layer.
Preferably, described grid is deposited on described barrier layer on the surface by the method for magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD).
The invention has the beneficial effects as follows:
1, class bores carbon is the structure that stereoeffect (diamond, sp3 key) and plane reticular structure (graphite, sp2 key) coexist, and by the proportionate relationship of both adjustment, can adjust its calorifics and electric property.The class that wherein sp2 content is greater than 50% is bored carbon and is presented the form of approximate graphite, has the characteristic of conduction; Simultaneously due to the existence of its diamond lattic structure, heat conductivility and thermal stability well, are arranged at the spontaneous thermal effect that effectively can reduce transistor device on grid, meet the demand of high pressure, hot operation, improve the stability of device.
2, p-type Al
1-xga
xn or p-type In
1-y-zga
yal
zn-type, as grid, can form p-n contact-making surface with barrier layer, improves threshold voltage, realizes the object of enhancement mode work; Said structure without impact, can not cause the degeneration of performance on AlGaN/GaN or InGaAlN/GaN heterojunction boundary characteristic.
3, in surface coverage passivation layer, decrease current collapse effect, weaken external environment to the impact of transistor device; Adopt the insulation class of the approximate diamond form of sp2<20% to bore carbon, heat dispersion is good, and pressure-resistant corrosion-resisting, can well protective transistor device.
4, processing procedure is simple, special-less process requirement, and controllability is strong, is suitable for production application.
Accompanying drawing explanation
Fig. 1 is the structural representation of first embodiment of the invention;
Fig. 2 is the structural representation of second embodiment of the invention;
Fig. 3 is the structural representation of third embodiment of the invention;
Fig. 4 is the structural representation of fourth embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Each accompanying drawing of the present invention is only signal to be easier to understand the present invention, and its concrete ratio can adjust according to design requirement.The upper and lower relation of opposed member in figure described in literary composition, will be understood that the relative position referring to component those skilled in the art, therefore all can overturn and present identical component, and this all should belong to the scope disclosed by this specification together.
Embodiment 1
With reference to figure 1, the transistor 100 of the present embodiment, from the bottom to top sequentially laminated with substrate 101, resilient coating 102, gallium nitride layer 103 and barrier layer 104, the grid 107 that the upper surface of barrier layer 104 is provided with source electrode 105, drain electrode 106 and is positioned between the two, grid 107 top is sequentially laminated with DLC layer 108 and metal electrode layer 109.Above said structure, be coated with passivation layer 110, passivation layer 110 is respectively equipped with opening in source electrode 105, drain electrode 106 and the top of metal electrode layer 109, and is respectively arranged with at opening and adds thick electrode 111a, 111b and 111c.
Barrier layer 104 is AlGaN; Grid 107 is p-type Al
1-xga
xn, wherein 0≤x≤1.AlGaN and Al
1-xga
xform p-n contact-making surface between N, the potential barrier that the more common Schottky contacts (metal gates/aluminium gallium nitride alloy) of its potential barrier causes is high, can increase threshold voltage, realize enhancement mode HEMT.DLC layer 108 bores carbon (Diamond-like carbon by class; DLC) make, can be specifically the structure without other element dopings, the content of its sp2 key be greater than 50%, is partial to graphite-structure, has good electric conductivity, and effectively can reduce the spontaneous thermal effect of area of grid.
Metal electrode layer 109 can be the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal.
Passivation layer 110 is SiO
2, SiN or insulation DLC, the DLC that wherein insulate can be structure without other element dopings, and the content of its sp2 key is less than 20%, is partial to diamond lattic structure, has insulation characterisitic.
Add many metal levels that thick electrode 111a, 111b and 111c are selected from Ti/Au, Ti/Al, Ti/Pt/Au or Cr/Au.
Prepare the method for transistor 100, comprise the following steps:
1-1: extension forms resilient coating 102 and gallium nitride layer 103 successively on substrate 101, and depositing Al GaN forms barrier layer 104, obtained test piece;
1-2: cleaning test piece, utilize the mode of dry ecthing (RIE or ICP) by clean for the epitaxial loayer etching beyond device active region after cleaning, etch depth is about 200nm, use electron beam evaporation plating machine in two regions many metal levels of Ti/Al/Ni/Au on evaporation successively respectively on active region barrier layer 104 surface, wherein the thickness of each layer of Ti/Al/Ni/Au is 25/125/45/55nm respectively, put into quick-speed annealing machine after evaporation, anneal at 800-950 DEG C 5-45 second.As the preferred mode of one, can anneal at 850 DEG C and within 30 seconds, make to form ohmic contact between metal and AlGaN, form source electrode 105 and drain electrode 106;
1-3: by method depositing Al such as magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD)s between the surperficial source electrode 105 of barrier layer 104 and drain electrode 106
1-xga
xn forms grid 107, wherein 0≤x≤1;
1-4: the DLC formation DLC layer 108 that the content depositing sp2 key by methods such as magnetic control sputtering plating, ion evaporation, arc ions evaporation or plasma enhanced chemical vapor depositions on grid 107 is greater than 50%;
1-5: evaporation metal electrode layer 109 in DLC layer 108;
1-6: by ald, sputtering or plasma enhanced chemical vapor deposition method deposit passivation layer 110 to cover said structure;
1-7: windowing on source electrode 105, drain electrode 106 and the top of metal electrode layer 109 and plate respectively adds thick electrode 111a, 111b and 111c.
Embodiment 2
With reference to figure 2, the transistor 200 of the present embodiment, from the bottom to top sequentially laminated with substrate 201, resilient coating 202, gallium nitride layer 203 and barrier layer 204, the grid 207 that the upper surface of barrier layer 204 is provided with source electrode 205, drain electrode 206 and is positioned between the two, grid 207 top is sequentially laminated with DLC layer 208 and metal electrode layer 209.Above said structure, be coated with passivation layer 210, passivation layer 210 is respectively equipped with opening in source electrode 205, drain electrode 206 and the top of metal electrode layer 209, and is respectively arranged with at opening and adds thick electrode 211a, 211b and 211c.
Barrier layer 204 is InAlGaN; Grid 207 is p-type In
1-y-zga
yal
zn, wherein 0≤y≤1; 0≤z≤1.InAlGaN and In
1-y-zga
yal
zform p-n contact-making surface between N, the potential barrier that the more common Schottky contacts (metal gates/aluminium gallium nitride alloy) of its potential barrier causes is high, can increase threshold voltage, realize enhancement mode HEMT.The material of other elements is with embodiment 1, and not in this to go forth.
Prepare the method similar embodiment 1 of transistor 200, not in this to go forth.
Embodiment 3
With reference to figure 3, the transistor 300 of the present embodiment, from the bottom to top sequentially laminated with substrate 301, resilient coating 302, gallium nitride layer 303 and barrier layer 304, the grid 307 that the upper surface of barrier layer 304 is provided with source electrode 305, drain electrode 306 and is positioned between the two, grid 307 top is sequentially laminated with DLC layer 308 and metal electrode layer 309.Above said structure, be coated with passivation layer 310, passivation layer 310 is respectively equipped with opening in source electrode 305, drain electrode 306 and the top of metal electrode layer 309, and is respectively arranged with at opening and adds thick electrode 311a, 311b and 311c.
In the present embodiment, DLC layer 308 is DLC of p-type doping, and the content of sp2 key is greater than 50%, and doped with the one be less than in the boron (B) of 5wt%, aluminium (Al), indium (In) or its combination.The material of other assemblies is with embodiment 1, and prepare the method also similar embodiment 1 of transistor 300, not in this to go forth.P-type DLC and Al
1-xga
xform p-n contact-making surface between N grid 307, further increase potential barrier, thus improve threshold voltage, enhancement mode effect is more remarkable.
Embodiment 4
With reference to figure 4, the transistor 400 of the present embodiment, from the bottom to top sequentially laminated with substrate 401, resilient coating 402, gallium nitride layer 403 and barrier layer 404, the upper surface of barrier layer 404 is provided with source electrode 405 and drain electrode 406, and become groove 4041 in part concave between the two, groove 4041 is provided with grid 407, grid 407 top is sequentially laminated with DLC layer 408 and metal electrode layer 409.Above said structure, be coated with passivation layer 410, passivation layer 410 is respectively equipped with opening in source electrode 405, drain electrode 406 and the top of metal electrode layer 409, and is respectively arranged with at opening and adds thick electrode 411a, 411b and 411c.
In the present embodiment, the material of each assembly is with embodiment 1, and not in this to go forth.Barrier layer 404 is due to the setting of groove 4041, and it is in the lower thickness at corresponding grid 408 place, and by arranging suitable gash depth, reducing the concentration of grid region 2-DGE, further increasing threshold voltage, enhancement mode effect is more remarkable.
Prepare the method for transistor 400, comprise the following steps:
4-1,4-2: with step 1-1,1-2;
4-3: form groove 4041 in barrier layer 404 surface by reactive ion etching (RIE) or the method that inductively etches the dry ecthing such as (ICP);
4-4: by method depositing Al such as magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD)s on groove 4041
1-xga
xn forms grid 407, wherein 0≤x≤1;
4-5 to 4-8: with step 1-4 to 1-7.
Above-described embodiment is only used for further illustrating a kind of transistor based on enhanced grid structure of the present invention and preparation method thereof; but the present invention is not limited to embodiment; every above embodiment is done according to technical spirit of the present invention any simple modification, equivalent variations and modification, all fall in the protection range of technical solution of the present invention.
Claims (12)
1. the transistor based on enhanced grid structure, include the substrate, resilient coating, gallium nitride (GaN) layer, the barrier layer that stack gradually from the bottom to top, and be arranged at source electrode on aluminum gallium nitride, drain and be positioned at grid between the two, described barrier layer is AlGaN or InAlGaN, it is characterized in that: described grid is p-type Al
1-xga
xn (0≤x≤1) or p-type In
1-y-zga
yal
zn (0≤y≤1; 0≤z≤1), on described grid, be also provided with a class bore carbon (Diamond-like carbon; DLC) layer, in described DLC, the content of sp2 key is greater than 50%.
2. the transistor based on enhanced grid structure according to claim 1, it is characterized in that: described DLC layer is p-type doping DLC, doped with the one be less than in the boron (B) of 5wt%, aluminium (Al), indium (In) or its combination.
3. the transistor based on enhanced grid structure according to claim 1, it is characterized in that: also comprise one and to be arranged at above described barrier layer and at least to cover the passivation layer of described source electrode, drain electrode, grid and conduction DLC layer part surface, described passivation layer is SiO
2, SiN or insulation DLC, in wherein said insulation DLC, the content of sp2 key is less than 20%.
4. the transistor based on enhanced grid structure according to claim 1, it is characterized in that: described source electrode, drain electrode and DLC layer top are respectively arranged with and add thick electrode, described in add many metal levels that thick electrode is selected from Ti/Au, Ti/Al, Ti/Pt/Au or Cr/Au.
5. the transistor based on enhanced grid structure according to claim 1, it is characterized in that: the upper surface of described DLC layer is also provided with metal electrode layer, the described thick electrode that adds is arranged on metal electrode layer, and wherein said metal electrode layer is the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal.
6. the transistor based on enhanced grid structure according to claim 1, is characterized in that: the upper surface portion concave of described barrier layer becomes groove, and described grid is arranged on described groove.
7., based on a preparation method for the transistor of enhanced grid structure, comprise the following steps:
(1) on a substrate, extension forms resilient coating, gallium nitride (GaN) layer and barrier layer successively;
(2) source electrode and drain electrode is formed on the surface in barrier layer;
(3) the area deposition grid extension on barrier layer between source electrode and drain electrode, wherein said grid is p-type Al
1-xga
xn (0≤x≤1) or p-type In
1-y-zga
yal
zn (0≤y≤1; 0≤z≤1);
(4) on grid, form DLC layer, in wherein said DLC, the content of sp2 key is greater than 50%;
(5) deposit a passivation layer, described passivation layer is covered in the superstructure that step (4) is formed;
(6) window to plate in the top of described source electrode, drain electrode and DLC layer and add thick electrode.
8. preparation method according to claim 7, is characterized in that: step (2) specifically comprises the following steps:
By the method for electron beam evaporation plating two regions many metal levels of Ti/Al/Ni/Au on evaporation successively respectively in described barrier layer surface, the thickness of wherein said Ti/Al/Ni/Au is 25/125/45/55nm respectively;
The 5-45 that anneals at 800-950 DEG C forms ohmic contact second, forms described source electrode and drain electrode.
9. preparation method according to claim 7, is characterized in that: described DLC layer be adopt magnetic control sputtering plating, ion evaporation, the method for arc ions evaporation or chemical vapour deposition (CVD) is formed at described gate surface.
10. the preparation method according to claim 7 or 9, is characterized in that: on the surface being also included in described barrier layer, dry etching forms the step of a groove, and described grid is formed on described groove.
11. preparation methods according to claim 7, is characterized in that: in step (4), are also included in the sub-step that DLC layer top deposits a metal electrode layer.
12. preparation methods according to claim 7, is characterized in that: described grid is deposited on described barrier layer on the surface by the method for magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD).
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| US20100258843A1 (en) * | 2009-04-08 | 2010-10-14 | Alexander Lidow | ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME |
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