CN104701363B - A kind of transistor and preparation method thereof based on enhanced grid structure - Google Patents
A kind of transistor and preparation method thereof based on enhanced grid structure Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 12
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 8
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 7
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract 2
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 18
- 238000005036 potential barrier Methods 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 238000007740 vapor deposition Methods 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008719 thickening Effects 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
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- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 abstract description 5
- 239000010432 diamond Substances 0.000 abstract description 5
- 239000000446 fuel Substances 0.000 abstract description 3
- 230000002269 spontaneous effect Effects 0.000 abstract description 3
- 241001074085 Scophthalmus aquosus Species 0.000 abstract description 2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
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- 238000005538 encapsulation Methods 0.000 description 1
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- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a kind of transistors based on enhanced grid structure, include substrate, buffer layer, gallium nitride (GaN) layer, the barrier layer stacked gradually from the bottom to top, and it is set to source electrode on aluminum gallium nitride, drain electrode and positioned at grid between the two, the barrier layer is AlGaN or InAlGaN, and the grid is p-type Al1‑ xGaxN (0≤x≤1) or p-type In1‑y‑zGayAlzN(0≤y≤1；0≤z≤1), bore carbon (Diamond like carbon in being additionally provided with one kind on the grid；DLC) layer, the content of sp2 keys is more than 50% in the DLC.The transistor of the present invention realizes the purpose of enhanced work, and class brill carbon can reduce the spontaneous fuel factor of transistor device, improve stability.The present invention also provides the preparation methods of above-mentioned transistor.
Description
Technical field
The present invention relates to semiconductor devices, more particularly to a kind of transistor based on enhanced grid structure and its preparation
Method.
Background technology
High electron mobility transistor (HEMT) is to utilize Two-dimensional electron gas-bearing formation (2-DGE) existing for heterojunction boundary,
By changing the electron concentration of grid pressurized control 2-DGE between source electrode and drain electrode, to control working condition.HEMT is new one
The transistor in generation, the first choice in terms of becoming high frequency, high pressure, high temperature and high-power applications due to its excellent performance.
In current HEMT, grid material mostly uses common metal material.Because it is in the shape of high current and high voltage
It is operated under state, thermostabilization and the thermal diffusivity of grid always are important research theme.But the metal being often used at present, such as tungsten
(W) though there is good thermal stability, fusing point causes Schottky contacts up to 3400 DEG C or more, but since work function is too low
(Schottky contact) is bad.And molybdenum (Mo) is as the metal being often used, fusing point is up to 2600 DEG C or more, but its heat is steady
It is qualitative bad, it is difficult to reach demand.
In addition, HEMT be usually depletion type work, to realize enhanced work, have at present using fluorine (F) plasma-based handle,
N2The processing of O plasma-baseds, but the plasma-based injury caused by plasma-based processing, can cause the stability of component insufficient；Also have using Cascode
Mode, but be made that process is complicated, encapsulation is special, technological requirement is high, yield is low, it is difficult to practical application.In addition, for enhanced
HEMT is mostly to have structured change in area of grid, and the thermal stability of grid is even more urgent problem.
Invention content
It is an object of the invention to overcome the deficiency of the prior art, a kind of transistor based on enhanced grid structure is provided
And preparation method thereof.
The technical solution adopted by the present invention to solve the technical problems is：A kind of crystal based on enhanced grid structure
Pipe, includes substrate, buffer layer, gallium nitride (GaN) layer, the barrier layer stacked gradually from the bottom to top, and be set to aluminium gallium nitride alloy
Source electrode on layer, drain electrode and positioned at grid between the two, the barrier layer is AlGaN or InAlGaN, and the grid is p-type
Al1-xGaxN (0≤x≤1) or p-type In1-y-zGayAlzN(0≤y≤1；0≤z≤1), in being additionally provided with a kind of brill on the grid
Carbon (Diamond-like carbon；DLC) layer, the content of sp2 keys is more than 50% in the DLC.
Preferably, the DLC layer is p-type doping DLC, doped with less than 5wt% boron (B), aluminium (Al), in indium (In)
One kind or combinations thereof.
Preferably, further include one being set to above the barrier layer and at least covering the source electrode, drain electrode, grid and conduction
The passivation layer of DLC layer part surface, the passivation layer are SiO2, SiN or insulation DLC, wherein in the insulation DLC, sp2 keys
Content is less than 20%.
Preferably, the source electrode, drain electrode and DLC layer top are respectively arranged with thickening electrode, and the thickening electrode is selected from Ti/
More metal layers of Au, Ti/Al, Ti/Pt/Au or Cr/Au.
Preferably, the upper surface of the DLC layer is additionally provided with metal electrode layer, and the thickening electrode is set to metal electrode
On layer, wherein the metal electrode layer is the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal.
Preferably, the recessed formation groove of the upper surface portion of the barrier layer, the grid are set on the groove.
A kind of preparation method of the transistor based on enhanced grid structure, includes the following steps：
(1) in being formed epitaxially one after the other buffer layer, gallium nitride (GaN) layer and barrier layer on a substrate；
(2) in forming source electrode and drain electrode in potential barrier layer surface；
(3) the area deposition grid extension between source electrode and drain electrode on barrier layer, wherein the grid is p-type Al1- xGaxN (0≤x≤1) or p-type In1-y-zGayAlzN(0≤y≤1；0≤z≤1)；
(4) in forming DLC layer on grid, wherein the content of sp2 keys is more than 50% in the DLC；
(5) passivation layer is deposited, the passivation layer is covered in the superstructure of step (4) formation；
(6) in the top of the source electrode, drain electrode and DLC layer, windowing plates thickening electrode.
Preferably, step (2) specifically includes following steps：
Upper Ti/Al/Ni/ is deposited successively respectively in two regions of the potential barrier layer surface by the method for electron beam evaporation plating
The more metal layers of Au, wherein the thickness of the Ti/Al/Ni/Au is 25/125/45/55nm respectively；
It anneals at 800-950 DEG C 5-45 seconds and forms Ohmic contact, form the source electrode and drain electrode.
Preferably, the DLC layer is using magnetic control sputtering plating, ion vapor deposition, arc ions vapor deposition or chemical vapor deposition
Method is formed in the gate surface.
Preferably, further include the steps that forming a groove, the grid shape in dry etching on the surface of the barrier layer
On groove described in Cheng Yu.
Preferably, further include depositing the sub-step of a metal electrode layer in DLC layer top in step (4).
Preferably, the grid is the side by magnetic control sputtering plating, ion vapor deposition, arc ions vapor deposition or chemical vapor deposition
Method is deposited in the potential barrier layer surface.
The beneficial effects of the invention are as follows：
1, it is that stereoeffect (diamond, sp3 keys) and plane mesh structure (graphite, sp2 keys) coexist that class, which bores carbon,
Structure can adjust its calorifics and electric property by adjusting the proportionate relationship of the two.Wherein sp2 contents are more than 50% class
The form that carbon shows approximate graphite is bored, there is conductive characteristic；Simultaneously because the presence of its diamond lattic structure, heat conductivility and
Thermal stability is good, is set to the spontaneous fuel factor that can effectively reduce transistor device on grid, meets high pressure, height
The demand of temperature work, improves the stability of device.
2, p-type Al1-xGaxN or p-type In1-y-zGayAlzN-type can form p-n contact surfaces with barrier layer, improve as grid
Threshold voltage realizes the purpose of enhanced work；Above structure is to AlGaN/GaN or InGaAlN/GaN heterojunction boundary characteristics
Without influence, the degeneration of performance will not be caused.
3, passivation layer is covered in surface, reduces current collapse effect, weaken influence of the external environment to transistor device；
Using sp2<The insulation class of 20% approximate diamond form bores carbon, and heat dissipation performance is good, pressure-resistant corrosion-resisting, can be very good to protect
Protect transistor device.
4, processing procedure is simple, and special-less process requirement, controllability is strong, is suitable for production application.
Description of the drawings
Fig. 1 is the structural schematic diagram of first embodiment of the invention；
Fig. 2 is the structural schematic diagram of second embodiment of the invention；
Fig. 3 is the structural schematic diagram of third embodiment of the invention；
Fig. 4 is the structural schematic diagram of fourth embodiment of the invention.
Specific implementation mode
Invention is further described in detail with reference to the accompanying drawings and embodiments.The present invention each attached drawing be only illustrate with
It is easier to understand the present invention, specific ratio can be adjusted according to design requirement.Opposed member in figure described in text
Upper and lower relation, will be understood that in those skilled in the art refer to component relative position for, therefore can all overturn and be in
Existing identical component, this should all belong to the range disclosed by this specification.
Embodiment 1
With reference to figure 1, the transistor 100 of the present embodiment is sequentially laminated with substrate 101, buffer layer 102, nitridation from the bottom to top
Source 105, drain electrode 106 is arranged and positioned at grid between the two in the upper surface of gallium layer 103 and barrier layer 104, barrier layer 104
107,107 top of grid is sequentially laminated with DLC layer 108 and metal electrode layer 109.Passivation layer is covered with above above structure
110, passivation layer 110 is respectively equipped with opening in the top of source electrode 105, drain electrode 106 and metal electrode layer 109, and distinguishes in opening
It is provided with and thickeies electrode 111a, 111b and 111c.
Barrier layer 104 is AlGaN；Grid 107 is p-type Al1-xGaxN, wherein 0≤x≤1.AlGaN and Al1-xGaxBetween N
P-n contact surfaces are formed, potential barrier is high caused by the more common Schottky contacts of potential barrier (metal gates/aluminium gallium nitride alloy), Ke Yizeng
Add threshold voltage, realizes enhanced HEMT.DLC layer 108 is to bore carbon (Diamond-like carbon by class；DLC it) is made, has
Body can be the structure of no other elements doping, and the content of sp2 keys is more than 50%, is partial to graphite-structure, has good
Electric conductivity, and can effectively reduce the spontaneous fuel factor of area of grid.
Metal electrode layer 109 can be the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal.
Passivation layer 110 is SiO2, SiN or insulation DLC, wherein insulation DLC can be the structure of no other elements doping,
The content of sp2 keys is less than 20%, is partial to diamond lattic structure, has insulation characterisitic.
Thicken more metal layers that electrode 111a, 111b and 111c are selected from Ti/Au, Ti/Al, Ti/Pt/Au or Cr/Au.
The method for preparing transistor 100, includes the following steps：
1-1：In being formed epitaxially one after the other buffer layer 102 and gallium nitride layer 103 on substrate 101, and depositing Al GaN forms potential barrier
Test piece is made in layer 104；
1-2：Test piece is cleaned, it will be outer other than device active region in the way of dry ecthing (RIE or ICP) after cleaning
Prolong layer etching totally, etch depth is about 200nm, using electron beam evaporation plating machine in the areas Liang Ge on 104 surface of active region barrier layer
The more metal layers of upper Ti/Al/Ni/Au are deposited in domain successively respectively, and the thickness of each layers of wherein Ti/Al/Ni/Au is 25/125/45/ respectively
55nm is put into quick-speed annealing machine after vapor deposition, anneals 5-45 seconds at 800-950 DEG C.It as a preferred mode, can be in 850
Annealing 30 seconds at DEG C makes to form Ohmic contact between metal and AlGaN, forms source electrode 105 and drain electrode 106；
1-3：Pass through magnetic control sputtering plating, ion vapor deposition, arc ions between 104 surface source electrode 105 of barrier layer and drain electrode 106
The methods of vapor deposition or chemical vapor deposition depositing Al1-xGaxN forms grid 107, wherein 0≤x≤1；
1-4：In heavy by magnetic control sputtering plating, ion vapor deposition, arc ions vapor deposition or plasma-based Assisted Chemical Vapor on grid 107
DLC of the content more than 50% of the methods of product deposition sp2 keys forms DLC layer 108；
1-5：In evaporation metal electrode layer 109 in DLC layer 108；
1-6：By atomic layer deposition, sputtering or plasma enhanced chemical vapor deposition method deposit passivation layer 110 to cover
Lid above structure；
1-7：On the top of source electrode 105, drain electrode 106 and metal electrode layer 109 windowing and plating respectively thicken electrode 111a,
111b and 111c.
Embodiment 2
With reference to figure 2, the transistor 200 of the present embodiment is sequentially laminated with substrate 201, buffer layer 202, nitridation from the bottom to top
Source 205, drain electrode 206 is arranged and positioned at grid between the two in the upper surface of gallium layer 203 and barrier layer 204, barrier layer 204
207,207 top of grid is sequentially laminated with DLC layer 208 and metal electrode layer 209.Passivation layer is covered with above above structure
210, passivation layer 210 is respectively equipped with opening in the top of source electrode 205, drain electrode 206 and metal electrode layer 209, and distinguishes in opening
It is provided with and thickeies electrode 211a, 211b and 211c.
Barrier layer 204 is InAlGaN；Grid 207 is p-type In1-y-zGayAlzN, wherein 0≤y≤1；0≤z≤1.
InAlGaN and In1-y-zGayAlzP-n contact surfaces, potential barrier more common Schottky contacts (metal gates/nitridation are formed between N
Gallium aluminium) caused by potential barrier it is high, threshold voltage can be increased, realize enhanced HEMT.The material of other elements with embodiment 1,
This is not repeated here.
The method similar embodiment 1 of transistor 200 is prepared, not in this to go forth.
Embodiment 3
With reference to figure 3, the transistor 300 of the present embodiment is sequentially laminated with substrate 301, buffer layer 302, nitridation from the bottom to top
Source 305, drain electrode 306 is arranged and positioned at grid between the two in the upper surface of gallium layer 303 and barrier layer 304, barrier layer 304
307,307 top of grid is sequentially laminated with DLC layer 308 and metal electrode layer 309.Passivation layer is covered with above above structure
310, passivation layer 310 is respectively equipped with opening in the top of source electrode 305, drain electrode 306 and metal electrode layer 309, and distinguishes in opening
It is provided with and thickeies electrode 311a, 311b and 311c.
In the present embodiment, DLC layer 308 is the DLC of p-type doping, and the contents of sp2 keys is more than 50%, and doped with less than
One kind or combinations thereof in the boron (B) of 5wt%, aluminium (Al), indium (In).The material of other assemblies prepares transistor with embodiment 1
300 method also similar embodiment 1, not in this to go forth.P-type DLC and Al1-xGaxP-n contacts are formed between N grids 307
Face further improves potential barrier, and to improve threshold voltage, enhanced effect is more notable.
Embodiment 4
With reference to figure 4, the transistor 400 of the present embodiment is sequentially laminated with substrate 401, buffer layer 402, nitridation from the bottom to top
Gallium layer 403 and barrier layer 404, the upper surface setting source 405 of barrier layer 404 and drain electrode 406, and under part between the two
Spill is provided with grid 407 at groove 4041 on groove 4041,407 top of grid is sequentially laminated with DLC layer 408 and metal electricity
Pole layer 409.Passivation layer 410 is covered with above above structure, passivation layer 410 is in source electrode 405, drain electrode 406 and metal electrode
The top of layer 409 is respectively equipped with opening, and is respectively arranged in opening and thickeies electrode 411a, 411b and 411c.
The material of each component is with embodiment 1 in the present embodiment, and not in this to go forth.Barrier layer 404 is due to groove 4041
Setting, the thickness at corresponding grid 408 is thinning, by the way that suitable gash depth is arranged, reduces the dense of grid region 2-DGE
Degree, further improves threshold voltage, enhanced effect is more notable.
The method for preparing transistor 400, includes the following steps：
4-1、4-2：With step 1-1,1-2；
4-3：By reactive ion etching (RIE) or inductively the method for the dry ecthings such as etching (ICP) is in barrier layer 404
Surface forms groove 4041；
4-4：In passing through on groove 4041, magnetic control sputtering plating, ion vapor deposition, arc ions vapor deposition or chemical vapor deposition etc. are square
Method depositing Al1-xGaxN forms grid 407, wherein 0≤x≤1；
4-5 to 4-8：With step 1-4 to 1-7.
A kind of transistor based on enhanced grid structure that above-described embodiment only is used for further illustrating the present invention and its
Preparation method, but the invention is not limited in embodiments, it is every according to the technical essence of the invention to made by above example
Any simple modification, equivalent change and modification are each fallen in the protection domain of technical solution of the present invention.
Claims (12)
1. a kind of transistor based on enhanced grid structure includes the substrate, buffer layer, nitridation stacked gradually from the bottom to top
Gallium (GaN) layer, barrier layer, and be set on aluminum gallium nitride source electrode, drain electrode and positioned at grid between the two, the potential barrier
Layer is AlGaN or InAlGaN, it is characterised in that：The grid is p-type Al1-xGaxN (0≤x≤1) or p-type In1-y-zGayAlzN
(0≤y≤1；0≤z≤1), bore carbon (Diamond-like carbon in being additionally provided with one kind on the grid；DLC) layer, institute
The content for stating sp2 keys in DLC is more than 50%.
2. the transistor according to claim 1 based on enhanced grid structure, it is characterised in that：The DLC layer is p-type
DLC is adulterated, doped with the boron (B) less than 5wt%, aluminium (Al), one kind or combinations thereof in indium (In).
3. the transistor according to claim 1 based on enhanced grid structure, it is characterised in that：Further include one being set to
The passivation layer of the source electrode, drain electrode, grid and conductive DLC layer part surface is covered above the barrier layer and at least, it is described blunt
It is SiO to change layer2, SiN or insulation DLC, wherein in the insulation DLC, the content of sp2 keys is less than 20%.
4. the transistor according to claim 1 based on enhanced grid structure, it is characterised in that：The source electrode, drain electrode
It is respectively arranged with thickening electrode with DLC layer top, the electrode that thickeies is selected from the more of Ti/Au, Ti/Al, Ti/Pt/Au or Cr/Au
Metal layer.
5. the transistor according to claim 4 based on enhanced grid structure, it is characterised in that：The DLC layer it is upper
Surface is additionally provided with metal electrode layer, and the thickening electrode is set on metal electrode layer, wherein the metal electrode layer be Ti,
The combination layer of Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal.
6. the transistor according to claim 1 based on enhanced grid structure, it is characterised in that：The barrier layer it is upper
The recessed formation groove of surface portion, the grid are set on the groove.
7. a kind of preparation method of the transistor based on enhanced grid structure, includes the following steps：
(1) in being formed epitaxially one after the other buffer layer, gallium nitride (GaN) layer and barrier layer on a substrate；
(2) in forming source electrode and drain electrode in potential barrier layer surface；
(3) the area deposition grid extension between source electrode and drain electrode on barrier layer, wherein the grid is p-type Al1-xGaxN(0
≤ x≤1) or p-type In1-y-zGayAlzN(0≤y≤1；0≤z≤1)；
(4) in forming DLC layer on grid, wherein the content of sp2 keys is more than 50% in the DLC；
(5) passivation layer is deposited, the passivation layer is covered in the superstructure of step (4) formation；
(6) in the top of the source electrode, drain electrode and DLC layer, windowing plates thickening electrode.
8. preparation method according to claim 7, it is characterised in that：Step (2) specifically includes following steps：
By the method for electron beam evaporation plating, in two regions of the potential barrier layer surface, the upper Ti/Al/Ni/Au of vapor deposition is more successively respectively
Metal layer, wherein the thickness of the Ti/Al/Ni/Au is 25/125/45/55nm respectively；
It anneals at 800-950 DEG C 5-45 seconds and forms Ohmic contact, form the source electrode and drain electrode.
9. preparation method according to claim 7, it is characterised in that：The DLC layer is deposited using magnetic control sputtering plating, ion
Or the method for chemical vapor deposition is formed in the gate surface.
10. the preparation method according to claim 7 or 9, it is characterised in that：Further include in dry on the surface of the barrier layer
Method etches the step of forming a groove, and the grid is formed on the groove.
11. preparation method according to claim 7, it is characterised in that：Further include being deposited in DLC layer top in step (4)
The sub-step of one metal electrode layer.
12. preparation method according to claim 7, it is characterised in that：The grid is deposited by magnetic control sputtering plating, ion
Or the method for chemical vapor deposition is deposited in the potential barrier layer surface.
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