CN110429063B - Method for manufacturing semiconductor device with low noise value and device - Google Patents
Method for manufacturing semiconductor device with low noise value and device Download PDFInfo
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- CN110429063B CN110429063B CN201910573633.4A CN201910573633A CN110429063B CN 110429063 B CN110429063 B CN 110429063B CN 201910573633 A CN201910573633 A CN 201910573633A CN 110429063 B CN110429063 B CN 110429063B
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 54
- 238000001465 metallisation Methods 0.000 claims abstract description 16
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims description 30
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000005137 deposition process Methods 0.000 claims description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- 238000002161 passivation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor device with a low noise value and the device, wherein the method comprises the following steps: manufacturing source electrode and drain electrode metal on the epitaxial wafer; coating a first photoresist, and forming an opening at the bottom of the enhancement type grid; coating a second photoresist, and forming an opening with a narrow top and a wide bottom above the bottom of the enhancement type grid; performing metal deposition to enable the metal to be deposited at the bottom of the enhancement type grid electrode to form enhancement type grid electrode bottom metal; removing the first photoresist and the second photoresist, coating the third photoresist, and forming an opening with a narrow top and a wide bottom above the bottom of the enhancement type grid and the depletion type grid; performing metal deposition to enable metal to be deposited on the enhancement type grid bottom metal and the depletion type grid bottom to form enhancement type grid top metal and depletion type grid metal; and removing the third photoresist. The invention can reduce the noise value of the device and improve the radio frequency performance under the conditions of not increasing a light shield, not increasing additional processing steps and not changing the existing processing conditions.
Description
Technical Field
The present invention relates to the field of semiconductor device manufacturing, and in particular, to a method and a device for manufacturing a semiconductor device with a low noise value.
Background
In the prior art, when an enhancement type and depletion type gate devices of a gallium arsenide substrate are prepared, as shown in fig. 1, the enhancement type and depletion type devices are generally prepared separately, and finally, a passivation layer is deposited on the devices. The preparation method of the enhancement device comprises the following steps: a Y gate bottom photoetching process, a Y gate top photoetching process, a Y gate metallization deposition process and a metal tempering process; the preparation method of the depletion mode device comprises the following steps: surface cleaning, grid photoetching process and Y grid metallization deposition process. And performing a passivation process and a subsequent metal connecting line process under the condition that the enhancement type device process and the depletion type device process are finished. If the noise value of the device needs to be reduced, the enhancement type Y gate metal needs to be increased, and an additional photomask and a manufacturing process are needed. Each photomask has the necessary process requirements of cleaning, photoresist covering, developing inspection, etc., and the addition of the photomask and the process steps increases the process cost.
Disclosure of Invention
Therefore, it is desirable to provide a method and a device for manufacturing a semiconductor device with a low noise value, which can solve the problems of complex process and high cost of the conventional method for manufacturing a low noise device.
To achieve the above object, the inventors provide a method for manufacturing a semiconductor device with a low noise value, comprising the steps of:
manufacturing source electrode and drain electrode metal on the epitaxial wafer;
coating a first photoresist, and forming an opening at the bottom of the enhancement type grid;
coating a second photoresist, and forming an opening with a narrow top and a wide bottom above the bottom of the enhancement type grid;
performing metal deposition to enable the metal to be deposited at the bottom of the enhancement type grid electrode to form enhancement type grid electrode bottom metal;
removing the first photoresist and the second photoresist, coating the third photoresist, and forming an opening with a narrow top and a wide bottom above the bottom of the enhancement type grid and the depletion type grid;
performing metal deposition to enable metal to be deposited on the enhancement type grid bottom metal and the depletion type grid bottom to form enhancement type grid top metal and depletion type grid metal;
and removing the third photoresist.
Further, the opening on the first photoresist is an opening with a wide upper part and a narrow lower part.
Further, the first photoresist is a positive photoresist, the second photoresist is a negative photoresist, or the third photoresist is a negative photoresist.
Further, a nitride deposition process is included, and nitride is formed on the surface of the enhancement type grid metal and the depletion type grid metal.
Further, the method also comprises the following processes:
and a first metal deposition process, wherein a first metal layer is deposited at the source metal and the drain metal.
Furthermore, the epitaxial wafer is a gallium arsenide substrate epitaxial wafer.
The invention provides a device made according to the method of any one of the preceding claims.
Compared with the prior art, the technical scheme has the advantages that the purpose of increasing the total metal thickness of the enhanced grid electrode can be achieved by preparing the depletion type grid electrode and simultaneously performing complementary plating on the enhanced grid electrode, so that the grid electrode resistance is reduced, the noise value of a device is reduced, and the radio frequency performance is improved. Therefore, the thickness of the enhanced gate metal is increased, and simultaneously, no photomask, no additional processing step and no change of the existing processing conditions are added, so that the cost of the process manufacturing is reduced.
Drawings
FIG. 1 is a process flow for the fabrication of enhancement and depletion mode gate devices as described in the background art;
FIG. 2 is a process flow diagram according to an embodiment;
FIG. 3 is a schematic diagram of a device according to an embodiment with a first photoresist opening;
FIG. 4 is a schematic diagram of a second photoresist opening performed by the device according to an embodiment;
FIG. 5 is a schematic diagram of an embodiment of an enhanced gate bottom metal deposition device;
FIG. 6 is a schematic diagram of an embodiment of a device with an enhancement bottom metal gate;
FIG. 7 is a schematic diagram of a third photoresist opening performed by the device according to an embodiment;
FIG. 8 is a schematic diagram of a device according to an embodiment with enhanced gate top metal and depletion gate metal deposition;
FIG. 9 is a schematic diagram of a device according to an embodiment removing a third photoresist;
fig. 10 is a schematic diagram of a nitride coated device according to an embodiment.
Description of reference numerals:
D. a drain metal;
s, source electrode metal;
1. a first photoresist;
2. an enhancement type gate bottom;
3. a second photoresist;
4. a deposited metal;
40. an enhancement gate bottom metal;
5. a third photoresist;
6. a deposited metal;
60. an enhancement gate top metal;
61. a depletion mode gate metal;
7. and (3) nitride.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 2 to 10, the present embodiment provides a method for manufacturing a semiconductor device with low noise level, including the following steps: manufacturing source S and drain D metals on the epitaxial wafer; that is, the first step in fig. 2, surface treatment of the epitaxial wafer and the source-drain metallization process are performed to form source and drain metals on the epitaxial wafer. Then as shown in fig. 3, coating a first photoresist 1, and opening at the bottom 2 of the gate of the enhancement device to expose the bottom of the enhancement device to be deposited; i.e. an enhanced bottom photolithography process as in fig. 2 is performed. Then, as shown in fig. 4, a second photoresist 3 is coated, and an opening with a narrow top and a wide bottom is formed above the bottom of the enhancement gate, thereby completing the top photolithography process of the enhancement gate. And then metal 4 is deposited so that metal is deposited at the bottom of the enhancement gate to form an enhancement gate bottom metal 40, as shown in fig. 5, completing the enhancement gate metal deposition process. The first photoresist and the second photoresist are removed as shown in fig. 6. And coating a third photoresist 5, and forming an opening with a narrow top and a wide bottom above the bottom of the enhancement type gate and the depletion type gate, as shown in fig. 7, thereby completing the depletion type gate photoetching process. Metal 6 deposition is performed as shown in fig. 8, so that metal is deposited on the enhancement gate bottom metal and the depletion gate bottom, forming enhancement gate top metal 60 and depletion gate metal 61 as shown in fig. 9. Then, as shown in fig. 10, the third photoresist 5 is removed, thereby completing the thickening of the enhancement gate metal and the fabrication of the depletion gate metal. And after the manufacturing process is finished, respectively leading out the grid electrode/the source electrode/the drain electrode of the device according to the existing metal connecting line process.
According to the technical scheme, the purpose of increasing the total metal thickness of the enhancement type grid can be achieved by preparing the depletion type grid and simultaneously performing complementary plating on the enhancement type grid, so that the grid resistance is reduced, and the relation between the grid resistance and the noise value is as follows:
that is, when the gate resistance Rg is decreased, the noise value NF is decreased. Thereby achieving the purposes of reducing the noise value of the device and improving the radio frequency performance. Therefore, the thickness of the enhanced gate metal is increased, and simultaneously, no photomask, no additional processing step and no change of the existing processing conditions are added, so that the cost of the process manufacturing is reduced.
In order to form a Y-shaped gate, the opening on the first photoresist is an opening with a wide top and a narrow bottom. Further, in order to realize the opening of the photoresist, the first photoresist is a positive photoresist, the second photoresist is a negative photoresist, or the third photoresist is a negative photoresist.
In order to protect the gate metal and improve the strength and the withstand voltage of the gate metal, a nitride deposition process is further included, that is, a nitride deposition process of the first passivation layer of fig. 2 is included, nitride 7 is formed on the surfaces of the enhancement type gate metal (including the enhancement type gate top metal and the enhancement type gate bottom metal) and the depletion type gate metal, and the withstand voltage of the gate metal can be improved through the insulation of the nitride.
In some embodiments, to implement the fabrication of the field effect transistor, the following process is further included: and a first metal deposition process for depositing a first metal layer on the source metal and the drain metal, so that the height of the source metal and the drain metal is increased, and the performance is improved. And then, the next nitride deposition process, the polymer passivation flat layer process, the second layer of metal deposition process and the last layer of nitride deposition process can be carried out, and the field effect transistor can be manufactured.
The epitaxial wafer of the present application may be an epitaxial wafer used for fabricating a field effect transistor, preferably, the epitaxial wafer is a gallium arsenide-based epitaxial wafer.
The invention provides a device made according to the method of any one of the preceding claims. The device can reduce the noise value of the device and improve the radio frequency performance under the conditions of not increasing a light shield, not increasing extra processing steps and not changing the existing processing conditions, thereby saving the cost and the processing steps.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (7)
1. A method for manufacturing a semiconductor device having a low noise figure, comprising the steps of:
manufacturing source electrode and drain electrode metal on the epitaxial wafer;
coating a first photoresist, and forming an opening at the bottom of the enhancement type grid;
coating a second photoresist, and forming an opening with a narrow top and a wide bottom above the bottom of the enhancement type grid;
performing metal deposition to enable metal to be deposited at the bottom of the enhancement type grid electrode to form enhancement type grid electrode bottom metal, wherein the enhancement type grid electrode bottom metal is a Y-shaped grid electrode;
removing the first photoresist and the second photoresist, coating the third photoresist, and forming an opening with a narrow top and a wide bottom above the bottom of the enhancement type grid and the depletion type grid;
performing metal deposition to enable metal to be deposited on the enhancement type grid bottom metal and the depletion type grid bottom to form enhancement type grid top metal and depletion type grid metal, wherein the enhancement type grid top metal is arranged at the top of the Y-shaped grid;
and removing the third photoresist.
2. A method for manufacturing a semiconductor device with a low noise figure according to claim 1, wherein: the opening on the first photoresist is an opening with a wide upper part and a narrow lower part.
3. A method for manufacturing a semiconductor device with a low noise figure according to claim 1, wherein: the first photoresist is a positive photoresist, the second photoresist is a negative photoresist, or the third photoresist is a negative photoresist.
4. A method for manufacturing a semiconductor device with a low noise figure according to claim 1, wherein: and a nitride deposition process is further included, and nitride is formed on the surfaces of the enhancement type grid metal and the depletion type grid metal.
5. A method for manufacturing a semiconductor device with a low noise figure according to claim 4, wherein: the method also comprises the following processes:
and a first metal deposition process, wherein a first metal layer is deposited at the source metal and the drain metal.
6. A method for manufacturing a semiconductor device with a low noise figure according to any one of claims 1 to 5, wherein: the epitaxial wafer is a gallium arsenide substrate epitaxial wafer.
7. A semiconductor device having a low noise figure, characterized in that: the semiconductor device of low noise figure is manufactured according to the method of any one of claims 1 to 6.
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| CN201910573633.4A CN110429063B (en) | 2019-06-28 | 2019-06-28 | Method for manufacturing semiconductor device with low noise value and device |
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| CN110429063B true CN110429063B (en) | 2021-12-10 |
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