CN110112131A - The method and device that a kind of enhanced and depletion type grid device is prepared simultaneously - Google Patents
The method and device that a kind of enhanced and depletion type grid device is prepared simultaneously Download PDFInfo
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- CN110112131A CN110112131A CN201910189530.8A CN201910189530A CN110112131A CN 110112131 A CN110112131 A CN 110112131A CN 201910189530 A CN201910189530 A CN 201910189530A CN 110112131 A CN110112131 A CN 110112131A
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- photoresist
- enhanced
- metal
- depletion type
- type grid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8236—Combination of enhancement and depletion transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
Abstract
The present invention discloses the method and device of the enhanced and depletion type grid device of one kind while preparation, and wherein method includes the following steps: to make source electrode and drain electrode metal in extension on piece；It is coated with the first photoresist, and in enhancement device gate bottom upper opening；Fluorine ion injection is carried out to enhancement device bottom and lattice is repaired in heat treatment；The first photoresist is removed, is coated with the second photoresist, and form opening wide at the top and narrow at the bottom above enhanced grid bottom and depletion type grid bottom；It is coated with third photoresist, and forms up-narrow and down-wide opening above enhanced grid bottom and depletion type grid bottom；Metal deposit is carried out, so that metal deposit forms enhanced grid metal and depletion type grid metal in enhanced grid bottom and depletion type grid bottom；Remove the second photoresist and third photoresist.Enhanced and depletion type grid of the invention carries out in metal evaporation technique with along with, reduces a metal evaporation, has saved cost, while improving performance.
Description
Technical field
The present invention relates to semiconductor devices production fields, more particularly to a kind of enhanced and depletion type grid device to make simultaneously
Standby method and device.
Background technique
The prior art is in the enhanced and depletion type grid device preparation to GaAs substrate, as shown in Figure 1, generally adopting
Form is prepared separately with enhanced and depletion device to carry out, and the deposition of layer is finally passivated above device.Wherein enhance
--- photoetching process --- Y grid metal depositing operation --- at the top of Y grid that type device is the preparation method comprises the following steps: Y grid bottom photoetching process
Metal tempering process；--- gate lithography technique --- the Y grid metalization the preparation method comprises the following steps: surface clean of depletion device deposits
Technique.In the case where enhanced and depletion device technique is all completed, then it is passivated technique and subsequent metal connecting line work
Skill.It is carried out according to traditional processing step, then enhanced and depletion device needs are prepared separately, and can make the production of making technology
Expense increases.And the Schottky layer of the first device is easy exposure time mistake in air when carrying out second of element manufacturing
It is long, and then influence electrical property.
Summary of the invention
For this reason, it may be necessary to provide the method and device of the enhanced and depletion type grid device of one kind while preparation, solve existing
The problem of making technology is costly when the preparation of enhanced and depletion device, poor electrical performance.
To achieve the above object, a kind of enhanced method with depletion type grid device while preparation is inventor provided,
Include the following steps:
Source electrode and drain electrode metal is made in extension on piece；
It is coated with the first photoresist, and in enhancement device gate bottom upper opening；
Fluorine ion injection is carried out to enhancement device bottom and lattice is repaired in heat treatment；
The first photoresist is removed, is coated with the second photoresist, and above enhanced grid bottom and depletion type grid bottom
Form opening wide at the top and narrow at the bottom；
It is coated with third photoresist, and forms up-narrow and down-wide open above enhanced grid bottom and depletion type grid bottom
Mouthful；
Metal deposit is carried out, so that metal deposit is formed enhanced in enhanced grid bottom and depletion type grid bottom
Gate metal and depletion type grid metal；
Remove the second photoresist and third photoresist.
Further, the opening on first photoresist is opening wide at the top and narrow at the bottom.
Further, first photoresist is positive photoresist or the second photoresist is positive photoresist or third
Photoresist is negative photoresist.
It further, further include nitride deposition process, in enhanced grid metal and depletion type grid metal surface shape
At nitride.
Further, further include following technique:
First layer metal depositing operation deposits first layer metal at source metal and drain metal.
Further, the epitaxial wafer is GaAs substrate epitaxial wafer.
The present invention provides a kind of device, it is characterised in that: the device is made according to above-mentioned any one the method.
It is different from the prior art, the enhanced and depletion type grid of above-mentioned technical proposal is with along in metal evaporation technique
It carries out, reduces a metal evaporation, saved cost.And it avoids and is made after the completion of the preparation of the first device in traditional handicraft
The touch opportunity and time of Schottky layer and other substances, improve the quality of Schottky contacts in standby second of device process.
Detailed description of the invention
Fig. 1 is enhanced described in background technique and depletion type grid device preparation process flow；
Fig. 2 is process flow chart described in specific embodiment；
Fig. 3 is the structural schematic diagram that device described in specific embodiment carries out the first photoresist；
Fig. 4 is the structural schematic diagram of the processing of device enhancement mode bottom device described in specific embodiment；
Fig. 5 is the structural schematic diagram that device described in specific embodiment removes the first photoresist；
Fig. 6 is the structural schematic diagram that device described in specific embodiment is coated with the second photoresist；
Fig. 7 is the structural schematic diagram that device described in specific embodiment is coated with third photoresist；
Fig. 8 is the structural schematic diagram that device described in specific embodiment carries out metal deposit；
Fig. 9 is the structural schematic diagram that device described in specific embodiment removes second, third photoresist.
Description of symbols:
D, drain metal；
S, source metal；
1, the first photoresist；
2, enhancement device grid bottom；
3, the second photoresist；
4, third photoresist；
5, the metal deposited；
50, gate metal.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality
It applies example and attached drawing is cooperated to be explained in detail.The english abbreviation being likely to occur in specification and Figure of description is said first below
It is bright:
1.EGB:E-modeGate Bottom, enhancement device bottom photoetching process.
2.EGT:E-modeGate Top, enhancement device top photoetching process.
3.EGD:E-modeGate Deposition, enhancement device metallic deposition technique.
4.DGP:D-ModeGatePhoto, depletion device photoetching process.
5.DGD:D-modeGateDeposition, depletion device metallic deposition technique.
6.1PN:1st Passivation Nitride, the first passivation layer nitride deposition process.
7.1MD:1st Metal Deposition, the first metal layer depositing operation.
8.2PN:2nd Passivation Nitride, the second passivation layer nitride deposition process.
9.PP:Polyimide Passivation, the flat layer process of polymer inactivation.
10.2MD:2nd Metal Deposition, second metal layer depositing operation.
11.3PN:3rd Passivation Nitride, third passivation layer nitride deposition process.
12.EGP:E-modegate pretreatment, the pretreatment of enhancement device grid.
13.FIMP:Fluoride ionimplant, fluorine ion injection.
14.EDGB:E/D-mode Gate Bottom, enhanced/depletion type grid bottom.
15.EDGT:E/D-mode Gate Top, enhanced/depletion type grid top.
16.EDGD:E/D-mode Gate Deposition, enhanced/depletion type grid metal deposition process.
Fig. 2 to 9 is please referred to, the present embodiment provides a kind of method that enhanced and depletion type grid device is prepared simultaneously, packets
It includes following steps: making source S and drain D metal in extension on piece；Carry out the first step in Fig. 2, epitaxial wafer surface treatment
With source-drain electrode metallization process, source electrode and drain electrode metal is formed in extension on piece.Then as shown in figure 3, the first photoresist of coating
1, and in 2 upper opening of enhancement device grid bottom, so that the bottom of upper enhancement device to be deposited is exposed,；Carry out in Fig. 2
EGP technique.Then as shown in figure 4, carrying out fluorine ion injection and heat treatment reparation lattice to enhancement device bottom 2
(FIMP), change the epitaxial wafer physical structure distribution of upper enhancement device bottom to be deposited in this way, and then change depletion region junction depth,
The cut-in voltage of device can be changed by the implantation amount and implantation depth difference of fluorine ion.Then as shown in figure 5, removal first
Photoresist 1, then as shown in fig. 6, the second photoresist 3 of coating, and rectangular on enhanced grid bottom and depletion type grid bottom
At opening (EDGB) wide at the top and narrow at the bottom.Then as shown in fig. 7, being coated with third photoresist 4, and in enhanced grid bottom and exhaust
Up-narrow and down-wide opening (EDGT) is formed above type gate bottom.Then as shown in figure 8, carrying out metal 5 deposits (EDGD), so that
Metal deposit forms enhanced grid metal 50 and depletion type grid metal in enhanced grid bottom and depletion type grid bottom
50；Then as shown in figure 9, the second photoresist 3 of removal and third photoresist 4, thus complete enhanced grid metal and exhaust
The production of type gate metal.It is completed after processing procedure, then according still further to existing metal connecting line technique by device grids/source/drain fraction
It does not draw.This method can realize it is enhanced realized in metal evaporation technique with depletion device with along with, while reducing device
Schottky layer (gate metal and epitaxial wafer contact position) aerial exposure duration, it is ensured that the stabilization of device Schottky contact
Property.
Ion implanting is carried out to enhanced grid bottom for convenience, the opening on first photoresist is wide at the top and narrow at the bottom
Opening.Further, in order to realize the opening of above-mentioned photoresist, first photoresist is positive photoresist or second
Photoresist is positive photoresist or third photoresist is negative photoresist.
In order to realize the protection to gate metal, gate metal intensity and pressure-resistant degree are improved, further includes nitride deposition
Technique, i.e. the 1PN technique of Fig. 2 form nitride in enhanced grid metal and depletion type grid metal surface, pass through nitride
Insulating properties, the pressure-resistant degree of gate metal can be improved.
In certain embodiments, further include following technique in order to realize the production of field effect transistor: first layer metal is heavy
Product technique, deposits first layer metal, so that the height of source metal and drain metal at source metal and drain metal
It gets higher, performance improves.The flat layer process of nitride deposition process, polymer inactivation, the second layer next time can then be carried out
The nitride deposition process of metal deposition process and the last layer, it can complete the production of field effect transistor.
The epitaxial wafer of the application can be the epitaxial wafer for making field effect transistor, it is preferable that the epitaxial wafer is
GaAs substrate epitaxial wafer.
The present invention provides a kind of device, it is characterised in that: the device is made according to above-mentioned any one the method.On
It states device to carry out in metal evaporation technique with depletion type grid with along with due to enhanced, reduces a metal evaporation, save
About cost.And it avoids and prepares Schottky layer in second of device process after the completion of the preparation of the first device in traditional handicraft
Touch opportunity and time with other substances, improve the quality of Schottky contacts.
It should be noted that being not intended to limit although the various embodiments described above have been described herein
Scope of patent protection of the invention.Therefore, it based on innovative idea of the invention, change that embodiment described herein is carried out and is repaired
Change, or using equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it directly or indirectly will be with
Upper technical solution is used in other related technical areas, is included within scope of patent protection of the invention.
Claims (7)
1. a kind of method that enhanced and depletion type grid device is prepared simultaneously, which comprises the steps of:
Source electrode and drain electrode metal is made in extension on piece；
It is coated with the first photoresist, and in enhancement device gate bottom upper opening；
Fluorine ion injection is carried out to enhancement device bottom and lattice is repaired in heat treatment；
The first photoresist is removed, is coated with the second photoresist, and formed above enhanced grid bottom and depletion type grid bottom
Opening wide at the top and narrow at the bottom；
It is coated with third photoresist, and forms up-narrow and down-wide opening above enhanced grid bottom and depletion type grid bottom；
Metal deposit is carried out, so that metal deposit forms enhanced grid in enhanced grid bottom and depletion type grid bottom
Metal and depletion type grid metal；
Remove the second photoresist and third photoresist.
2. the enhanced method prepared simultaneously with depletion type grid device of one kind according to claim 1, it is characterised in that:
Opening on first photoresist is opening wide at the top and narrow at the bottom.
3. the enhanced method prepared simultaneously with depletion type grid device of one kind according to claim 1, it is characterised in that:
First photoresist is positive photoresist or the second photoresist is positive photoresist or third photoresist is negative photo
Glue.
4. the enhanced method prepared simultaneously with depletion type grid device of one kind according to claim 1, it is characterised in that:
Further include nitride deposition process, forms nitride in enhanced grid metal and depletion type grid metal surface.
5. the enhanced method prepared simultaneously with depletion type grid device of one kind according to claim 4, it is characterised in that:
Further include following technique:
First layer metal depositing operation deposits first layer metal at source metal and drain metal.
6. according to claim 1 to the method that one kind described in 5 any one is enhanced and depletion type grid device is prepared simultaneously,
It is characterized by: the epitaxial wafer is GaAs substrate epitaxial wafer.
7. a kind of device, it is characterised in that: the device is made to 6 any one the methods according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910189530.8A CN110112131A (en) | 2019-03-13 | 2019-03-13 | The method and device that a kind of enhanced and depletion type grid device is prepared simultaneously |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910189530.8A CN110112131A (en) | 2019-03-13 | 2019-03-13 | The method and device that a kind of enhanced and depletion type grid device is prepared simultaneously |
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| CN110112131A true CN110112131A (en) | 2019-08-09 |
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| CN201910189530.8A Pending CN110112131A (en) | 2019-03-13 | 2019-03-13 | The method and device that a kind of enhanced and depletion type grid device is prepared simultaneously |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110429063A (en) * | 2019-06-28 | 2019-11-08 | 福建省福联集成电路有限公司 | A kind of method, semi-conductor device manufacturing method and device of noise values |
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| CN103915434A (en) * | 2014-03-28 | 2014-07-09 | 长安大学 | GaN-base ultra-thin potential barrier reinforced and depletion mode phase inverter, ring oscillation and manufacturing method of phase inverter |
| CN104835819A (en) * | 2014-12-04 | 2015-08-12 | 中国电子科技集团公司第五十五研究所 | GaN E/D integrated device production method based on two-step oxidation method |
| CN108922924A (en) * | 2018-06-05 | 2018-11-30 | 福建省福联集成电路有限公司 | A kind of multilayer autoregistration Y gate transistor device manufacturing method and transistor device |
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2019
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1921077A (en) * | 2005-08-26 | 2007-02-28 | 中国科学院微电子研究所 | Producing method for GaAs radical enhancing/depletion type fakement matching high electron mobility transistor gate |
| CN102376760A (en) * | 2010-08-25 | 2012-03-14 | 财团法人交大思源基金会 | Enhanced high electron mobility transistor and manufacturing method thereof |
| CN103915434A (en) * | 2014-03-28 | 2014-07-09 | 长安大学 | GaN-base ultra-thin potential barrier reinforced and depletion mode phase inverter, ring oscillation and manufacturing method of phase inverter |
| CN104835819A (en) * | 2014-12-04 | 2015-08-12 | 中国电子科技集团公司第五十五研究所 | GaN E/D integrated device production method based on two-step oxidation method |
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| CN110429063A (en) * | 2019-06-28 | 2019-11-08 | 福建省福联集成电路有限公司 | A kind of method, semi-conductor device manufacturing method and device of noise values |
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Application publication date: 20190809 |
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