CN103066122A - Metal-oxide-semiconductor field effect transistor (MOSFET) and manufacturing method thereof - Google Patents
Metal-oxide-semiconductor field effect transistor (MOSFET) and manufacturing method thereof Download PDFInfo
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- CN103066122A CN103066122A CN2011103220870A CN201110322087A CN103066122A CN 103066122 A CN103066122 A CN 103066122A CN 2011103220870 A CN2011103220870 A CN 2011103220870A CN 201110322087 A CN201110322087 A CN 201110322087A CN 103066122 A CN103066122 A CN 103066122A
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Abstract
The invention discloses a metal-oxide-semiconductor field effect transistor (MOSFET). The MOSFET comprises a substrate, a grid stacking structure arranged on the substrate, grid side wall structures arranged on two sides of the grid stacking structure and a source drain region arranged inside the substrate on two sides of the grid side wall structures. The MOSFET is characterized in that each grid side wall structure comprises a first grid side wall and a second grid side wall, and the second grid side wall is made of diamond-like carbon (DLC). In accordance with the high stress MOSFET and a manufacturing method thereof, high stress DLC thin films are used as grid side walls, and thus the distance of a stressed layer and a channel region is shortened, the carrier mobility of the channel region is effectively improved, and the performance of a device is enhanced.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of MOSFET and manufacture method thereof with heavily stressed diamond like carbon amorphous carbon (DLC) side wall.
Background technology
From 90nm CMOS integrated circuit technology, along with constantly dwindling of device feature size, played more and more important effect take raising channel carrier mobility as purpose stressed channels engineering (Strain Channel Engineering).Multiple single shaft technique is led to stress to be integrated in the device technology and is gone, thereby also namely introduces compression or tension stress enhancing carrier mobility at channel direction, improves device performance.For example, in 90nm technique, adopt embedded SiGe (e-SiGe) source to leak or 100 crystal orientation substrates and provide compression in the pMOS device in conjunction with tension stress etch barrier (tCESL); In 65nm technique, on 90nm technique basis, further adopt first generation source-drain electrode stress memory technique (SMT
* 1), and adopted two etch barrier; In the 45nm technique, adopted second generation source-drain electrode stress memory technique (SMT on basis before
* 2), adopt the e-SiGe technology in conjunction with single tCESL or two CESL, and adopted stress closely to face technology (Stress Proximity Technique, SPT), adopt 110 substrates and adopt 100 substrates for nMOS for pMOS in addition; After the 32nm, adopted third generation source-drain electrode stress memory technique (SMT
* 3), on basis before, also selected embedded SiC source to leak to strengthen tension stress in the nMOS device.
In addition, introduce the technology of stress to raceway groove except changing substrate, source leakage material, can also realize by material, the section shape of control raceway groove or side wall.For example adopt two stress liner (DSL) technology, adopt tension stress SiN for nMOS
xLayer side wall adopts the compression side wall for pMOS.The section that for example embedded SiGe source is leaked again is fabricated to ∑ shape, improves the channel stress of pMOS.
Yet these conventional stress technique effects continue to dwindle and are constantly weakened along with device size.For nMOS, along with characteristic size reduction, provide dislocation and skew between each layer film of stress more and more obvious, when just requiring the film thickness attenuate, this can also accurately provide higher stress.For pMOS, the channel carrier mobility that technology is leaked in embedded SiGe source significantly depends on characteristic size, dimension reduction so that the effect that carrier mobility improves have a greatly reduced quality.
A kind of new thinking is to adopt diamond like carbon amorphous carbon (DLC) film to improve the intrinsic stress of device.Such as people such as Kian-Ming Tan at IEEE ELETRON DEVICE LETTERS, VOL.29, NO.2, " A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET " that delivers on the FEBUARY 2008, cover the DLC higher than SiN compression on whole MOSFET surface, the heavily stressed going down of DLC is to channel region, thereby correspondingly improved channel stress, improved the electric property of device.In addition, US Patent No. 2010/0213554A1 has also adopted similar structures.
But, when the DLC of the high strain of routine is applied to aforementioned CESL or pressure cushion layer structure, owing to only covering heavily stressed DLC film at whole device surface, it is far away apart from the device inside channel region, to the effects of strain effect of raceway groove center a little less than, also being the DLC film reduces through the stress that is delivered to channel region after grid, thicker individual layer side wall or the structures such as multilayer side wall stacked structure, gate insulating film, is difficult to produce a desired effect.
In a word, in existing stress MOSFET, therefore traditional stress provides structure to be difficult to be applied to small size device, is difficult to the Effective Raise device performance, a kind ofly can effectively control channel stress, improves Novel MOS FET and manufacture method thereof that carrier mobility is improved device performance thereby need badly.
Summary of the invention
From the above mentioned, thus the object of the present invention is to provide and a kind ofly can effectively control channel stress, improve Novel MOS FET and manufacture method thereof that carrier mobility is improved device performance.
For this reason, the invention provides a kind of MOSFET, comprise the gate stack structure on substrate, the substrate, the grid curb wall structure of gate stack structure both sides, the source-drain area in the substrate of grid curb wall structure both sides, it is characterized in that: the grid curb wall structure comprises first grid side wall and second grid side wall, and the material of second grid side wall is DLC.
Wherein, sp among the DLC of second grid side wall
3The content of key at least greater than 50%, hydrogen atom content is less than 40%, nitrogen atom content is less than 20%, intrinsic stress is not less than 2GPa.
Wherein, the first grid side wall comprises vertical component and horizontal component, and the second grid side wall is positioned on the horizontal component of first grid side wall.
Wherein, the material of first grid side wall is silica, silicon nitride and/or silicon oxynitride.
Wherein, the thickness of first grid side wall is 1～25nm, and the thickness of second grid side wall is 2～60nm.
Wherein, gate stack structure comprises gate insulator, gate material layers and barrier layer; Gate insulator comprises silica, nitrating silica, silicon nitride or hafnium; Gate material layers comprises the metal that is selected from Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, or comprises and be selected from In
2O
3, SnO
2, ITO, IZO conductor metal oxide, or the polysilicon, amorphous silicon, polycrystalline germanium, the poly-SiGe that mix; Or M
xN
y, M
xSi
yN
z, M
xAl
yN
z, M
aAl
xSi
yN
z, wherein M comprises Ta, Ti, Hf, Zr, Mo, W, or the composite bed of above-mentioned material; Substrate comprises silicon, germanium, strained silicon, germanium silicon, compound semiconductor or the materials such as Graphene, carbon back semiconductor.Wherein, mix C, F, N, O, B, P, As in the gate material layers.
Wherein, source-drain area is embedded SiGe or SiC, and source-drain area also has source and drain extension along channel direction, and source and drain extension is positioned at grid curb wall structure below.
Wherein, have drain contact metal silicide in source on the source-drain area, contact etch stop layer covers source drain contact metal silicide, grid curb wall structure and gate stack structure.Wherein, drain contact metal silicide in source comprises CoSi
2, TiSi
2, NiSi, PtSi, NiPtSi, CoGeSi, TiGeSi, NiGeSi, the contact etch stop layer material is heavily stressed silica, silicon nitride or DLC.
The present invention also provides a kind of MOSFET manufacture method, may further comprise the steps: form the dummy grid stacked structure at substrate; In the substrate of dummy grid stacked structure both sides, form source-drain area; Form the first grid side wall in dummy grid stacked structure both sides; Forming material at the first grid side wall is the second grid side wall of DLC; Form source metal and miss contact area; Form stress and cover insulating barrier; Form ground floor insulation spacer medium layer, and planarization; Remove the dummy grid stacked structure, form gate stack structure.
The present invention also provides a kind of MOSFET manufacture method, may further comprise the steps: form gate stack structure at substrate; Form the first grid side wall in the gate stack structure both sides; Forming material at the first grid side wall is the second grid side wall of DLC; In the substrate of second grid side wall both sides, form source-drain area.
Wherein, sp among the DLC of second grid side wall
3The content of key at least greater than 50%, hydrogen atom content is less than 40%, nitrogen atom content is less than 20%, intrinsic stress is not less than 2GPa.
Wherein, deposit formation DLC film by magnetic filtered pulse cathodic vacuum arc discharge (FCVA), PECVD, magnetron sputtering, then adopt O
2And/or Ar plasma dry etching forms the second grid side wall that is positioned on the first grid side wall horizontal component.
Wherein, groove is leaked in etched substrate formation source, thereby leaks in the groove epitaxial growth SiGe in the source or SiC forms embedded strained source drain region.
Wherein, adopt high temperature rapid thermal annealing to improve or change stress to the surface of gate stack structure.
Wherein, after the formation gate stack structure or after the formation source-drain area, form source drain contact metal silicide at source-drain area, then form contact etch stop layer at source drain contact metal silicide, the first and second grid curb walls and gate stack structure.Wherein, drain contact metal silicide in source comprises CoSi
2, TiSi
2, NiSi, PtSi, NiPtSi, CoGeSi, TiGeSi, NiGeSi, the contact etch stop layer material is heavily stressed silica, silicon nitride or DLC.
According to heavily stressed MOSFET of the present invention and manufacture method thereof, adopt heavily stressed DLC film as grid curb wall, shortened the distance of stressor layers and channel region, effectively promoted the channel region carrier mobility, improved device performance.
Purpose of the present invention, and in these other unlisted purposes, in the scope of the application's independent claims, satisfied.Embodiments of the invention are limited in the independent claims, and specific features is limited in its dependent claims.
Description of drawings
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Fig. 8 is the generalized section according to each step of manufacture method of the rear grid technique of heavily stressed MOSFET of the present invention; And
Fig. 9 to Figure 13 is the generalized section according to each step of manufacture method of the front grid technique of heavily stressed MOSFET of the present invention.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail referring to accompanying drawing and in conjunction with schematic embodiment, can effectively control channel stress, improve Novel MOS FET and manufacture method thereof that carrier mobility is improved device performance thereby disclose.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These are modified is not space, order or the hierarchical relationship of hint institute's modification device architecture or manufacturing process unless stated otherwise.
Describe each step of manufacture method according to heavily stressed MOSFET of the present invention in detail hereinafter with reference to the generalized section of Fig. 1 to Fig. 8, wherein especially, described method is preferably applied in rear grid technique (gate-last).
At first, with reference to Fig. 1, form gate stack structure 20 at substrate 10.At first, provide substrate 10.Substrate 10 needs and choose reasonable according to the device purposes, can comprise monocrystalline silicon (Si), silicon-on-insulator (SOI), monocrystal germanium (Ge), germanium on insulator (GeOI), strained silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, for example gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon back semiconductor for example Graphene, SiC, carbon nanotube etc.Secondly, in substrate 10, form shallow trench isolation from (STI) 11, forming shallow trenchs such as first photoetching/etched substrate 10 then adopts the routine techniquess deposition insulation isolated material such as LPCVD, PECVD and cmp planarization until expose substrate 10, form STI 11, wherein the packing material of STI 11 can be oxide, nitride or nitrogen oxide.Again, also be that substrate 10 and STI 11 surfaces deposit gate insulating film 21 and grid material 22 and etching formation gate stack structure 20 successively in whole wafer surface.Wherein for rear grid technique, gate stack structure 20 is dummy grid stacked structures, to remove in subsequent technique, so gate insulating film 21 is preferably the bed course of silica, dummy grid material 22 is preferably polysilicon, amorphous silicon or microcrystal silicon or even silica.For front grid technique, gate stack structure 20 will keep in subsequent technique, therefore gate insulating film 21 is preferably silica, the nitrating silica, silicon nitride, or other hafnium, high k material includes but not limited to comprise and is selected from HfO2, HfSiOx, HfSiON, HfAlOx, HfTaOx, HfLaOx, HfAlSiOx, the hafnium sill of HfLaSiOx (wherein, each material is different according to multi-element metal component proportion and chemical valence, oxygen atom content x can rationally adjust, for example can be 1～6 and be not limited to integer), or comprise and be selected from ZrO2, La2O3, LaAlO3, TiO2, the rare earth based high K dielectric material of Y2O3, or comprise Al2O3, with the composite bed of its above-mentioned material; 22 of grid materials can be polysilicon, poly-SiGe or metal, wherein metal can comprise metal simple-substance or the alloy of these metals and the nitride of these metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, also can be doped with the elements such as C, F, N, O, B, P, As in the grid material 22 with the regulatory work function.
Secondly, with reference to Fig. 2, form dummy grid side wall 23 in dummy grid stacked structure 20 both sides.For example the spacer material layer of device surface cvd silicon oxide, silicon nitride or its composite bed then etching form dummy grid side wall 23.
Again, with reference to Fig. 3, in dummy grid side wall 23 both sides substrates 10, form source-drain area 30.The source-drain area 30 of traditional handicraft can be that the dopant implant ion forms in the substrate 10.In the preferred embodiment of the present invention, source-drain area 30 is embedded strained source drain regions, also namely take dummy grid side wall 23 as the mask etching substrate 10 formation sources leak groove, thereby then leak the embedded strained source drain region that epitaxial growth SiGe or SiC etc. are different from substrate 10 materials in the groove heavily stressed materials form corresponding material in the source.Wherein the upper surface in embedded strained source drain region 30 is not limited to shown in Figure 3 and substrate 10 upper surface flush, but can be higher than substrate 10 upper surfaces, forms the lifting source and leaks.Preferably, also can be to dopant implant ion in the embedded strained source drain region 30 to regulate type and concentration; Above-mentioned embedded source is leaked and is mixed simultaneously corresponding NMOS Doping Phosphorus, arsenic, antimony etc., PMOS doped with boron, aluminium, gallium, indium etc.
Then, with reference to Fig. 4, remove dummy grid side wall 23 and in the substrate 10 of dummy grid stacked structure 20 both sides, form source and drain extension 31.Can remove by wet etching the dummy grid side wall 23 of silicon nitride or silicon oxynitride, then carry out the source and leak Implantation, form the source and drain extension 31 of light dope (LDD).
Then, with reference to Fig. 5, form grid curb wall structure 40 in dummy grid stacked structure 20 both sides.Wherein, grid curb wall structure 40 comprises first grid side wall 41 and second grid side wall 42 at least.At first form first grid side wall 41, by traditional handicraft deposition first grid spacer material, can be silica (SiO at device surface
x) or silicon nitride (SiN
x, x can be 1～2, is not limited to integer) or silicon oxynitride (SiO
xN
yX, y can rationally adjust according to needs), also can be the stacking of these materials, then control etching mask domain and etching technics parameter so that the section shape of the first grid side wall 41 that etching obtains is L shaped, also namely comprise the vertical component that directly contacts with dummy grid stacked structure 20, and the horizontal component that directly contacts with embedded strained source drain region 30 and/or source and drain extension 31.First grid side wall 41 is as the resilient coating of heavily stressed side wall, and its thickness is preferably 1～25nm, and thinner thickness is conducive to the stress transmission.
Form after the first grid side wall 41, form again second grid side wall 42.Form diamond like carbon amorphous carbon (DLC) film that has than high intrinsic by the low temperature methods such as magnetic filtered pulse cathodic vacuum arc discharge (FCVA), PECVD, magnetron sputtering deposition, then adopt O
2And/or Ar plasma dry etching forms the second grid side wall 42 be positioned on first grid side wall 41 horizontal components, and to make its section shape be subtriangular or 1/4 ellipse.Wherein, because the material behavior of DLC film depends on sp to a great extent
3The content of key, higher sp
3The content of key is so that the DLC structure more is similar to diamond rather than graphite, and therefore in order to improve intrinsic stress, control technological parameter in the preferred embodiment of the present invention is so that sp among the DLC
3The content of key at least greater than 50%, hydrogen atom content is less than 40%, nitrogen atom content is less than 20%, so so that be not less than 2GPa and be preferably 4～10GPa as the DLC film intrinsic stress of second grid side wall 42.The thickness of second grid side wall 42 is preferably 2～60nm.The stress of the CESL of traditional SiN material only is 2.4～3.5GPa, and the DLC intrinsic stress is larger among the present invention, and the second grid side wall 42 of DLC and substrate channel region are separated with the thinner first grid side wall 41 as resilient coating between only, therefore than traditional structure, MOSFET of the present invention can provide higher stress to channel region, thereby improves carrier mobility, improve device performance.The DLC film is tensile stress for nMOS, and the DLC film is compression for pMOS, and therefore second grid side wall 42 will form at twice with difference proof stress kind and size in the manufacturing process of cmos device.
Subsequently, carry out subsequent technique with reference to Fig. 6 and Fig. 7, comprise formation source drain contact metal silicide 60; Form contact etching stop layer (CESL) 70, this layer possesses higher stress simultaneously; Form an I LD80, and use planarization such as CMP to make it planarization, make it simultaneously the top concordant with dummy grid stacked structure 20 tops; Selective etching is removed dummy grid stacked structure 20, is formed gate stack structure 50;
Particularly, take the first and second grid curb walls 41/42 as mask, carry out self-alignment silicide technology, film at whole device surface deposition Pt, Co, the metal or metal alloy such as Ni, Ti, then the high temperature anneal is so that contained silicon and metal react and generate such as CoSi in the embedded strained source drain region 30
2, TiSi
2, NiSi, PtSi, NiPtSi, CoGeSi, the source drain contact metal silicides 60 such as TiGeSi, NiGeSi to be reducing source-drain contact resistance, thereby further improve device performance.
After the formation source drain contact metal silicide 60, form contact etching stop layer (CESL) 70 in whole device surface deposition, also be that CESL 70 is positioned on STI 11, source drain contact metal silicide 60, second grid side wall 42, the gate material layers 52, its material can be to have heavily stressed traditional SiOx, SiN
xMaterial, or aforesaid heavily stressed DLC.CESL 70 provides extra stress to strengthen, and has further increased channel region stress.Particularly, CESL70 so-called heavily stressed be that the intrinsic stress of material is greater than 1GPa, and preferably between 2～10GPa in the present invention.
Deposit ground floor insulation spacer medium layer 80 is used for rear grid technique, and this layer can be silica, phosphorosilicate glass, fluorine-doped silica, carbon doped silicon oxide, silicon nitride or low-k material, perhaps MULTILAYER COMPOSITE layer; Use CMP, the method planarizations 80 such as dry back quarter make it upper surface concordant with dummy grid stacked structure 20 tops.
Remove dummy grid stacked structure 20 by wet etching, stay gate trench.Then by the gate insulator 51 of method cvd silicon oxide, nitrating silica, silicon nitride or other hafniums in gate trench such as PECVD, HDPCVD, ALD, gate insulator 51 can only be positioned at the gate trench bottom also can be positioned at gate trench bottom and sidewall.Gate insulator 51 used high k materials include but not limited to comprise the hafnium sill that is selected from HfO2, HfSiOx, HfSiON, HfAlOx, HfTaOx, HfLaOx, HfAlSiOx, HfLaSiOx, or comprise the rare earth based high K dielectric material that is selected from ZrO2, La2O3, LaAlO3, TiO2, Y2O3, or comprise Al2O3, with the composite bed of its above-mentioned material.Gate insulator 51 is by conventional method deposition of gate material layers 52 such as PVD, CVD, ALD in gate trench, gate material layers 52 can comprise the metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, also can be In
2O
3, SnO
2, the conductor metal oxides such as ITO, IZO, can also be the polysilicon that mixes, amorphous silicon, polycrystalline germanium, poly-SiGe etc.Can mix the elements such as C, F, N, O, B, P, As in the gate material layers 52.Also preferably form the barrier layer 53 of nitride between gate material layers 52 and the gate insulator 51 by conventional methods such as PVD, CVD, ALD, barrier layer 53 materials are M
xN
y, M
xSi
yN
z, M
xAl
yN
z, M
aAl
xSi
yN
z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.More preferably, gate material layers 52 not only adopts stacked up and down lamination layer structure with barrier layer 53, can also adopt the dopant implant layer structure that mixes, the material that also namely consists of gate material layers 52 and barrier layer 53 is deposited on the gate insulator 51 simultaneously, so gate material layers comprises the material on above-mentioned barrier layer.Whole device surface preferably adopts the high temperature rapid thermal annealing that for example comprises laser annealing, Spike annealing to improve or change stress.As mentioned above, gate insulator 51, gate material layers 52 and barrier layer 53 common formation gate stack structures 50.
At last, with reference to Fig. 8, finish the device manufacturing.Form the second inter-level dielectric (ILD) 82 and cmp planarization in whole device surface deposition, etching the one ILD80, the 2nd ILD 82 and CESL70 form drain contact hole, source with source of exposure drain contact metal silicide 60, and deposition contacting metal formation source leakage metal closures 90 and cmp planarization are until expose ILD 82.
The final MOSFET device architecture that forms as shown in Figure 8, comprise the grid curb wall structure 40 that is consisted of by first grid side wall 41 and second grid side wall 42 of gate stack structure 50 on substrate 10, the substrate 10, gate stack structure 50 both sides, the source-drain area 30 in the grid curb wall structure 40 both sides substrates 10, wherein, second grid side wall 42 comprises DLC.Gate stack structure 50 comprises gate insulator 51, gate material layers 52 and barrier layer 53, wherein barrier layer 53 can be positioned at the top of gate insulator 51, the bottom of gate material layers 52 and sidepiece can be blocked layer 53 parcel, and perhaps gate material layers 52 is mixed mutually with the material on barrier layer 53.Source-drain area 30 is embedded strained source drain region, and source-drain area 30 also has source and drain extension 31 along channel direction, and source and drain extension 31 is positioned at grid curb wall structure 40 belows.First grid side wall 41 is L shaped, comprises vertical component and horizontal component, and second grid side wall 42 is positioned on this horizontal component.Has source drain contact metal silicide 60 on the source-drain area 30.CESL 70 covers STI 11, source drain contact metal silicide 60, second grid side wall 42 and gate material layers 52.Double-deck ILD 80/82 covers CESL 70, and source leakage metal closures 90 passes ILD 80/82 and CESL 70 contacts with source drain contact metal silicide 60.Described in the material of above-mentioned each member such as the aforementioned manufacture method, do not repeat them here.
It should be noted that above-mentioned Fig. 1 to Fig. 8 technique is corresponding to rear grid technique.For front grid technique, corresponding manufacture method change is as follows:
With reference to Fig. 9, form gate stack structure 50 at substrate 10, comprise successively gate insulator 51, barrier layer 53 and the gate material layers 52 of horizontal stacking.Gate stack structure 50 various piece materials are same as shown in Figure 7, repeat no more.Its process sequence is identical with rear grid technique, except planarization and the gate electrode of an ILD80 are removed technique.
With reference to Figure 10, form pseudo-side wall (not shown) in gate stack structure 50 both sides, to carry out the source-drain structure making and comprise embedded SiGe or SiC structure 30 etc., the formation method repeats no more with identical shown in Fig. 3,4.Then form source and drain extension 31 in gate stack structure 50 both sides.
With reference to Figure 11, form grid curb wall structure 40 in gate stack structure 50 both sides.Comprise forming first L shaped first grid side wall 41, and then form the second grid side wall 42 of heavily stressed DLC at first grid side wall 41.
Then, with reference to Figure 12, be similar to Fig. 6,7, form source drain contact metal silicide 60 and form contact etching stop layer (CESL) 70.From different shown in Fig. 6,7 be, the gate stack structure 50 of front grid technique is slightly had any different with Fig. 6,7 rear grid techniques among Figure 12, also namely before the gate stack structure 50 of grid technique be three layer 51/53/52 of horizontal stacking, rather than the rear U-shaped encirclement structure of grid technique.60/70 layer of structure of among Figure 12 those, material and formation method are identical with the first half of Fig. 6,7 rear grid techniques, repeat no more.
At last, with reference to Figure 13, finish the device manufacturing.Form inter-level dielectric (ILD) 80 and cmp planarization in whole device surface deposition, etching ILD 80 and CESL70 form drain contact hole, source with source of exposure drain contact metal silicide 60, and deposition contacting metal formation source leakage metal closures 90 and cmp planarization are until expose ILD 80.
The device architecture that forms by front grid method as shown in figure 13, comprise the grid curb wall structure 40 that is consisted of by first grid side wall 41 and second grid side wall 42 of gate stack structure 50 on substrate 10, the substrate 10, gate stack structure 50 both sides, the source-drain area 30 in the grid curb wall structure 40 both sides substrates 10, wherein, second grid side wall 42 comprises DLC.Gate stack structure 50 comprises successively gate insulator 51, barrier layer 53 and the gate material layers 52 of horizontal stacking.Source-drain area 30 is embedded strained source drain region, and source-drain area 30 also has source and drain extension 31 along channel direction, and source and drain extension 31 is positioned at grid curb wall structure 40 belows.First grid side wall 41 is L shaped, comprises vertical component and horizontal component, and second grid side wall 42 is positioned on this horizontal component.Has source drain contact metal silicide 60 on the source-drain area 30.CESL 70 covers STI 11, source drain contact metal silicide 60, second grid side wall 42 and gate material layers 52.Individual layer ILD 80 covers CESL70, and source leakage metal closures 90 passes ILD 80 and CESL 70 contacts with source drain contact metal silicide 60.Described in the material of above-mentioned each member such as the aforementioned manufacture method, do not repeat them here.
In addition, although only shown the MOSFET schematic diagram of planar channeling in the accompanying drawing of the present invention, what those skilled in the art should know is that the heavily stressed sidewall structure of DLC of the present invention also can be applicable to other device architectures such as three-dimensional multiple-grid, vertical-channel, nano wire.
In addition, although only shown the MOSFET schematic diagram of the single raceway groove in plane in the accompanying drawing of the present invention, what those skilled in the art should know is that the heavily stressed sidewall structure of DLC of the present invention also can be applicable to other device architectures such as PMOS, NMOS, CMOS.
According to heavily stressed MOSFET of the present invention and manufacture method thereof, adopt heavily stressed DLC film as grid curb wall, shortened the distance of stressor layers and channel region, effectively promoted the channel region carrier mobility, improved device performance.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and device architecture is made various suitable changes and equivalents.In addition, can be made by disclosed instruction and manyly may be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, purpose of the present invention does not lie in to be limited to as being used for and realizes preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.
Claims (18)
1. MOSFET, comprise the gate stack structure on substrate, the substrate, the grid curb wall structure of gate stack structure both sides, the source-drain area in the substrate of grid curb wall structure both sides, it is characterized in that: the grid curb wall structure comprises first grid side wall and second grid side wall, and the material of second grid side wall is DLC.
2. MOSFET as claimed in claim 1, wherein, sp among the DLC of second grid side wall
3The content of key at least greater than 50%, hydrogen atom content is less than 40%, nitrogen atom content is less than 20%, intrinsic stress is not less than 2GPa.
3. MOSFET as claimed in claim 1, wherein, the first grid side wall comprises vertical component and horizontal component, the second grid side wall is positioned on the horizontal component of first grid side wall.
4. MOSFET as claimed in claim 1, wherein, the material of first grid side wall is silica and/or silicon nitride.
5. MOSFET as claimed in claim 1, wherein, the thickness of first grid side wall is 1～25nm, the thickness of second grid side wall is 2～60nm.
6. MOSFET as claimed in claim 1, wherein, gate stack structure comprises gate insulator, gate material layers and barrier layer; Gate insulator comprises silica, nitrating silica, silicon nitride, hafnium and combination thereof; Gate material layers comprises the metal that is selected from Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, or comprises and be selected from In
2O
3, SnO
2, ITO, IZO conductor metal oxide, or the polysilicon, amorphous silicon, polycrystalline germanium, the poly-SiGe that mix, or M
xN
y, M
xSi
yN
z, M
xAl
yN
z, M
aAl
xSi
yN
z, wherein M comprises Ta, Ti, Hf, Zr, Mo, W, or the composite bed of above-mentioned material; Substrate comprises silicon, germanium, strained silicon, germanium silicon, compound semiconductor, carbon back semi-conducting material and combination thereof.
7. MOSFET as claimed in claim 6, wherein, high k material comprises the hafnium sill that is selected from HfO2, HfSiOx, HfSiON, HfAlOx, HfTaOx, HfLaOx, HfAlSiOx, HfLaSiOx, or comprise the rare earth based high K dielectric material that is selected from ZrO2, La2O3, LaAlO3, TiO2, Y2O3, or comprise Al2O3, with the composite bed of its above-mentioned material.
8. MOSFET as claimed in claim 1, wherein, source-drain area is embedded SiGe or SiC, and source-drain area also has source and drain extension along channel direction, and source and drain extension is positioned at grid curb wall structure below.
9. MOSFET as claimed in claim 1 wherein, has source drain contact metal silicide on the source-drain area, and contact etch stop layer covers source drain contact metal silicide, grid curb wall structure and gate stack structure.
10. MOSFET as claimed in claim 9, wherein, source drain contact metal silicide comprises CoSi
2, TiSi
2, NiSi, PtSi, NiPtSi, CoGeSi, TiGeSi, NiGeSi, the contact etch stop layer material is heavily stressed silica, silicon nitride or DLC.
11. a MOSFET manufacture method may further comprise the steps:
Form the dummy grid stacked structure at substrate;
In the substrate of dummy grid stacked structure both sides, form source-drain area;
Form the first grid side wall in dummy grid stacked structure both sides;
Forming material at the first grid side wall is the second grid side wall of DLC;
Form source metal and miss contact area;
Form stress and cover insulating barrier;
Form ground floor insulation spacer medium layer, and planarization;
Remove the dummy grid stacked structure, form final gate stack structure.
12. a MOSFET manufacture method may further comprise the steps:
Form gate stack structure at substrate;
Form the first grid side wall in the gate stack structure both sides;
Forming material at the first grid side wall is the second grid side wall of DLC;
In the substrate of second grid side wall both sides, form source-drain area.
13. such as the MOSFET manufacture method of claim 11 or 12, wherein, sp among the DLC of second grid side wall
3The content of key at least greater than 50%, hydrogen atom content is less than 40%, nitrogen atom content is less than 20%, intrinsic stress is not less than 2GPa.
14. such as the MOSFET manufacture method of claim 11 or 12, wherein, deposit formation DLC film by magnetic filtered pulse cathodic vacuum arc discharge (FCVA), PECVD, magnetron sputtering, then adopt O
2And/or Ar plasma dry etching forms the second grid side wall that is positioned on the first grid side wall horizontal component.
15. such as the MOSFET manufacture method of claim 11 or 12, wherein, groove is leaked in etched substrate formation source, thereby leaks in the groove epitaxial growth SiGe in the source or SiC forms embedded strained source drain region.
16. such as the MOSFET manufacture method of claim 11 or 12, wherein, adopt high temperature rapid thermal annealing to improve or change stress to whole device surface.
17. the MOSFET manufacture method such as claim 11 or 12, wherein, after the formation gate stack structure or after the formation source-drain area, form source drain contact metal silicide at source-drain area, then form contact etch stop layer at source drain contact metal silicide, the first and second grid curb walls and gate stack structure, this layer possesses heavily stressed simultaneously.
18. such as the MOSFET manufacture method of claim 17, wherein, source drain contact metal silicide comprises CoSi
2, TiSi
2, NiSi, PtSi, NiPtSi, CoGeSi, TiGeSi, NiGeSi, the contact etch stop layer material is heavily stressed silica, silicon nitride or DLC.
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