CN114695115A - Semiconductor device with fin structure and preparation method thereof - Google Patents
Semiconductor device with fin structure and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000002360 preparation method Methods 0.000 title abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims description 48
- 229910002601 GaN Inorganic materials 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000002161 passivation Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 238000003780 insertion Methods 0.000 claims description 7
- 230000037431 insertion Effects 0.000 claims description 7
- 229910052594 sapphire Inorganic materials 0.000 claims description 7
- 239000010980 sapphire Substances 0.000 claims description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 150000002902 organometallic compounds Chemical class 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 24
- 238000009826 distribution Methods 0.000 abstract description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 17
- 230000008569 process Effects 0.000 description 16
- 238000001312 dry etching Methods 0.000 description 8
- 230000005533 two-dimensional electron gas Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- -1 trimethylaluminum Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract
The application discloses a semiconductor device with a fin structure and a preparation method thereof, which relate to the field of semiconductors and comprise the steps of obtaining a substrate with a patterned polarity adjusting layer; growing a fin type heterojunction by adjusting the input ratio of the group V source and the group III source, wherein the fin type heterojunction comprises a nitrogen polarity heterojunction in a region of the substrate which is not covered by the patterned polarity adjusting layer and a metal polarity heterojunction positioned on the patterned polarity adjusting layer, and the heights of the nitrogen polarity heterojunction and the metal polarity heterojunction are different; and preparing electrodes to obtain the semiconductor device with the fin structure. The graphical polarity adjusting layer can control the distribution of the metal polarity heterojunction and the nitrogen polarity heterojunction, the growth heights of the metal polarity heterojunction and the nitrogen polarity heterojunction are different under the input ratios of different V-group sources and III-group sources, the fin type heterojunction can be directly grown, etching is not needed, damage caused by etching can be avoided, a channel leakage channel caused by etching damage is also avoided, and off-state leakage current is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device having a fin structure and a method for fabricating the same.
Background
With the development of semiconductor technology, a device structure evolves from a planar structure to a fin type three-dimensional channel structure, the fin type channel structure enables the contact area of a gate electrode and a channel layer to be increased, and an electron depletion region is further increased, so that the semiconductor device has stronger grid control capability, and the electric leakage problem caused by a short channel effect is effectively improved.
At present, a fin structure of a semiconductor device is formed by a top-down dry etching process, after an epitaxial plane structure is manufactured, a mask is manufactured by a photoetching process, and a three-dimensional channel is etched by a dry method to obtain a fin structure transistor. The dry etching introduces a high-density defect state on the etching surface, and the donor-like defect state causes serious leakage current, so that the off-state leakage current and the power consumption of the device are increased. When the damage of the dry etching is too large, the electric leakage of the device is serious, and even the device is difficult to turn off. At present, although etching damage can be reduced by wet solution etching, dielectric layer passivation and other processes, high-density etching damage is still difficult to remove fundamentally, and the etching cost is also high.
Therefore, how to provide a device manufacturing method without etching damage needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a semiconductor device with a fin structure and a manufacturing method thereof, so as to remove damage caused by etching.
In order to solve the above technical problem, the present application provides a method for manufacturing a semiconductor device having a fin structure, including:
obtaining a substrate on which a patterned polarity adjustment layer is formed;
growing a fin heterojunction by adjusting an input ratio of a group V source and a group III source, wherein the fin heterojunction comprises a nitrogen polarity heterojunction in a region of the substrate not covered by the patterned polarity adjusting layer and a metal polarity heterojunction on the patterned polarity adjusting layer, and the nitrogen polarity heterojunction and the metal polarity heterojunction are different in height;
and preparing electrodes to obtain the semiconductor device with the fin structure.
Optionally, when the height of the metal polar heterojunction is higher than that of the nitrogen polar heterojunction, the input ratio of the group v source to the group iii source is below 2500, and the fin heterojunction includes a buffer layer, a channel layer and a barrier layer which are stacked next to each other away from the group v source and the group iii source.
Optionally, when the height of the metal polar heterojunction is lower than that of the nitrogen polar heterojunction, the input ratio of the group v source to the group iii source is greater than 2500, and the fin heterojunction includes a buffer layer, a back barrier layer, and a channel layer that are sequentially stacked in a direction away from the substrate.
Optionally, the fin heterojunction further comprises an insertion layer.
Optionally, the growing the fin heterojunction includes:
and epitaxially growing the fin heterojunction by adopting a metal organic compound chemical vapor deposition method, a molecular beam epitaxy method or a magnetron sputtering method.
Optionally, a height difference between the nitrogen polar heterojunction and the metal polar heterojunction is within 500 nm.
Optionally, the substrate is any one of a gallium nitride substrate, a diamond substrate, a sapphire substrate, a SiC substrate, and a Si substrate.
Optionally, the width of a fin in the fin heterojunction is between 5nm and 3 μm.
Optionally, after preparing the electrode, the method further comprises:
and depositing a passivation layer on the surface of the semiconductor device with the fin structure.
The application also provides a semiconductor device with a fin structure, which is manufactured by adopting any one of the manufacturing methods of the semiconductor device with the fin structure.
The application provides a preparation method of a semiconductor device with a fin structure, which comprises the following steps: obtaining a substrate on which a patterned polarity adjustment layer is formed; growing a fin heterojunction by adjusting an input ratio of a group V source and a group III source, wherein the fin heterojunction comprises a nitrogen polarity heterojunction in a region of the substrate not covered by the patterned polarity adjusting layer and a metal polarity heterojunction on the patterned polarity adjusting layer, and the nitrogen polarity heterojunction and the metal polarity heterojunction are different in height; and preparing electrodes to obtain the semiconductor device with the fin structure.
Therefore, when the fin type structure in the semiconductor device is prepared, the substrate with the patterned polarity adjusting layer is obtained, the patterned polarity adjusting layer can control the distribution of the metal polarity heterojunction and the nitrogen polarity heterojunction in the fin type heterojunction, the growth heights of the metal polarity heterojunction and the nitrogen polarity heterojunction are different under different input ratios of the group V source and the group III source, the fin type heterojunction directly grows in the region, which is not subjected to the patterned polarity adjusting layer, of the patterned polarity adjusting layer and the substrate by adjusting the input ratio of the group V source and the group III source, the fin type heterojunction can be obtained without etching, the damage caused by etching can be avoided, the etching cost can be reduced, the channel leakage channel caused by etching damage is also avoided, the off-state leakage current is further improved, and the breakdown characteristic of the semiconductor device is enhanced, The power consumption is reduced.
In addition, the application also provides a semiconductor device with the fin type structure, which has the advantages.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for fabricating a semiconductor device having a fin structure according to an embodiment of the present disclosure;
figure 2 is a schematic diagram of the input ratio of group v and group iii sources as provided by the present application for metal and nitrogen polarity heterojunction height difference adjustment;
FIG. 3 is a schematic structural diagram of a fin AlGaN/GaN heterojunction according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a fin GaN/AlGaN heterojunction according to an embodiment of the present application;
fig. 5 to 11 are process flow diagrams of a semiconductor device having a fin structure according to an embodiment of the present disclosure;
fig. 12-14 are partial process flow diagrams of another semiconductor device with a fin structure according to an embodiment of the present disclosure;
in the figure: 1. the structure comprises a substrate, 2 parts of a patterned polarity adjusting layer, 3 parts of a buffer layer, 4 parts of a channel layer, 5 parts of a barrier layer, 6 parts of two-dimensional electron gas, 7 parts of a gate dielectric layer, 8 parts of a gate electrode, 9 parts of an insertion layer, 10 parts of a passivation layer, 2 'parts of a polarity adjusting layer, 5' parts of a back barrier layer, A parts of a metal polarity heterojunction and B parts of a nitrogen polarity heterojunction.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background section, the fin structure of the semiconductor device is formed by a top-down dry etching process, the dry etching introduces a high-density defect state on the etching surface, and the donor-like defect state causes a severe leakage current, thereby increasing the off-state leakage current and power consumption of the device. Although the etching damage can be reduced by wet solution etching, dielectric layer passivation and other processes, the high-density etching damage is still difficult to remove fundamentally, and the etching cost is also high.
In view of the above, the present application provides a method for manufacturing a semiconductor device having a fin structure, with reference to fig. 1, including:
step S101: a substrate formed with a patterned polarity-adjusting layer is obtained.
Optionally, the present step includes:
step S1011: preparing a clean substrate;
step S1012: and depositing a polarity adjusting layer on the upper surface of the substrate, and etching the polarity adjusting layer by adopting a wet etching or dry etching mode to form the graphical polarity adjusting layer.
Wherein the substrate includes, but is not limited to, any one of a gallium nitride substrate, a diamond substrate, a sapphire substrate, a SiC substrate, and a Si substrate. The patterned polarity adjusting layer can be an AlN layer, a GaN layer or Al2O3Layers, and the like.
Step S102: growing a fin heterojunction by adjusting an input ratio of a group V source and a group III source, wherein the fin heterojunction comprises a nitrogen polarity heterojunction in a region of the substrate not covered by the patterned polarity adjusting layer and a metal polarity heterojunction located on the patterned polarity adjusting layer, and heights of the nitrogen polarity heterojunction and the metal polarity heterojunction are different.
It should be noted that, in the present application, the growth manner of the fin heterojunction is not limited, and can be selected by itself. For example, the fin-type heterojunction can be epitaxially grown by a Metal Organic Chemical Vapor Deposition (MOCVD) method, a Molecular Beam Epitaxy (MBE) method, or a magnetron sputtering method.
Optionally, the difference in height between the nitrogen polar heterojunction and the metal polar heterojunction may be within 500 nm. The width of a fin in the fin heterojunction can be 5 nm-3 mu m, wherein the width direction is the direction vertical to the growth direction of the fin heterojunction.
For a heterojunction of GaN and AlGaN, the group v source may be ammonia and the group iii source may be a metal organic compound, such as trimethylaluminum, or the like.
Due to the difference of the metal polarity and the nitrogen polarity surface energy, the two polarity regions have different rates of adsorbing growth molecules and nucleating on the surface during growth. Therefore, the growth speed of the metal polar heterojunction and the nitrogen polar heterojunction is controlled by adjusting the input ratio of the group V source and the group III source in epitaxial growth, and the fin structure is obtained.
A schematic diagram of adjusting the input ratio of the group v source and the group iii source for the height difference of the metal polar heterojunction and the nitrogen polar heterojunction is shown in fig. 2, wherein the abscissa is the input ratio of the group v source and the group iii source, and the ordinate is the height difference of the nitrogen polar heterojunction and the metal polar heterojunction, and when the group v source and the group iii source are lower than 2500, the desorption probability of the organic metal molecules of the metal polar heterojunction after being adsorbed on the substrate is less, so that the nucleation growth rate is higher, and the height of the metal polar heterojunction is also larger; when the input ratio of the group V source to the group III source is higher than 2500, the nucleation growth rate of the nitrogen polar heterojunction is higher, and the growth mode at the moment shows that the nitrogen polar heterojunction grows faster, so that the height of the nitrogen polar heterojunction is higher under the growth condition.
For different heterojunctions, the height relationship between the metal polarity heterojunction and the nitrogen polarity heterojunction is different, and the input ratio of the group v source and the group iii source is different, and the heterojunction formed by GaN and AlGaN is taken as an example and respectively described below.
First, referring to fig. 3, when the fin heterojunction is an AlGaN/GaN heterojunction, the height of the metal polar heterojunction a is higher than that of the nitrogen polar heterojunction B, the input ratio of the group v source to the group iii source is below 2500, and the fin heterojunction includes a buffer layer 3, a channel layer 4, and a barrier layer 5 sequentially stacked in a direction away from the substrate 1. Wherein the barrier layer 5 is made of AlGaN, the channel layer 4 is made of GaN, and the buffer layer 3 is made of AlxGa1-xN（0≤x≤1）。
The area corresponding to the patterned polarity adjusting layer 2 is a metal polarity heterojunction A, the area corresponding to the substrate 1 not covered by the patterned polarity adjusting layer 2 is a nitrogen polarity heterojunction B, and a channel layer 4 of the metal polarity heterojunction A induces two-dimensional electron gas 6, so that the area is higher in height; the nitrogen polarity heterojunction B is low in height and no two-dimensional electron gas 6 is generated.
In the AlGaN/GaN heterojunction, since the channel layer 4 and the buffer layer 3 occupy most of the thickness, the input ratio of the group v source and the group iii source in the epitaxial growth of these two parts can be mainly adjusted.
Further, the AlGaN/GaN heterojunction may further include an insertion layer between the barrier layer and the channel layer to adjust the alignment and uniformity of the interface and reduce scattering.
Secondly, referring to fig. 4, when the fin heterojunction is a GaN/AlGaN heterojunction, the height of the metal polar heterojunction a is lower than that of the nitrogen polar heterojunction B, the input ratio of the group v source to the group iii source is greater than 2500, and the fin heterojunction includes a buffer layer 3, a back barrier layer 5', and a channel layer 4 sequentially stacked in a direction away from the substrate 1. Wherein, the back barrier layer 5' is AlGaN, the channel layer 4 is GaN, and the buffer layer 3 is AlxGa1-xN（0≤x≤1）。
The area corresponding to the patterned polarity adjusting layer 2 is a metal polarity heterojunction A, the area corresponding to the substrate 1 not covered by the patterned polarity adjusting layer 2 is a nitrogen polarity heterojunction B, a channel layer 4 of the nitrogen polarity heterojunction B induces a two-dimensional electron gas 6, and the area is high in height; the metal polar heterojunction a has a low height and no two-dimensional electron gas 6 is generated.
Further, the GaN/AlGaN heterojunction can also comprise an insertion layer positioned between the back barrier layer and the channel layer so as to adjust the collimation and uniformity of an interface and reduce scattering.
Step S103: and preparing electrodes to obtain the semiconductor device with the fin structure.
The electrodes of the semiconductor device having the fin structure may include an ohmic electrode and a gate electrode, and at this time, the step may include:
step S1031: depositing an ohmic electrode and a gate dielectric layer on the substrate with the fin-type heterojunction, wherein the gate dielectric layer can reduce the leakage current of the device and adjust the threshold voltage;
step S1032: a gate electrode is deposited.
The fin heterojunction prepared in the application is suitable for high-voltage-resistant power devices, advanced-process GaN CMOS (Complementary Metal Oxide Semiconductor) logic circuits, low-power-consumption GaN monolithic microwave integrated circuits and the like. The type of the semiconductor device having the fin structure is not limited in the present application as long as the semiconductor device has a fin heterostructure, for example, a fin HEMT (High Electron Mobility Transistor) or the like.
The preparation method of the application obtains the substrate with the patterned polarity adjusting layer when the fin structure in the semiconductor device is prepared, the patterned polarity adjusting layer can control the distribution of the metal polarity heterojunction and the nitrogen polarity heterojunction in the fin type heterojunction, under different input ratios of the group V source and the group III source, the growth heights of the metal polar heterojunction and the nitrogen polar heterojunction are different, by adjusting the input ratio of the group V source and the group III source, fin type heterojunction is directly grown in the patterned polarity adjusting layer and the substrate in the region not subjected to the patterned polarity adjusting layer, a three-dimensional channel structure can be obtained without etching, the damage caused by etching can be avoided, the etching cost can be reduced, in addition, a channel leakage channel caused by etching damage is avoided, off-state leakage current is further improved, and the breakdown characteristic of the semiconductor device is enhanced and power consumption is reduced.
On the basis of the above embodiments, in an embodiment of the present application, the method for manufacturing a semiconductor device having a fin structure further includes, after the manufacturing of the electrode:
and depositing a passivation layer on the surface of the semiconductor device with the fin structure to protect the semiconductor device with the fin structure.
The following takes a fin-type HEMT device as an example, and further explains a method for manufacturing a semiconductor device having a fin-type structure in the present application.
Example 1 Fin HEMT device with AlGaN/GaN heterojunction
Step 1: the sapphire substrate 1 is cleaned, as shown in fig. 5.
Step 2: epitaxially growing a 20nm polarity-adjusted layer 2' on the sapphire substrate by using the MOCVD method, as shown in fig. 6; a patterned polarity adjusting layer (an active region is grown in a region where the polarity adjusting layer exists, and an isolation region is grown in a region where the polarity adjusting layer does not exist) is prepared by using a photolithography process, the patterned polarity adjusting layer with the characteristic dimension of micron to submicron corresponding to the three-dimensional channel structure is included, and the polarity adjusting layer outside the active region is removed by using a dry etching technology, so that the substrate 1 with the patterned polarity adjusting layer 2 is obtained, as shown in fig. 7.
And step 3: based on the substrate 1 with the patterned polarity adjusting layer 2 prepared in the step 2, AlGaN/GaN heterojunction with a transverse polarity structure is epitaxially grown in MOCVD, and the AlGaN/GaN heterojunction respectively has 20nm Al from top to bottom0.3Ga0.7An N-barrier layer 5, a 1nm AlN insertion layer 9, a 200nm GaN channel layer 4, and a 2 μm GaN high-resistance buffer layer 3, as shown in FIG. 8. The channel layer 4 and the buffer layer 3 occupy most of the thickness of the fin-type HEMT device, so the input ratio of the epitaxially grown group V source and the group III source of the two parts is mainly adjusted, the input ratio of the group V source and the group III source is adjusted to 2200 for growing the GaN channel layer 4 and the buffer layer 3, the barrier layer 5 and the insertion layer 9 grow normally, the metal polarity heterojunction A with a higher height can be obtained, namely the top of the fin-type structure, the nitrogen polarity heterojunction B with a lower height is obtained, namely the bottom of the fin-type structure, and the two-dimensional electron gas 6 exists in the GaN channel layer 4 of the metal polarity heterojunction A.
And 4, step 4: preparing Ti/Al/Ni/Au ohmic electrode region by using photoetching process and ohmic electrode process, and performing N reaction at 850 deg.C2And rapidly annealing for 30s under the atmosphere condition to obtain the ohmic electrode with low contact resistance.
And 5: preparation of 10nm SiN by LPCVD (Low Pressure Chemical Vapor Deposition)xAnd a gate dielectric layer 7 as shown in fig. 9.
Step 6: by using photolithography and electron beam process, a deposited Ni/Au gate electrode 8 is prepared, as shown in FIG. 10
And 7: based on PECVD (Plasma Enhanced Chemical Vapor Deposition, Plasma Enhanced chemistry)Vapor deposition) method for 300nm SiN depositionxPassivation layer 10, as shown in fig. 11.
Example 2 Fin HEMT device with GaN/AlGaN heterojunction
Step 1: the sapphire substrate 1 is cleaned, as shown in fig. 5.
And 2, step: epitaxially growing a 20nm polarity-adjusted layer 2' on the sapphire substrate by using the MOCVD method, as shown in fig. 6; a patterned polarity adjusting layer (an active region is grown in a region where the polarity adjusting layer exists, and an isolation region is grown in a region where the polarity adjusting layer does not exist) is prepared by using a photoetching process, the patterned polarity adjusting layer with the characteristic dimension of micron to submicron corresponding to the three-dimensional channel structure is included, and then the AlN crystal layer outside the active region is removed by using a dry etching technology, so that the substrate 1 with the patterned polarity adjusting layer 2 is obtained, as shown in fig. 7.
And step 3: based on the substrate 1 with the patterned polarity adjusting layer 2 prepared in the step 2, GaN/AlGaN heterojunction with a transverse polarity structure is epitaxially grown in MOCVD, and the GaN/AlGaN heterojunction is a 100nm GaN channel layer 4 and a 50nm Al layer from top to bottom respectively0.3Ga0.7An N back barrier layer 5', and a 2 μm GaN high resistance buffer layer 3, as shown in fig. 4. The input ratio of the group V source and the group III source is adjusted to 2800 to grow the GaN buffer layer 3, the back barrier layer 5' and the channel layer 4, and then the higher height of the nitrogen polarity heterojunction B, namely the top of the fin structure, and the lower area of the metal polarity heterojunction A, namely the bottom of the fin structure can be obtained, and at the moment, the two-dimensional electron gas 6 exists in the GaN channel layer 4 of the nitrogen polarity heterojunction B.
And 4, step 4: and preparing a Ti/Al/Ni/Au ohmic electrode region by utilizing a photoetching process and an ohmic electrode process, and rapidly annealing for 30s at 850 ℃ under the atmosphere of N2 to obtain the ohmic electrode with low contact resistance.
And 5: preparation of 10nm SiN by LPCVDxAnd a gate dielectric layer 7 as shown in fig. 12.
Step 6: the deposited Ni/Au gate electrode 8 is prepared using a photolithography process and an electron beam process, as shown in fig. 13.
And 7: 300nm SiN deposition based on PECVD methodxPassivation layers 10, e.g.As shown in fig. 14.
The application further provides a semiconductor device with a fin structure, which is manufactured by the method for manufacturing the semiconductor device with the fin structure according to any one of the embodiments.
The type of the semiconductor device having the fin structure is not limited in the present application as long as the semiconductor device has a fin heterostructure, for example, a fin HEMT (High Electron Mobility Transistor) or the like.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The semiconductor device with the fin structure and the method for manufacturing the same provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (10)
1. A method for manufacturing a semiconductor device with a fin structure is characterized by comprising the following steps:
obtaining a substrate on which a patterned polarity adjustment layer is formed;
growing a fin heterojunction by adjusting an input ratio of a group V source and a group III source, wherein the fin heterojunction comprises a nitrogen polarity heterojunction in a region of the substrate not covered by the patterned polarity adjusting layer and a metal polarity heterojunction on the patterned polarity adjusting layer, and the nitrogen polarity heterojunction and the metal polarity heterojunction are different in height;
and preparing electrodes to obtain the semiconductor device with the fin structure.
2. The method of manufacturing a semiconductor device having a fin structure according to claim 1, wherein an input ratio of the group v source to the group iii source is 2500 or less when a height of the metal polarity heterojunction is higher than a height of the nitrogen polarity heterojunction, and the fin heterojunction includes a buffer layer, a channel layer, and a barrier layer which are sequentially stacked in a direction away from the substrate.
3. The method of claim 1, wherein an input ratio of the group V source to the group III source is greater than 2500 when a height of the metal polarity heterojunction is less than a height of the nitrogen polarity heterojunction, and wherein the fin heterojunction comprises a buffer layer, a back barrier layer, and a channel layer stacked in that order in a direction away from the substrate.
4. The method of fabricating the semiconductor device with the fin structure of claim 1, wherein the fin heterojunction further comprises an insertion layer.
5. The method of fabricating the semiconductor device with the fin-type structure of claim 1, wherein the growing the fin-type heterojunction comprises:
and epitaxially growing the fin heterojunction by adopting a metal organic compound chemical vapor deposition method, a molecular beam epitaxy method or a magnetron sputtering method.
6. The method of claim 1, wherein a difference in height between the nitrogen polar heterojunction and the metal polar heterojunction is within 500 nm.
7. The method of manufacturing a semiconductor device having a fin structure according to claim 1, wherein the substrate is any one of a gallium nitride substrate, a diamond substrate, a sapphire substrate, a SiC substrate, and a Si substrate.
8. The method of claim 1, wherein the fin heterojunction has a fin width of between 5nm and 3 μm.
9. The method of fabricating the semiconductor device with the fin structure according to any one of claims 1 to 8, further comprising, after the fabricating the electrode:
and depositing a passivation layer on the surface of the semiconductor device with the fin structure.
10. The semiconductor device with the fin structure is prepared by the method for preparing the semiconductor device with the fin structure according to any one of claims 1 to 9.
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| US20100320505A1 (en) * | 2009-06-17 | 2010-12-23 | Fujitsu Limited | Semiconductor device and method for manufacturing the same, and amplifier |
| CN111029404A (en) * | 2018-10-09 | 2020-04-17 | 西安电子科技大学 | P-GaN/AlGaN/GaN enhancement device based on fin-shaped gate structure and manufacturing method thereof |
| CN113394096A (en) * | 2021-06-16 | 2021-09-14 | 中国科学院宁波材料技术与工程研究所 | HEMT device and self-isolation method and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100320505A1 (en) * | 2009-06-17 | 2010-12-23 | Fujitsu Limited | Semiconductor device and method for manufacturing the same, and amplifier |
| CN111029404A (en) * | 2018-10-09 | 2020-04-17 | 西安电子科技大学 | P-GaN/AlGaN/GaN enhancement device based on fin-shaped gate structure and manufacturing method thereof |
| CN113394096A (en) * | 2021-06-16 | 2021-09-14 | 中国科学院宁波材料技术与工程研究所 | HEMT device and self-isolation method and manufacturing method thereof |
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