CN108321200A - A kind of three-dimensional enhancement type high electron mobility transistor and its manufacturing method based on p-GaN structures - Google Patents

A kind of three-dimensional enhancement type high electron mobility transistor and its manufacturing method based on p-GaN structures Download PDF

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CN108321200A
CN108321200A CN201711462615.6A CN201711462615A CN108321200A CN 108321200 A CN108321200 A CN 108321200A CN 201711462615 A CN201711462615 A CN 201711462615A CN 108321200 A CN108321200 A CN 108321200A
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张凯
朱广润
孔岑
周建军
陈堂胜
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CETC 55 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The present invention relates to a kind of three-dimensional enhancement type high electron mobility transistor and its manufacturing method based on p GaN structures, its structure includes substrate, buffer layer, GaN base three-dimensional fin, grid, source electrode and drain electrode successively from bottom to top, it is characterized in that, further include built-in high resistant GaN area, it is located at the top of the lower section buffer layer adjacent with the two side areas of GaN base three-dimensional fin of the grid；The top of the GaN base three-dimensional fin and the growth of both sides secondary epitaxy have p GaN/AlGaN/GaN hetero-junctions；The grid is wrapped in the top and both sides of p GaN/AlGaN/GaN hetero-junctions, forms three-dimensional grid structure；The p GaN layers of grid two side areas being removed by etching mode by forming AlGaN/GaN hetero-junctions, the source electrode and drain electrode is respectively provided at the both ends of AlGaN/GaN hetero-junctions.The present invention can improve the threshold voltage and breakdown voltage of p GaN enhancement devices.

Description

A kind of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures and its Manufacturing method
Technical field
The invention belongs to technical field of semiconductor device preparation, more particularly to a kind of three-dimensional increasing based on p-GaN structures Strong type high electron mobility transistor and its manufacturing method.
Technical background
The advantages that due to the high breakdown field strength of third generation semiconductor GaN material, high saturated velocity, high temperature resistant, is based on GaN materials High electron mobility transistor prepared by material has many characteristics such as high-power, high efficiency, high speed, high-breakdown-voltage, is recognized To be the preferred material for manufacturing New-generation microwave and high-power electric and electronic.
Since polarity effect is in the 2DEG, conventional GaN of barrier layer and channel layer heterojunction boundary induction generation high concentration High electron mobility transistor is intrinsic to show as depletion-mode or normally opened work.And in power switch, electric vehicle, wireless charging Etc. in practical applications, often close pattern or enhanced GaN transistor for fail safe and simplify gate driving circuit structure, Reduce the selection that cost is optimal.However, can it is simple and effective, obtain high threshold voltage, high performance enhanced at low cost Device is still the ultimate challenge faced at present.At present it has been reported that multiple technologies realize the normal pass work of device, for example, Fluorine ion injection, p-GaN structures, ultra-thin barrier layer construction, dry method, wet method and electrochemical oxidation barrier layer, non-polar hetero knot Design, MIS slot grid etching, three-dimensional grid structure etc..
2008, MIS grooves grid structure that Japanese Tohru Oka et al. are proposed (referring to document Tohru Oka al., “AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications”,IEEE Electron Device Lett., Vol.29, no.7, pp.668-670,2008) it is to study one of relatively broad and potential structure at present, but there is etching The problems such as damage, the uncontrollable, interface stability of threshold value uniformity.
At present the most potential structure of industrial quarters be Toyota Company in 2007 propose p-GaN gate structures (referring to text Tohru Oka al. are offered, " Gate Injection Transistor (GIT)-A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation”,IEEE Electron Device Lett., vol.54,no.12,pp.3933-3935,2007).This structure under grid by forming p-type AlGaN or GaN layer to exhaust raceway groove Electronics realizes the enhancement device of higher thresholds.The problems such as stability of MIS slot grid structures is not present due to this structure, closely It gets the attention, quickly grows over year.However due to remaining thicker undoped AlGaN potential barriers below this structure grid Layer, and limited by p-type doping techniques, cause device threshold voltage relatively low.In order to improve threshold voltage, 2017 Hideyuki Okita et al. propose slot grid combination p-GaN structure (referring to document Hideyuki Okita al., “Through Recess and Regrowth Gate Technology for Realizing Process Stability of GaN-Based Gate Injection Transistors”,IEEE Trans.Electron Devices,vol.64, No.3, pp.1026-1031,2017), threshold value is increased to 2.3V from 1V.
In recent years, due to three-dimensional grid GaN device have better gate control ability and receive and pay close attention to, advantage it First, improving device threshold voltage and breakdown voltage (referring to document Kota Ohi al., " Drain by side grid ability Current Stability and Controllability of Threshold Voltage and Subthreshold Current in a Multi-Mesa-Channel AlGaN/GaN High Electron Mobility Transistor”, Japanese Journal of Applied Physics,vol.48,no. 8,pp.081002,2009).But existing three Dimension enhancement device is all based on Schottky junction structure or MOS/MIS structures (referring to document Ki-Sik Im al., " High- Performance GaN-Based Nanochannel FinFETs With/Without AlGaN/GaN Heterostructure”,IEEE Trans. Electron Devices,vol.60,no.10,pp.3012-3018, 2013) the problems such as, therefore there are operating voltage low and above-mentioned stability.
Chinese patent application discloses a kind of GaN base fin grid enhancement device and preparation method thereof, mainly solves existing same Class device threshold voltage is just floating small problem.However the grid structure of the device uses the contact of Xiao Te grid, therefore the forward direction of device Operating voltage is very low, it is difficult to meet significant power demand.
Chinese patent application discloses a kind of enhanced GaN transistor device of the notched gates based on nano-channel, the crystal Pipe has the advantages that grid-control ability is strong, inhibits short-channel effect, realizes that device enhancement mode and conducting resistance are small.However the device Grid structure uses the structure of groove combination MOS/MIS, therefore device the problems such as there are etching homogeneity, interface stabilities, It is difficult to realize industrial applications.
Although above-mentioned two scheme can realize GaN enhancement devices and improve threshold voltage, there is also obviously not Foot：Schottky or MOS/MIS grid structures are predominantly used, therefore the deficiencies of there are operating voltage is low and controllability, stability.
How to overcome deficiency of the prior art to have become in current technical field of semiconductor device preparation urgently to solve One of emphasis problem certainly.
Invention content
The purpose of the present invention is to overcome deficiency of the prior art to provide a kind of three-dimensional based on p-GaN structures Enhancement type high electron mobility transistor and its manufacturing method, the present invention can improve the threshold voltage of p-GaN enhancement devices With breakdown voltage.
2, according to a kind of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures proposed by the present invention, institute The structure for stating three-dimensional enhancement type high electron mobility transistor includes substrate, buffer layer, GaN base three-dimensional fin successively from bottom to top Piece, grid, source electrode and drain electrode, which is characterized in that further include built-in terminal structure, the built-in terminal structure is to be noted by ion Enter the built-in high resistant GaN area to be formed, the built-in high resistance areas GaN are located at the lower section and the two of GaN base three-dimensional fin of the grid The top of the adjacent buffer layer of side region；The top of the GaN bases three-dimensional fin and the growth of both sides secondary epitaxy have p-GaN/ AlGaN/GaN hetero-junctions；The grid is wrapped in the top and both sides of p-GaN/AlGaN/GaN hetero-junctions, forms three-dimensional grid knot Structure；The p-GaN layer of grid two side areas is removed by etching mode by form AlGaN/GaN hetero-junctions, the source electrode and drain electrode It is respectively provided at the both ends of AlGaN/GaN hetero-junctions.
A kind of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures proposed by the present invention it is further Preferred embodiment is：
The height of the GaN base three-dimensional fin is 200~1000nm, width is 200~2000nm, and the GaN bases are three-dimensional The quantity of fin be n >=1, the GaN base three-dimensional fin it is adjacent between spacing be 200~2000nm.The p-GaN/ The thickness of the p-GaN of AlGaN/GaN hetero-junctions is 40~150nm, p-type doping concentration is 1017~5 × 1020cm-3, p-type doping Material is any one of Mg, Fe, Zn, C and Ca；The thickness of AlGaN is 5~30nm, the group of Al is divided into 10~40%, GaN's Thickness is 20~200nm.
The first manufacture of a kind of three-dimensional GaN enhancement type high electron mobility transistors and preferred embodiment proposed by the present invention Method, which is characterized in that comprise the following specific steps that：
1) in the top grown buffer layer of the substrate；
2) in the disposed thereon metal or dielectric of the buffer layer as hard mask；
3) mask that GaN base three-dimensional fin is defined in the top of the hard mask, then passes through RIE and ICP modes Etching removal hard mask；
4) GaN is etched by RIE and ICP modes, forms three-dimensional GaN fins；The height of the GaN base three-dimensional fin is 200~1000nm, width be 200~2000nm, the GaN base three-dimensional fin it is adjacent between spacing be 200~2000nm；
5) use the modes such as TMAH or plasma treatment to remove etching injury, then inject ions into buffer layer formed it is built-in Terminal structure；The element of the ion implanting is any one of Ar, H, B, O, N, He, Zn and F, the energy of the ion implanting For 30~300KeV；
6) wet method or dry method mode is used to remove hard mask；
7) on the surface and side of buffer layer and GaN base three-dimensional fin, p- is grown using modes such as MOCVD, MBE and PLD GaN/AlGaN/GaN hetero-junctions；The thickness of the p-GaN of the p-GaN/AlGaN/GaN hetero-junctions is 40~150nm, p-type is adulterated A concentration of 1017~5 × 1020cm-3, p-type dopant material be any one of Mg, Fe, Zn, C and Ca；The thickness of AlGaN be 5~ The group of 30nm, Al are divided into 10~40%；The thickness of GaN is 20~200nm；
8) the p-GaN/AlGaN/GaN hetero-junctions surface above GaN base three-dimensional fin is heavy using evaporating or sputtering mode Product grid metal, then uses the modes such as ALD, PECVD, ICP-CVD and LPCVD to deposit block media layer；
9) photoetched grid mask is sequentially etched block media layer and grid metal using RIE and ICP modes, forms grid；
10) using the block media layer as mask, the p-type except removal area of grid is etched by RIE and ICP modes GaN forms AlGaN/GaN hetero-junctions；
11) wet etching is used to remove block media layer；
12) in the both sides of grid, photoetching source and drain mask then deposits source and drain metal, and high annealing forms source electrode and drain electrode；
13) photoetching isolation mask is defined, is isolated using etching or ion implanting mode, active area is formed；
14) grid, source electrode, drain electrode and AlGaN/GaN hetero-junctions surface, using ALD, PECVD and the side ICP-CVD Formula deposits passivation dielectric layer；
15) definition interconnection aperture area mask, etching form interconnection trepanning；
16) definition interconnection metal area mask forms interconnection metal by evaporation and stripping technology.
A kind of second based on three-dimensional GaN enhancement type high electron mobility transistors and preferred embodiment proposed by the present invention Manufacturing method, which is characterized in that comprise the following specific steps that:
1) in the top grown buffer layer of the substrate；
2) in the disposed thereon metal or dielectric of the buffer layer as hard mask；
3) mask that GaN base three-dimensional fin is defined in the top of the hard mask, then passes through RIE and ICP modes Etching removal hard mask；
4) GaN is etched by RIE and ICP modes, forms GaN base three-dimensional fin；The height of the GaN base three-dimensional fin is 200~1000nm, width are 200~2000nm；The GaN base three-dimensional fin it is adjacent between spacing be 200~2000nm；
5) it uses TMAH or plasma treatment mode to remove etching injury, then injects ions into buffer layer and form built-in end End structure；The element of the ion implanting is any one of Ar, H, B, O, N, He, Zn and F, and the energy of the ion implanting is 30~300KeV；
6) wet method or dry method mode is used to remove hard mask；
7) it on the surface and side of the buffer layer and GaN base three-dimensional fin, is grown using MOCVD, MBE and PLD mode P-GaN/AlGaN/GaN hetero-junctions；The thickness of the p-GaN of the p-GaN/AlGaN/GaN hetero-junctions is 40~150nm, p-type is mixed Miscellaneous a concentration of 1017~5 × 1020cm-3, p-type dopant material be any one of Mg, Fe, Zn, C and Ca；The thickness of AlGaN is 5 The group of~30nm, Al is divided into 10~40%；The thickness of GaN is 20~200nm；
8) it in p-GaN/AlGaN/GaN hetero-junctions both ends photoetching source and drain mask, is then carved by RIE and ICP modes Etching off removes p-type GaN, deposits source and drain metal, and high annealing forms source electrode and drain electrode；
9) the p-GaN/AlGaN/GaN hetero-junctions photomask surface gate masks above GaN base three-dimensional fin, using evaporation Or sputtering mode deposits grid metal, by stripping technology, forms grid；
10) using the source electrode, drain and gate as mask, by RIE and ICP modes etch removal source electrode, drain electrode and P-type GaN except area of grid forms AlGaN/GaN hetero-junctions；
11) photoetching isolation mask is defined, device isolation is carried out using etching or ion implanting mode, forms active area；
12) on grid, source electrode, drain electrode and AlGaN/GaN hetero-junctions surface, using ALD, PECVD and ICP-CVD mode Deposit passivation dielectric layer；
13) definition interconnection aperture area mask, etching form interconnection trepanning；
14) definition interconnection metal area mask forms interconnection metal by evaporation and stripping technology.
The realization principle of the present invention：The present invention forms GaN base three-dimensional fin by lithographic method first, and uses ability The pioneering built-in terminal structure in domain, which refers to the built-in high resistance area formed by ion implanting, described built-in The high resistance areas GaN are located at the top of the lower section buffer layer adjacent with the two side areas of GaN base three-dimensional fin of the grid, thus with Alleviate fin corner electric field；P-GaN/AlGaN/GaN layers then are grown using secondary epitaxy mode again, except by grid P-GaN etching removals after, the p-GaN/AlGaN/GaN that three-dimensional grid structure is formed below grid is heterogeneous, so as to utilize three The advantage for tieing up grid structure overcomes the defect of the existing plane enhancement device based on p-GaN structures, improves device threshold voltage And breakdown voltage.
Its remarkable advantage is the present invention compared with prior art：
First, three-dimensional grid structure is introduced into p-GaN enhancement devices by device of the invention, is increased using three-dimensional grid structure Strong gate control ability further improves the threshold voltage of conventional p-GaN structures enhancement device；
Second, three-dimensional grid structure is introduced into p-GaN enhancement devices by device of the invention, is had using three-dimensional grid structure There is better electric field ability of regulation and control and introduce built-in electric field terminal structure, is formed by fin both sides of the ion implanting below grid High resistance area alleviates fin corner peak electric field, therefore further improves hitting for conventional p-GaN structures enhancement device Wear voltage.
Third, device of the invention use p-GaN technologies, therefore compared with other MOS/MIS three-dimensionals enhancement devices, Controllability, stability higher, industrial applications potentiality bigger；The present invention is suitable for GaN high-tension electricity electronic fields.
Description of the drawings
Fig. 1 a are a kind of the flat of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures proposed by the present invention Face schematic diagram；Fig. 1 b are the sectional views of vertical direction a in Fig. 1 a；Fig. 1 c are the sectional views of horizontal direction b in Fig. 1 a.
Fig. 2 a, Fig. 2 b, Fig. 2 c, Fig. 2 d, Fig. 2 e, Fig. 2 f, Fig. 2 g, Fig. 2 h, Fig. 2 i are a kind of base proposed by the present invention successively In the schematic diagram of the flow of the first manufacturing method of the three-dimensional enhancement type high electron mobility transistor of p-GaN structures.
Fig. 3 a, Fig. 3 b, Fig. 3 c, Fig. 3 d, Fig. 3 e, Fig. 3 f, Fig. 3 g, Fig. 3 h are proposed by the present invention a kind of based on p- successively The schematic diagram of the flow of second of manufacturing method of the three-dimensional enhancement type high electron mobility transistor of GaN structures.
Specific implementation mode
The specific implementation mode of the present invention is further described in detail with reference to the accompanying drawings and examples.
A, Fig. 1 b and Fig. 1 c referring to Fig.1, a kind of enhanced high electronics of three-dimensional based on p-GaN structures proposed by the present invention move Shifting rate transistor is to be based on III nitride semiconductor, and structure includes substrate 1, buffer layer 2, GaN base three-dimensional fin from bottom to top Piece 3, grid 6, source electrode and drain electrode further include built-in terminal structure 4, and the built-in terminal structure 4 is to be formed by ion implanting Built-in high resistant GaN area, the built-in high resistance areas GaN are located at two lateral areas of the lower section and GaN base three-dimensional fin 3 of the grid 6 The top of the adjacent buffer layer 2 in domain；The top of the GaN base three-dimensional fin 3 and both sides growth have p-GaN/AlGaN/GaN heterogeneous Knot 5；The grid 6 is wrapped in the top and both sides of p-GaN/AlGaN/GaN hetero-junctions, forms three-dimensional grid structure；Pass through etching Mode removes the p-GaN layer of 6 two side areas of grid and forms AlGaN/GaN hetero-junctions, and the source electrode and drain electrode is respectively provided at The both ends of AlGaN/GaN hetero-junctions.Wherein：
The height of the GaN base three-dimensional fin 3 be 200~1000nm (including selection 200nm, 400nm, 600nm or 1000nm etc.), width be 200~2000nm (including selection 200nm, 600nm, 1000nm or 2000nm etc.)；The GaN base The quantity of three-dimensional fin 3 be n >=1, the GaN base three-dimensional fin 3 it is adjacent between spacing be 200~2000nm (including 200nm, 800nm, 1500nm or 2000nm etc.).
The p-GaN thickness of the p-GaN/AlGaN/GaN hetero-junctions 5 be 40~150nm (including selection 40nm, 70nm, 100nm or 150nm etc.), doping concentration 1017~5 × 1020cm-3, the thickness of AlGaN is 5~30nm, the group of Al is divided into 10 The thickness of~40%, GaN are 20~200nm (including selection 20nm, 50nm, 100nm or 200nm etc.).
With reference to Fig. 2 a, Fig. 2 b, Fig. 2 c, Fig. 2 d, Fig. 2 e, Fig. 2 f, Fig. 2 g, Fig. 2 h and Fig. 2 i, a kind of base proposed by the present invention In the first manufacturing method of the three-dimensional enhancement type high electron mobility transistor of p-GaN structures, comprise the following specific steps that：
1) in the top grown buffer layer 2 of the substrate 1, such as Fig. 2 a；Wherein, the material of the substrate 1 is Si, Buddha's warrior attendant Any one of stone, SiC, sapphire and GaN self-supported substrates；
2) in the disposed thereon metal or dielectric of the buffer layer 2 as hard mask；The hard mask be Ni, W, SiN and SiO2Any one or more of combines；
3) mask that GaN base three-dimensional fin is defined in the top of the hard mask, then passes through RIE and ICP modes Etching removal hard mask, such as Fig. 2 b；
4) GaN is etched by RIE and ICP modes, GaN base three-dimensional fin 3 is formed, such as Fig. 2 c；The GaN base three-dimensional fin The height of piece 3 is 200~1000nm, width is 200~2000nm；The GaN base three-dimensional fin 3 it is adjacent between spacing be 200~2000nm；
5) it uses the modes such as TMAH or plasma treatment to remove etching injury, then injects ions into buffer layer 2 formed Terminal structure 4 is set, such as Fig. 2 d；The element of the ion implanting is any one of Ar, H, B, O, N, He, Zn and F, it is described from The energy of son injection is 30~300KeV；
6) wet method or dry method mode is used to remove hard mask；
7) it on the surface and side of buffer layer 2 and GaN base three-dimensional fin 3, is grown using modes such as MOCVD, MBE and PLD P-GaN/AlGaN/GaN hetero-junctions 5, such as Fig. 2 e；The thickness of the p-GaN of the p-GaN/AlGaN/GaN hetero-junctions 5 be 40~ 150nm, p-type doping concentration are 1017~5 × 1020cm-3, p-type dopant material be any one of Mg, Fe, Zn, C and Ca； The thickness of AlGaN is 5~30nm, the group of Al is divided into 10~40%；The thickness of GaN is 20~200nm；
8) 5 surface of p-GaN/AlGaN/GaN hetero-junctions above GaN base three-dimensional fin 3 is using evaporation or sputtering mode Grid metal is deposited, block media layer is then deposited using ALD, PECVD, ICP-CVD and LPCVD mode, such as Fig. 2 f；The grid gold Category includes any multiple layer metal or single-layer metal of Pd/Au, W/Al, Ni/Au, Mo/Au, WN/Al, Pt, TiN and W, described The thickness of grid metal is 50~500nm；
9) photoetched grid mask is sequentially etched block media layer and grid metal using RIE and ICP modes, forms grid 6, Such as Fig. 2 g；
10) using block media layer as mask, the p-type except 6 region of removal grid is etched by RIE and ICP modes GaN forms AlGaN/GaN hetero-junctions, such as Fig. 2 h；
11) wet etching is used to remove block media layer；
12) in the both sides of grid 6, photoetching source and drain mask then deposits source and drain metal, and high annealing forms source electrode and leakage Pole, such as Fig. 2 i；
13) photoetching isolation mask is defined, is isolated using etching or ion implanting mode, active area is formed；
14) grid 6, source electrode, drain electrode and AlGaN/GaN hetero-junctions surface, using ALD, PECVD and ICP-CVD etc. Mode deposits passivation dielectric layer；
15) definition interconnection aperture area mask, etching form interconnection trepanning；
16) definition interconnection metal area mask forms interconnection metal by evaporation and stripping technology.
With reference to Fig. 3 a, Fig. 3 b, Fig. 3 c, Fig. 3 d, Fig. 3 e, Fig. 3 f, Fig. 3 g and Fig. 3 h, one kind proposed by the present invention is based on p- Second of manufacturing method of the three-dimensional enhancement type high electron mobility transistor of GaN structures, comprises the following specific steps that：
1) in the top grown buffer layer 2 of the substrate 1, such as Fig. 3 a；Wherein, the material of the substrate 1 is Si, Buddha's warrior attendant Any one of stone, SiC, sapphire and GaN self-supported substrates；
2) in the disposed thereon metal or dielectric of the buffer layer 2 as hard mask；The hard mask be Ni, W, SiN and SiO2Any one or more of combines；
3) mask that GaN base three-dimensional fin 3 is defined in the top of the hard mask, then passes through RIE and the side ICP Formula etching removal hard mask, such as Fig. 3 b；
4) GaN is etched by RIE and ICP modes, GaN base three-dimensional fin 3 is formed, such as Fig. 3 c；The GaN base three-dimensional fin The height of piece (3) is 200~1000nm, width is 200~2000nm；The GaN bases three-dimensional fin (3) it is adjacent between Spacing is 200~2000nm；
5) it uses the modes such as TMAH or plasma treatment to remove etching injury, then injects ions into buffer layer 2 formed Terminal structure 4 is set, such as Fig. 3 d；The element of the ion implanting is any one of Ar, H, B, O, N, He, Zn and F, it is described from The energy of son injection is 30~300KeV；
6) wet method or dry method mode is used to remove hard mask；
7) it on the surface and side of buffer layer 2 and GaN base three-dimensional fin 3, is grown using modes such as MOCVD, MBE and PLD P-GaN/AlGaN/GaN hetero-junctions 5, such as Fig. 3 e；The thickness of the p-GaN of the p-GaN/AlGaN/GaN hetero-junctions 5 be 40~ 150nm, p-type doping concentration are 1017~5 × 1020cm-3, p-type dopant material be any one of Mg, Fe, Zn, C and Ca； The thickness of AlGaN is 5~30nm, the group of Al is divided into 10~40%；The thickness of GaN is 20~200nm；
8) it in 5 both ends photoetching source and drain mask of p-GaN/AlGaN/GaN hetero-junctions, is then etched by RIE and ICP modes P-type GaN is removed, deposits source and drain metal, high annealing forms source electrode and drain electrode, such as Fig. 3 f；
9) the 5 photomask surface gate mask of p-GaN/AlGaN/GaN hetero-junctions above GaN base three-dimensional fin 3, using steaming Hair or sputtering mode deposit grid metal, by stripping technology, grid are formed, such as Fig. 3 g；The grid metal include Pd/Au, W/Al, Any multiple layer metal or single-layer metal of Ni/Au, Mo/Au, WN/Al, Pt, TiN and W, the thickness of the grid metal is 50~ 500nm；
10) using the source electrode, drain and gate as mask, by RIE and ICP modes etch removal source electrode, drain electrode and P-type GaN except area of grid forms AlGaN/GaN hetero-junctions, such as Fig. 3 h；
11) photoetching isolation mask is defined, device isolation is carried out using etching or ion implanting mode, forms active area；
12) on grid, source electrode, drain electrode and AlGaN/GaN hetero-junctions surface, using ALD, PECVD and ICP-CVD mode Deposit passivation dielectric layer；
13) definition interconnection aperture area mask, etching form interconnection trepanning；
14) definition interconnection metal area mask forms interconnection metal by evaporation and stripping technology.
According to a kind of above three-dimensional enhancement type high electron mobility transistor based on p-GaN structures of the present invention and Its two kinds of manufacturing methods, the present invention further disclose following specific examples, but are not limited to the specific embodiment.
Embodiment 1：The material for preparing substrate 1 is Si, the width of GaN base three-dimensional fin 3 is 200nm, be highly 1000nm, GaN base three-dimensional fin it is adjacent between spacing be 2000nm, grid metal W, using Ar ion implantings formed built-in terminal knot The three-dimensional GaN enhancement type high electron mobility transistors of structure, technical process comprise the concrete steps that：
1) first raw at 1050 DEG C using metal organic chemical vapor deposition technology MOCVD in the top of Si substrates 1 The AlN of long 200nm, then at 1000 DEG C grow 1 μm unintentional doping AlGaN layer (Al groups 15%) and 1 μm of GaN layer, Form buffer layer 2；
2) magnetron sputtering deposition 100nm W metals are used successively in the top of buffer layer 2,80nm is deposited using PECVD SiN is as hard mask；W sputtering conditions are：Du≤1.5 × 10 Zhen Kong-6Torr, deposition rate are less thanSiN depositing technics items Part is：Gas is respectively SiH4、NH3, He and N2, flow is respectively 8sccm, 2sccm, 100sccm and 200sccm, and pressure is 500mTorr, 260 DEG C of temperature, power 25W；
3) mask that GaN base three-dimensional fin 3 is defined in the top of W/SiN hard masks, is then carved by ICP modes Etching off removes hard mask；Etch technological condition is：Gas is SF6, flow 20sccm, pressure 0.2pa；
4) GaN is etched by ICP modes, forms GaN base three-dimensional fin 3；The width of GaN base three-dimensional fin 3 be 200nm, GaN base three-dimensional fin 3 it is adjacent between be divided into 2000nm；Etch technological condition is：Gas is respectively BCl3And Cl2, flow Respectively 25sccm and 5sccm, pressure 30mTorr, upper electrode power 100W, lower electrode 10W, etching depth 1000nm；
5) it uses TMAH to remove etching injury, Ar ion implantings buffer layer 2 is then formed into built-in terminal structure 4；Ar from The energy of son injection is 30KeV；
6) HF acid and H are successively used2O2Remove SiN and W metals；
7) on the surface and side of buffer layer 2 and GaN base three-dimensional fin 3, p-GaN/AlGaN/GaN is grown using MOCVD Hetero-junctions 5；The thickness of p-GaN is 150nm, doping concentration is 2 × 1017cm-3, p type dopant materials be Mg；The thickness of AlGaN For the group of 5nm, Al, to be divided into the thickness of 40%, GaN be 200nm；
8) 5 surface of p-GaN/AlGaN/GaN hetero-junctions above GaN base three-dimensional fin 3 is deposited using sputtering mode 50nm W grid metals then deposit 50nm block media layers SiN using PECVD modes；W sputtering conditions are：Du≤1.5 Zhen Kong × 10-6Torr, deposition rate are less thanSiN depositing technics conditions are：Gas is respectively SiH4、NH3, He and N2, flow difference For 8sccm, 2sccm, 100sccm and 200sccm, pressure 500mTorr, 260 DEG C of temperature, power 25W；
9) photoetched grid mask is sequentially etched SiN block medias layer and W grid metals using ICP, forms grid 6；SiN is carved Etching technique condition is：Gas is SF6, flow 20sccm, pressure 0.2pa；
10) using SiN block medias layer as mask, the p type GaN except 6 region of removal grid is etched by ICP, are formed AlGaN/GaN hetero-junctions；Etch technological condition is：Gas is respectively BCl3And Cl2, flow is respectively 25sccm and 5sccm, pressure Power is 30mTorr, 25 DEG C, upper electrode power 100W of temperature, lower electrode 10W；
11) successively BOE is used to remove SiN layer；
12) in 6 both sides of grid, photolithographic source drain mask, subsequent electron beam evaporation source and drain metal, high annealing formation source electrode And drain electrode；The metal deposited is from bottom to top Ti, Al and TiN, and thickness is respectively 20nm, 100nm and 200nm；Electron beam Evaporate the condition that uses for：Du≤2.0 × 10 Zhen Kong-6Torr, deposition rate are less thanThe process conditions of rapid thermal annealing For：550 DEG C of temperature, time 90s；
13) photoetching isolation mask is defined, is isolated using ion implanting mode, active area is formed；Injection condition is：From Son is B+, electric current 10 μ A, energy 200KeV, dosage 5e14；
14) on grid 6, source electrode, drain electrode and AlGaN/GaN hetero-junctions surface, using PECVD deposition 200nm SiN passivation Layer；SiN depositing technics conditions are：Gas is respectively SiH4、NH3, He and N2, flow is respectively 8sccm, 2sccm, 100sccm And 200sccm, pressure 500mTorr, 260 DEG C of temperature, power 25W；
15) definition interconnection aperture area mask, etching form interconnection trepanning；Etch technological condition is：Gas is SF6, flow For 20sccm, pressure 0.2pa；
16) definition interconnection metal area mask forms interconnection metal by evaporation and stripping technology；Du≤1.5 Zhen Kong × 10-6Torr, deposition rate are less thanDeposited it is metal laminated from bottom to top be Ti, Al, thickness be respectively 30nm, 500nm。
Embodiment 2：The material for preparing substrate 1 is GaN, the width of GaN base three-dimensional fin 3 is 600nm, be highly 600nm, GaN base three-dimensional fin it is adjacent between spacing be 1500nm, grid metal TiN/Al, built-in end is formed using B ion implantings The three-dimensional GaN enhancement type high electron mobility transistors of end structure 4, the specific steps of technical process include：
1) it is grown at 1000 DEG C using metal organic chemical vapor deposition technology MOCVD in the top of GaN substrate 1 The GaN layer of 2 μm of unintentional doping forms buffer layer 2；
2) 100nm Ni are deposited as hard mask using electron-beam evaporation mode in the top of buffer layer 2；Evaporation conditions are： Du≤1.5 × 10 Zhen Kong-6Torr, deposition rate are less than
3) mask of GaN base three-dimensional fin 3 is defined in the top of Ni hard masks, it is then hard by ICP etching removals Mask.Ni etch technological conditions are：Gas is Ar, flow 50sccm, pressure 0.4pa；
4) GaN is etched by ICP modes, forms GaN base three-dimensional fin 3；The width of GaN base three-dimensional fin 3 be 600nm, GaN base three-dimensional fin 3 it is adjacent between be divided into 1500nm；Etch technological condition is：Gas is respectively BCl3And Cl2, flow Respectively 25sccm and 5sccm, pressure 30mTorr, upper electrode power 100W, lower electrode 10W, etching depth 600nm；
5) it uses TMAH to remove etching injury, B ion implantings buffer layer 2 is then formed into built-in terminal structure；B ions Implantation Energy is 100KeV；
6) successively nitric acid is used to remove Ni metals；
7) different using MBE growths p-GaN/AlGaN/GaN on the surface and side of buffer layer 2 and GaN base three-dimensional fin 3 Matter knot 5；The thickness of p-GaN is 100nm, doping concentration is 5 × 1018cm-3, p type dopant materials be Fe；The thickness of AlGaN is The thickness that the group of 12nm, Al are divided into 28%, GaN is 100nm；
8) 5 surface of p-GaN/AlGaN/GaN hetero-junctions above GaN base three-dimensional fin 3 is heavy using sputtering mode successively The grid metal of product 100nm TiN and 250nm Al, then deposit 50nm block media layers SiN using PECVD modes；TiN is sputtered Condition is：Du≤1.5 × 10 Zhen Kong-6Torr, deposition rate are less thanSiN depositing technics conditions are：Gas is respectively SiH4、NH3, He and N2, flow is respectively 8sccm, 2sccm, 100sccm and 200sccm, pressure 500mTorr, temperature 260 DEG C, power 25W；
9) photoetched grid mask is sequentially etched SiN block medias layer and TiN/Al grid metals using ICP modes, forms grid Pole 6；The etch technological condition of SiN and TiN is：Gas is SF6, flow 20sccm, pressure 0.2pa.The etching technics item of Al Part is：Gas is Cl2, flow is respectively 35sccm, pressure 30mTorr, upper electrode power 200W, lower electrode 10W；
10) this step is identical as the step 10) of embodiment 1；
11) this step is identical as the step 11) of embodiment 1；
12) in the both sides of grid 6, photolithographic source drain mask, subsequent electron beam evaporation source and drain metal, high annealing formation source Pole and drain electrode；The metal deposited from bottom to top be respectively Ti, Al, Ni and Au, thickness be respectively 20nm, 150nm, 30nm and 50nm；The condition that electron beam evaporation uses for：Du≤2.0 × 10 Zhen Kong-6Torr, deposition rate are less thanRapid thermal annealing Process conditions be：850 DEG C of temperature, time 30s；
13) this step is identical as the step 13) of embodiment 1；
14) this step is identical as the step 14) of embodiment 1；
15) this step is identical as the step 15) of embodiment 1；
16) definition interconnection metal area mask forms interconnection metal by evaporation and stripping technology；Du≤1.5 Zhen Kong × 10-6Torr, deposition rate are less thanDeposited it is metal laminated from bottom to top be Ti, Au, thickness be respectively 30nm, 300nm。
Embodiment 3：The material for preparing substrate 1 is SiC, and the width of GaN base three-dimensional fin 3 is 1000nm, is highly 400nm, GaN base three-dimensional fin it is adjacent between spacing be 800nm, grid metal Pt, injected using F ion to be formed it is built-in The three-dimensional GaN enhancement type high electron mobility transistors of terminal structure, the specific steps of technical process include：
1) in the top of SiC substrate 1, using metal organic chemical vapor deposition technology MOCVD, first at 1050 DEG C Grow 250nm AlN, then at 1000 DEG C grow 3 μm unintentional doping GaN layer, formed buffer layer 2；
2) PECVD deposition 50nm SiN and 300nm SiO are used successively in the top of buffer layer 22As hard mask；SiN Depositing technics condition is：Gas is respectively SiH4、NH3, He and N2, flow be respectively 8sccm, 2sccm, 100sccm and 200sccm, pressure 500mTorr, 260 DEG C of temperature, power 25W；SiO2Depositing technics condition is：Gas is respectively SiH4、 N2O, He and N2, flow is respectively 10sccm, 3sccm, 100sccm and 200sccm, pressure 400mTorr, 260 DEG C of temperature, Power 25W；
3) in SiN/SiO2The top of hard mask defines the mask of GaN base three-dimensional fin 3, then passes through ICP modes Etching removal hard mask；Etch technological condition is：Gas is SF6, flow 50sccm, pressure 0.5pa；
4) GaN is etched by ICP modes, forms GaN base three-dimensional fin 3；The width of GaN base three-dimensional fin 3 be 1000nm, GaN base three-dimensional fin 3 it is adjacent between be divided into 800nm；Etch technological condition is：Gas is respectively BCl3And Cl2, flow Respectively 25sccm and 5sccm, pressure 30mTorr, upper electrode power 100W, lower electrode 10W, etching depth 400nm；
5) it uses TMAH to remove etching injury, F ion injecting layer 2 is then formed into built-in terminal structure 4；F ion The energy of injection is 200KeV；
6) successively HF acid is used to remove SiN and SiO2；
7) on the surface and side of buffer layer 2 and GaN base three-dimensional fin 3, p-GaN/AlGaN/GaN is grown using MOCVD Hetero-junctions 5；The thickness of p-GaN is 70nm, doping concentration is 4 × 1019cm-3, p type dopant materials be Ca；The thickness of AlGaN is The thickness that the group of 20nm, Al are divided into 20%, GaN is 50nm.
8) in 5 both ends photoetching source and drain mask of p-GaN/AlGaN/GaN hetero-junctions, removal p-type is then etched by ICP modes GaN, magnetron sputtering deposition source and drain metal, high annealing form source electrode and drain electrode；P-GaN etch technological conditions are：Gas is distinguished For BCl3And Cl2, flow is respectively 25sccm and 5sccm, pressure 30mTorr, upper electrode power 100W, lower electrode 10W；It splashes The source and drain metal penetrated is from bottom to top Ti, Al and W, and thickness is respectively 20nm, 100nm and 100nm；Sputter the condition used For：Du≤2.0 × 10 Zhen Kong-6Torr, deposition rate are less thanThe process conditions of rapid thermal annealing are：900 DEG C of temperature, when Between 30s；
9) the 5 photomask surface gate mask of p-GaN/AlGaN/GaN hetero-junctions above GaN base three-dimensional fin 3, using steaming Originating party formula deposits Pt metals, by stripping technology, forms grid 6；The Pt conditions that use of evaporation for：Du≤2.0 × 10 Zhen Kong- 6Torr, deposition rate are less thanThickness is 130nm；
10) using the source electrode, drain and gate 6 as mask, removal source electrode, drain and gate are etched by ICP modes P-type GaN except region forms AlGaN/GaN hetero-junctions；P-GaN etch technological conditions are：Gas is respectively BCl3And Cl2, Flow is respectively 25sccm and 5sccm, pressure 30mTorr, upper electrode power 100W, lower electrode 10W；
11) photoetching isolation mask is defined, is isolated using ion implanting mode, active area is formed；Injection condition is：From Son is Ar+, electric current 10 μ A, energy 300KeV, dosage 8e14；
12) this step is identical as the step 14) of embodiment 1；
13) this step is identical as the step 15) of embodiment 1；
14) this step is identical as the step 16) of embodiment 1.
Embodiment 4：The material for preparing substrate 1 is diamond, and the width of GaN base three-dimensional fin 3 is 2000nm, is highly 200nm, GaN base three-dimensional fin it is adjacent between spacing be 200nm, grid metal Ni/Au, formed using O ion implantings in The three-dimensional GaN enhancement type high electron mobility transistors of terminal structure are set, the specific steps of technical process include：
1) in the top of diamond substrate 1, using metal organic chemical vapor deposition technology MOCVD, first at 900 DEG C Grow 50nm AlN, then at 1000 DEG C grow 2.6 μm unintentional doping GaN layer, formed buffer layer 2；
2) in the top of buffer layer 2 successively using using magnetron sputtering deposition 50nm Ge and 300nm SiO2As covering firmly Mould；Sputtering condition is：Du≤1.5 × 10 Zhen Kong-6Torr, deposition rate are less than
3) in Ge/SiO2The top of hard mask defines the mask of GaN base three-dimensional fin 3, then passes through ICP modes Etching removal hard mask；Etch technological condition is：Gas is SF6, flow 50sccm, pressure 0.5pa；
4) GaN is etched by ICP modes, forms GaN base three-dimensional fin 3；The width of GaN base three-dimensional fin 3 be 2000nm, GaN base three-dimensional fin 3 it is adjacent between be divided into 200nm；Etch technological condition is：Gas is respectively BCl3And Cl2, flow Respectively 25sccm and 5sccm, pressure 30mTorr, upper electrode power 100W, lower electrode 10W, etching depth 200nm；
5) it uses wet method HCl to remove etching injury, O ion implantings buffer layer 2 is then formed into built-in terminal structure 4；O from The energy of son injection is 300KeV；
6) BOE and H is successively used2O2Remove SiO2With Ge metals；
7) different using MBE growths p-GaN/AlGaN/GaN on the surface and side of buffer layer 2 and GaN base three-dimensional fin 3 Matter knot 5；The thickness of p-GaN is 40nm, doping concentration is 5 × 1020cm-3, p type dopant materials be C；The thickness of AlGaN is The thickness that the group of 30nm, Al are divided into 15%, GaN is 50nm.
8) this step is identical as the step 8) of embodiment 3；
9) the 5 photomask surface gate mask of p-GaN/AlGaN/GaN hetero-junctions above GaN base three-dimensional fin 3, using steaming Originating party formula is sequentially depositing Ni and Au grid metals, by stripping technology, forms grid 6；The conditions that use of evaporation Ni and Au for：Very Du≤2.0 × 10 Kong-6Torr, deposition rate are less thanThickness is respectively 30nm and 470nm；
10) this step is identical as the step 10) of embodiment 3；
11) photoetching isolation mask is defined, device isolation is carried out using ion implanting mode, forms active area；Injection condition For：Ion is O+, electric current 15 μ A, energy 150KeV, dosage 2e15；
12) this step is identical as the step 14) of embodiment 1；
13) this step is identical as the step 15) of embodiment 1；
14) this step is identical as the step 16) of embodiment 2.
The explanation being not directed in the specific implementation mode of the present invention belongs to technology well known in the art, can refer to known technology It is implemented.
The above specific implementation mode and embodiment are enhanced to a kind of three-dimensional based on p-GaN structures proposed by the present invention The specific support of high electron mobility transistor and its manufacturing method technological thought cannot limit the protection model of the present invention with this It encloses, every any equivalent variations or equivalent according to technological thought proposed by the present invention, done on the basis of the technical program Change still falls within the range of technical solution of the present invention protection.

Claims (9)

1. a kind of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures, the enhanced high electronics of three-dimensional moves The structure of shifting rate transistor includes substrate (1), buffer layer (2), GaN base three-dimensional fin (3), grid (6), source successively from bottom to top Pole and drain electrode, which is characterized in that further include built-in terminal structure (4), the built-in terminal structure (4) is to pass through ion implanting shape At built-in high resistant GaN area, the built-in high resistance areas GaN are located at lower section and the GaN base three-dimensional fin (3) of the grid (6) The top of the adjacent buffer layer of two side areas (2)；The top of the GaN base three-dimensional fin (3) and the growth of both sides secondary epitaxy have P-GaN/AlGaN/GaN hetero-junctions (5)；The grid (6) is wrapped in the top and two of p-GaN/AlGaN/GaN hetero-junctions (5) Side forms three-dimensional grid structure；It is heterogeneous that AlGaN/GaN is formed by the p-GaN layer of etching mode removal grid (6) two side areas Knot, the source electrode and drain electrode are respectively provided at the both ends of AlGaN/GaN hetero-junctions.
2. a kind of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures according to claim 1, special Sign is that the height of the GaN base three-dimensional fin (3) is 200~1000nm, width is 200~2000nm；The GaN base three Tie up fin (3) quantity be n >=1, the GaN base three-dimensional fin (3) it is adjacent between spacing be 200~2000nm.
3. a kind of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures according to claim 2, special Sign is that the thickness of the p-GaN of the p-GaN/AlGaN/GaN hetero-junctions (5) is 40~150nm, p-type doping concentration is 1017 ~5 × 1020cm-3, p-type doped chemical be any one of Mg, Fe, Zn, C and Ca；The thickness of AlGaN is 5~30nm, Al Group is divided into 10~40%；The thickness of GaN is 20~200nm.
4. a kind of system of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures according to claim 1 Make method, which is characterized in that comprise the following specific steps that：
1) in the top grown buffer layer (2) of the substrate (1)；
2) in the disposed thereon metal or dielectric of the buffer layer (2) as hard mask；
3) mask that GaN base three-dimensional fin (3) is defined in the top of the hard mask, is then carved by RIE and ICP modes Etching off removes hard mask；
4) GaN is etched by RIE and ICP modes, forms GaN base three-dimensional fin (3)；The height of the GaN base three-dimensional fin (3) It is 200~2000nm for 200~1000nm, width；The GaN base three-dimensional fin (3) it is adjacent between spacing be 200~ 2000nm；
5) it uses TMAH or plasma treatment mode to remove etching injury, it is built-in eventually then to inject ions into buffer layer (2) formation End structure (4)；The element of the ion implanting is any one of Ar, H, B, O, N, He, Zn and F, the energy of the ion implanting Amount is 30~300KeV；
6) wet method or dry method mode is used to remove hard mask；
7) it on the surface and side of the buffer layer (2) and GaN base three-dimensional fin (3), is given birth to using MOCVD, MBE and PLD mode Long p-GaN/AlGaN/GaN hetero-junctions (5)；The thickness of the p-GaN of the p-GaN/AlGaN/GaN hetero-junctions (5) be 40~ 150nm, p-type doping concentration are 1017~5 × 1020cm-3, p-type dopant material be any one of Mg, Fe, Zn, C and Ca； The thickness of AlGaN is 5~30nm, the group of Al is divided into 10~40%；The thickness of GaN is 20~200nm；
8) p-GaN/AlGaN/GaN hetero-junctions (5) surface above GaN base three-dimensional fin (3) is using evaporation or sputtering mode Grid metal is deposited, block media layer is then deposited using ALD, PECVD, ICP-CVD and LPCVD mode；
9) photoetched grid mask is sequentially etched block media layer and grid metal using RIE and ICP modes, forms grid (6)；
10) using the block media layer as mask, the p-type except removal grid (6) region is etched by RIE and ICP modes GaN forms AlGaN/GaN hetero-junctions；
11) wet etching is used to remove block media layer；
12) in the both sides of grid (6), photoetching source and drain mask then deposits source and drain metal, and high annealing forms source electrode and drain electrode；
13) photoetching isolation mask is defined, is isolated using etching or ion implanting mode, active area is formed；
14) grid (6), source electrode, drain electrode and AlGaN/GaN hetero-junctions surface, using ALD, PECVD and ICP-CVD mode Deposit passivation dielectric layer；
15) definition interconnection aperture area mask, etching form interconnection trepanning；
16) definition interconnection metal area mask forms interconnection metal by evaporation and stripping technology.
5. according to a kind of three-dimensional enhancement type high electron mobility crystal based on p-GaN structures of claim 1 any one of them The manufacturing method of pipe, which is characterized in that comprise the following specific steps that：
1) in the top grown buffer layer (2) of the substrate (1)；
2) in the disposed thereon metal or dielectric of the buffer layer (2) as hard mask；
3) mask that GaN base three-dimensional fin (3) is defined in the top of the hard mask, is then carved by RIE and ICP modes Etching off removes hard mask；
4) GaN is etched by RIE and ICP modes, forms GaN base three-dimensional fin (3)；The height of the GaN base three-dimensional fin (3) It is 200~2000nm for 200~1000nm, width；The GaN base three-dimensional fin (3) it is adjacent between spacing be 200~ 2000nm；
5) it uses TMAH or plasma treatment mode to remove etching injury, it is built-in eventually then to inject ions into buffer layer (2) formation End structure (4)；The element of the ion implanting is any one of Ar, H, B, O, N, He, Zn and F, the energy of the ion implanting Amount is 30~300KeV；
6) wet method or dry method mode is used to remove hard mask；
7) it on the surface and side of the buffer layer (2) and GaN base three-dimensional fin (3), is given birth to using MOCVD, MBE and PLD mode Long p-GaN/AlGaN/GaN hetero-junctions (5)；The thickness of the p-GaN of the p-GaN/AlGaN/GaN hetero-junctions (5) be 40~ 150nm, p-type doping concentration are 1017~5 × 1020cm-3, p-type dopant material be any one of Mg, Fe, Zn, C and Ca； The thickness of AlGaN is 5~30nm, the group of Al is divided into 10~40%；The thickness of GaN is 20~200nm；
8) it in p-GaN/AlGaN/GaN hetero-junctions (5) the both ends photoetching source and drain mask, is then etched by RIE and ICP modes P-type GaN is removed, source and drain metal is deposited, high annealing forms source electrode and drain electrode；
9) p-GaN/AlGaN/GaN hetero-junctions (5) photomask surface gate mask above GaN base three-dimensional fin (3), using steaming Hair or sputtering mode deposit grid metal, by stripping technology, form grid (6)；
10) using the source electrode, drain and gate (6) as mask, removal source electrode, drain electrode and grid are etched by RIE and ICP modes P-type GaN except pole (6) region forms AlGaN/GaN hetero-junctions；
11) photoetching isolation mask is defined, device isolation is carried out using etching or ion implanting mode, forms active area；
12) heavy using ALD, PECVD and ICP-CVD mode on grid (6), source electrode, drain electrode and AlGaN/GaN hetero-junctions surface Product passivation dielectric layer；
13) definition interconnection aperture area mask, etching form interconnection trepanning；
14) definition interconnection metal area mask forms interconnection metal by evaporation and stripping technology.
6. a kind of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures according to claim 4 or 5 Manufacturing method, which is characterized in that the material of the step 1) substrate (1) is Si, diamond, SiC, sapphire and GaN self-supportings Any one of substrate.
7. a kind of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures according to claim 4 or 5 Manufacturing method, which is characterized in that the material of the step 2) hard mask is Ni, W, Ge, SiN and SiO2Any one or more of Combination.
8. a kind of system of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures according to claim 4 Make method, which is characterized in that the step 8) grid metal includes Pd/Au, W/Al, Ni/Au, Mo/Au, WN/Al, Pt, TiN and W Any one of multiple layer metal or single-layer metal, the thickness of the grid metal be 50~500nm.
9. a kind of system of three-dimensional enhancement type high electron mobility transistor based on p-GaN structures according to claim 5 Make method, which is characterized in that the step 9) grid metal includes Pd/Au, W/Al, Ni/Au, Mo/Au, WN/Al, Pt, TiN and W Any one of multiple layer metal or single-layer metal, the thickness of the grid metal be 50~500nm.
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