CN105118860A - HEMT with integrated ordered GaN-base nanowire array and preparation method thereof - Google Patents
HEMT with integrated ordered GaN-base nanowire array and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention discloses a HEMT with an integrated ordered GaN-base nanowire array and a preparation method thereof. A groove pattern substrate is prepared through a photolithography technique in order that the length, the width, and the depth of a groove pattern are controllable. Thus, the controllability of an epitaxial grown micro-nanometer material on the groove pattern substrate is effectively improved. A HEMT is directly prepared on the epitaxial grown micro-nanometer material on the groove pattern substrate. Compared with an integrated device preparation method for acquiring the micro-nanometer material by stripping the substrate or transferring the substrate with a single one-dimensional material, the method effectively simplifies processing steps and is more beneficial to practical application. The HEMT and the preparation method thereof are can be widely used in the field of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to a kind of integrated orderly GaN base nano-wire array HEMT and preparation method thereof.
Background technology
Semiconductor nanowires becomes the focus studied at present due to the speciality such as Large ratio surface sum high aspect ratio of the peculiar property and one-dimensional nano structure that possess semiconductor simultaneously.Because nanostructure has more satisfactory physics and chemistry character, great potential in the basic module or interconnection element of semiconductor device, thus has huge application prospect in future microelectronics integrated technology.
The preparation of semiconductor microactuator nano parts mainly contains two kinds of methods: one is the technology being called as " Top-Down ", namely utilizes technological means by semi-conducting material as Si, Ge, GaN etc. diminish, is then prepared into device; Another is the technology being called as " Bottom-Up ", mainly the molecule of inorganic or organic semiconducting materials, atom is assembled into nano functional device, makes size " greatly ".The former is limited to photoetching process and resolution; And with molecular self-assembling etc. for the growing method of " Bottom-Up " of representative can prepare the higher micro-nano material of crystal mass, become the study hotspot in each field, but the growth of nanometer one-dimensional material depends on the random introducing of metallic catalyst mostly, this randomness causing micro-nano material to grow and uncontrollability, make micro-nano device can not play the potential of micro-nano material completely.
Semiconductor material with wide forbidden band GaN has the speciality such as saturated electrons migration velocity is fast, breakdown electric field is high, physico-chemical property is stable, capability of resistance to radiation is strong, is the ideal material making high temperature, high frequency, high-power pulsed ion beams.Because AlGaN/GaN heterojunction boundary two-dimensional electron gas (2DEG) has the characteristics such as electron concentration is large, power density is high, making the advantage having uniqueness in HEMT device.But the current preparation of the HEMT device based on AlGaN/GaN nanowire heterojunction is also immature, by heterojunction nano-wire epitaxial growth and device preparative separation in most preparation method, this not only increases process complexity, and controllability is low, limits its actual application and development.
Summary of the invention
In order to solve the problems of the technologies described above, the object of this invention is to provide a kind of energy Simplified flowsheet, and improving integrated orderly GaN base nano-wire array HEMT of one of controllability and preparation method thereof.
The technical solution adopted in the present invention is:
A kind of integrated orderly GaN base nano-wire array HEMT, comprise substrate, be etched in the groove of the multiple equidistant arrangement of substrate face and in the drain electrode of strip with source electrode, on the sidewall of each described groove, growth has nano wire to form nano-wire array, described substrate is provided with mask layer, described drain electrode and source electrode are located at the two ends of nano-wire array respectively and are connected with each nano wire is vertical, described substrate back preparation has gate dielectric layer, is formed with grid below described gate dielectric layer.
As the further improvement of described a kind of integrated orderly GaN base nano-wire array HEMT, between the nano wire in each described groove, be filled with insulating dielectric materials, form insulating medium layer.
As the further improvement of described a kind of integrated orderly GaN base nano-wire array HEMT, between described recess sidewall and nano wire, be provided with resilient coating.
As the further improvement of described a kind of integrated orderly GaN base nano-wire array HEMT, described nano wire be included in resilient coating Epitaxial growth stratum nucleare, grow thin layer on stratum nucleare and the shell of growth on thin layer.
Another technical scheme of the present invention is:
A kind of integrated orderly GaN base nano-wire array HEMT preparation method, comprises the following steps:
The groove of A, the multiple equidistant arrangement of etching formation on substrate;
B, at each recess sidewall Epitaxial growth nano wire, formed nano-wire array;
C, in each groove both sides nano wire between fill insulating dielectric materials and form insulating medium layer, and etching is carried out to insulating medium layer each nano wire upper end is exposed;
D, to prepare respectively at the two ends of nano-wire array and formed and the drain electrode connected vertically of each nano wire and source electrode;
E, substrate back preparation formed gate dielectric layer, and below gate dielectric layer preparation formed grid.
As the further improvement of described a kind of integrated orderly GaN base nano-wire array HEMT preparation method, described steps A comprises:
A1, substrate face prepare dielectric material formed mask layer;
A2, employing acetone and isopropyl alcohol clean mask layer surface and dry, and then at surperficial spin coating photoresist layer;
A3, by equidistant striped photoetching board to explosure carry out development treatment subsequently, and then carry out except glue process;
The etching depth that A4, basis are preset, carries out wet etching to the part after glue, forms the groove of multiple equidistant arrangement.
As the further improvement of described a kind of integrated orderly GaN base nano-wire array HEMT preparation method, described step B comprises:
B1, by Metalorganic Chemical Vapor Deposition at each recess sidewall Epitaxial growth resilient coating;
B2, on the buffer layer epitaxial growth stratum nucleare, and at stratum nucleare Epitaxial growth thin layer, then at thin layer Epitaxial growth shell, form nano wire, obtain nano-wire array.
As the further improvement of described a kind of integrated orderly GaN base nano-wire array HEMT preparation method, described step C comprises:
C1, employing acetone, isopropyl alcohol and deionized water clean nano-wire array, then adopt nitrogen to dry up and carry out baking to it to remove surface water molecule, and then carry out oxygen plasma treatment;
C2, insulating dielectric materials is filled to both sides in each groove by spin coating nano wire between, then it toasted and cool, and then carrying out oxygen plasma treatment;
C3, etching is carried out to insulating medium layer each nano wire upper end is exposed.
As the further improvement of described a kind of integrated orderly GaN base nano-wire array HEMT preparation method, described step D is specially:
Utilize the method for evaporation or sputtering to prepare respectively at the two ends of nano-wire array to be formed and the drain electrode connected vertically of each nano wire and source electrode.
The invention has the beneficial effects as follows:
A kind of integrated orderly GaN base nano-wire array HEMT of the present invention and preparation method thereof prepares groove pattern substrate by photoetching process, makes groove pattern length, width, the degree of depth controlled, thus effectively improves the micro-nano material controllability of graph substrate Epitaxial growth.And the present invention directly prepares HEMT device on the micro-nano material of graph substrate Epitaxial growth, method with respect to the translate substrate obtaining micro-nano material or single one-dimensional material at the bottom of peeling liner prepares integrated device, the present invention effectively simplifies processing step, is more conducive to practical application.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further:
Fig. 1 is the structural representation of a kind of integrated orderly GaN base nano-wire array HEMT of the present invention;
Fig. 2 is Si(100 in a kind of integrated orderly GaN base nano-wire array HEMT of the present invention) the nano thread structure schematic diagram of substrate;
Fig. 3 is Si(110 in a kind of integrated orderly GaN base nano-wire array HEMT of the present invention) the nano thread structure schematic diagram of substrate;
Fig. 4 is the flow chart of steps of a kind of integrated orderly GaN base nano-wire array HEMT preparation method of the present invention;
Fig. 5 is the flow chart of steps of a kind of integrated orderly GaN base nano-wire array HEMT preparation method steps A of the present invention;
Fig. 6 is the flow chart of steps of a kind of integrated orderly GaN base nano-wire array HEMT preparation method step B of the present invention;
Fig. 7 is the flow chart of steps of a kind of integrated orderly GaN base nano-wire array HEMT preparation method step C of the present invention.
Embodiment
With reference to figure 1-Fig. 7, a kind of integrated orderly GaN base nano-wire array HEMT of the present invention, comprise substrate 1, be etched in the groove of the multiple equidistant arrangement in substrate 1 front and in the drain electrode 5 of strip with source electrode 4, on the sidewall of each described groove, growth has nano wire 3 to form nano-wire array, described substrate 1 is provided with mask layer 11, described drain electrode 5 and source electrode 4 are located at the two ends of nano-wire array respectively and are connected with each nano wire 3 is vertical, the preparation of described substrate 1 back side has gate dielectric layer 6, is formed with grid 7 below described gate dielectric layer 6.
Be further used as preferred embodiment, be filled with insulating dielectric materials between the nano wire 3 in each described groove, form insulating medium layer 2, described insulating medium layer 2 adopts oxygen plasma etch part to expose nano-wire array upper end.
Be further used as preferred embodiment, between described recess sidewall and nano wire 3, be provided with resilient coating 12.
Be further used as preferred embodiment, described nano wire 3 be included in resilient coating 12 Epitaxial growth stratum nucleare 31, grow thin layer 32 on stratum nucleare 31 and the shell 33 of growth on thin layer 32.
In a kind of integrated orderly GaN base nano-wire array HEMT preparation method specific embodiment of the present invention, comprise the following steps:
S1, prepare on Si substrate 1 dielectric material formed mask layer 11, the thickness of mask layer 11 is 100-200nm; Dry in thermal station after cleaning up surface through acetone, isopropyl alcohol, then spin coating photoresist layer on sol evenning machine; Then special equidistant striped photoetching board to explosure is adopted; Develop subsequently, and carry out, except glue process, if photoresist layer is positive glue, then removing the photoresist layer be exposed; If photoresist layer is negative glue, then remove unexposed photoresist layer; Then configure etching liquid removal photoresist layer is spilt to substrate 1 part and carries out wet etching, etching depth controls according to etch period, forms equidistant groove array;
S2, the Si substrate 1 with equidistant groove array figure prepared in step S1 is loaded into metal organic chemical vapor deposition system response room, then epitaxial growth buffer 12AlN is to reduce the stress of epitaxial gan layers, then at resilient coating 12 Epitaxial growth high-quality GaN stratum nucleare 31, then growing AIN thin layer 32, then grow AlGaN shell 33, finally form the nano-wire array of GaN/AlN/AlGaN nucleocapsid in groove two side;
S3, nano wire 3 heterojunction array by preparing in acetone, isopropyl alcohol, washed with de-ionized water step S2, nitrogen dries up and is placed in thermal station toasts removes surface water molecule in 2 ~ 10 minutes, then adopts oxygen plasma treatment 5 ~ 10 minutes; Adopt sol evenning machine insulating dielectric materials PMMA will be adopted to be spun on substrate to fill nano wire 3 heterojunction array gap as institute in the present invention, sol evenning machine rotating speed is 2000 ~ 4000rpm, and repetition spin coating twice is fully to cover nano-wire array; Thermal station is toasted and is utilized 120W oxygen plasma treatment 10 ~ 20 minutes after cooling subsequently, and etching one deck PMMA is to expose heterojunction nano-wire array upper end;
S4, utilize evaporation or sputtering method to prepare strip electrode in heterojunction nano-wire array upper end, form source electrode 4 and the drain electrode 5 of HEMT device;
S5, prepare gate dielectric layer 6 at Si substrate 1 back side, thickness is 100-200nm; Then on gate dielectric layer 6, make electrode, form grid 7.
The preparation method of described a kind of integrated orderly GaN base nano-wire array HEMT, by substrate 1 and the mask layer 11 that is positioned on substrate 1 in conjunction with photoetching technique, the striped groove of ordered arrangement can prepare the controlled figure micro-nano structure substrate 1 of length, the degree of depth, width.
The preparation method of described a kind of integrated orderly GaN base nano-wire array HEMT, on described micro-nano array pattern substrate 1 and substrate 1, the nano-wire array material such as GaN, AlGaN of extension is the preparation method forming nano wire 3 heterojunction array.
The preparation method of described a kind of integrated orderly GaN base nano-wire array HEMT, epitaxial nanowires 3 material adopts metal organic chemical vapor deposition technology, by regulating organic source, growth temperature, air pressure, time, III-V race's heterojunction micro-nano array structure such as GaN, AlGaN/GaN, InGaN/GaN, AlInGaN/GaN can be prepared.
The preparation method of described a kind of integrated orderly GaN base nano-wire array HEMT, utilize filling insulating material GaN nano gap, packing material can be the insulating dielectric materials such as oxide, nitride, organic high molecular compound, and fill method can adopt the methods such as spin coating, evaporation, sputtering.
Under specific embodiments of the invention:
Embodiment 1, in conjunction with reference to figure 1 ~ Fig. 3, (100) p-Si substrate 1 of 2 inches prepares silicon dioxide as mask layer 11, the thickness of mask layer 11 is 150nm; Toast 5 minutes in thermal station after cleaning up surface through acetone, isopropyl alcohol, the then positive photoresist layer of spin coating on sol evenning machine; Then adopt special equidistant striped photoetching board to explosure, photolithography plate fringe spacing is 3um; Develop subsequently, remove the photoresist layer be exposed; Then configure etching liquid to removal photoresist layer spill substrate 1Si part carry out wet etching, etching depth is 1.2um, forms equidistant inverted trapezoidal groove array, and groove two sides are Si(111) face, flute pitch is 2um.
The Si substrate 1 with equidistant groove array figure prepared being loaded into metal organic chemical vapor deposition system response room, then epitaxial growth AlN(20nm) resilient coating 12 to be to reduce the stress of epitaxial gan layers; Then at recess sidewall growing GaN/AlN/AlGaN nano wire 3 heterojunction array, GaN(1.5um is comprised) stratum nucleare 31, AlN(1nm) thin layer 32, AlGaN(50nm) shell 33.
The substrate grown by epitaxial structure cuts into 1*1cm small pieces, and by acetone, isopropyl alcohol, washed with de-ionized water, nitrogen dries up and is placed in thermal station and toasts 5 minutes removal surface water molecules, then adopts oxygen plasma treatment 5 minutes; Adopt sol evenning machine PMMA to be spun on substrate to fill nano wire 3 heterojunction array gap, sol evenning machine rotating speed is 3000rpm, and repetition spin coating twice is fully to cover nano-wire array; Thermal station is toasted and is utilized 120W oxygen plasma treatment 15 minutes after cooling subsequently, and etching one deck PMMA is to expose heterojunction nano-wire array upper end.
Bar shaped Ti/Al/Ti/Au(20nm/50nm/20nm/50nm is prepared in heterojunction nano-wire array upper end) electrode, and vertical with nano-wire array direction, form source electrode 4 and the drain electrode 5 of HEMT device.
At Si substrate 1 back side electron beam transpiration SiO2 as gate dielectric layer 6, thickness is 150nm; Then on gate medium evaporating Al as grid 7.
Embodiment 2, in conjunction with reference to figure 1 ~ Fig. 3, (100) p-Si substrate 1 of 2 inches prepares silicon dioxide as mask layer 11, the thickness of mask layer 11 is 150nm; Toast 5 minutes in thermal station after cleaning up surface through acetone, isopropyl alcohol, the then positive photoresist layer of spin coating on sol evenning machine; Then adopt special equidistant striped photoetching board to explosure, photolithography plate fringe spacing is 5um; Develop subsequently, remove the photoresist layer be exposed; Then configure etching liquid to removal photoresist layer spill substrate 1Si part carry out wet etching, etching depth is 1.2um, forms equidistant inverted trapezoidal groove array, and groove two sides are Si(111) face, flute pitch is 4um.
The Si substrate 1 with equidistant groove array figure prepared being loaded into metal organic chemical vapor deposition system response room, then epitaxial growth AlN(20nm) resilient coating 12 to be to reduce the stress of epitaxial gan layers; Then at recess sidewall growing GaN/AlN/AlGaN nano wire 3 heterojunction array, GaN(1.5um is comprised) stratum nucleare 31, AlN(1nm) thin layer 32, AlGaN(50nm) shell 33.
The substrate grown by epitaxial structure cuts into 1*1cm small pieces, and by acetone, isopropyl alcohol, washed with de-ionized water, nitrogen dries up and is placed in thermal station and toasts 5 minutes removal surface water molecules, then adopts oxygen plasma treatment 5 minutes; Adopt sol evenning machine PMMA to be spun on substrate to fill nano wire 3 heterojunction array gap, sol evenning machine rotating speed is 3000rpm, and repetition spin coating twice is fully to cover nano-wire array; Thermal station is toasted and is utilized 120W oxygen plasma treatment 15 minutes after cooling subsequently, and etching one deck PMMA is to expose heterojunction nano-wire array upper end.
Bar shaped Ti/Al/Ti/Au(20nm/50nm/20nm/50nm is prepared in heterojunction nano-wire array upper end) electrode, and vertical with nano-wire array direction, form HEMT device source electrode 4 and drain electrode 5.
At Si substrate 1 back side electron beam transpiration SiO2 as gate dielectric layer 6, thickness is 150nm; Then on gate dielectric layer 6 evaporating Al as grid 7.
Embodiment 3, in conjunction with reference to figure 1 ~ Fig. 3, (100) p-Si substrate 1 of 2 inches prepares silicon dioxide as mask layer 11, the thickness of mask layer 11 is 150nm; Toast 5 minutes in thermal station after cleaning up surface through acetone, isopropyl alcohol, the then positive photoresist layer of spin coating on sol evenning machine; Then adopt special equidistant striped photoetching board to explosure, photolithography plate fringe spacing is 5um; Develop subsequently, remove the photoresist layer be exposed; Then configure etching liquid to removal photoresist layer spill substrate 1Si part carry out wet etching, etching depth is 1.2um, forms equidistant inverted trapezoidal groove array, and groove two sides are Si(111) face, flute pitch is 4um.
The Si substrate 1 with equidistant groove array figure prepared being loaded into metal organic chemical vapor deposition system (MOCVD) reative cell, then epitaxial growth AlN(20nm) resilient coating 12 to be to reduce the stress of epitaxial gan layers; Then at recess sidewall growing GaN/AlN/AlGaN nano wire 3 heterojunction array, comprise GaN(1.5um) stratum nucleare 31, AlN(1nm) thin layer 32, AlGaN(50nm) shell 33, wherein shell 33 comprises involuntary doped with Al GaN (20nm) and mixes N-shaped AlGaN(30nm).
The substrate grown by epitaxial structure cuts into 1*1cm small pieces, and by acetone, isopropyl alcohol, washed with de-ionized water, nitrogen dries up and is placed in thermal station and toasts 5 minutes removal surface water molecules, then adopts oxygen plasma treatment 5 minutes; Adopt sol evenning machine PMMA to be spun on substrate to fill nano wire 3 heterojunction array gap, sol evenning machine rotating speed is 3000rpm, and repetition spin coating twice is fully to cover nano-wire array; Thermal station is toasted and is utilized 120W oxygen plasma treatment 15 minutes after cooling subsequently, and etching one deck PMMA is to expose heterojunction nano-wire array upper end.
Bar shaped Ti/Al/Ti/Au(20nm/50nm/20nm/50nm is prepared in heterojunction nano-wire array upper end) electrode, and vertical with nano-wire array direction, form HEMT device source electrode 4 and drain electrode 5.
At Si substrate 1 back side electron beam transpiration SiO2 as gate dielectric layer 6, thickness is 150nm; Then on gate dielectric layer 6 evaporating Al as grid 7.
Embodiment 4, in conjunction with reference to figure 1 ~ Fig. 3, (110) p-Si substrate 1 of 2 inches prepares silicon dioxide as mask layer 11, the thickness of mask layer 11 is 150nm; Toast 5 minutes in thermal station after cleaning up surface through acetone, isopropyl alcohol, the then positive photoresist layer of spin coating on sol evenning machine; Then adopt special equidistant striped photoetching board to explosure, photolithography plate fringe spacing is 5um; Develop subsequently, remove the photoresist layer be exposed; Then configure etching liquid to removal photoresist layer spill substrate 1Si part carry out wet etching, etching depth is 1.2um, forms equidistant rectangular recess array, and groove two sides are Si(111) face, flute pitch is 4um.
The Si substrate 1 with equidistant groove array figure prepared being loaded into metal organic chemical vapor deposition system (MOCVD) reative cell, then epitaxial growth AlN(20nm) resilient coating 12 to be to reduce the stress of epitaxial gan layers; Then at recess sidewall growing GaN/AlN/AlGaN nano wire 3 heterojunction array, comprise GaN(1.2um) stratum nucleare 31, AlN(1nm) thin layer 32, AlGaN(50nm) shell 33, wherein shell 33 comprises involuntary doped with Al GaN (20nm) and mixes N-shaped AlGaN(30nm).
The substrate grown by epitaxial structure cuts into 1*1cm small pieces, and by acetone, isopropyl alcohol, washed with de-ionized water, nitrogen dries up and is placed in thermal station and toasts 5 minutes removal surface water molecules, then adopts oxygen plasma treatment 5 minutes; Adopt sol evenning machine PMMA to be spun on substrate to fill nano wire 3 heterojunction array gap, sol evenning machine rotating speed is 3000rpm, and repetition spin coating twice is fully to cover nano-wire array; Thermal station is toasted and is utilized 120W oxygen plasma treatment 15 minutes after cooling subsequently, and etching one deck PMMA is to expose heterojunction nano-wire array upper end.
Bar shaped Ti/Al/Ti/Au(20nm/50nm/20nm/50nm is prepared in heterojunction nano-wire array upper end) electrode, and vertical with nano-wire array direction, form HEMT device source electrode 4 and drain electrode 5.
At Si substrate 1 back side electron beam transpiration SiO2 as gate dielectric layer 6, thickness is 150nm; Then on gate dielectric layer 6 evaporating Al as grid 7.
More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and these equivalent distortion or replacement are all included in the application's claim limited range.
Claims (9)
1. an integrated orderly GaN base nano-wire array HEMT, it is characterized in that: comprise substrate, be etched in the groove of the multiple equidistant arrangement of substrate face and in the drain electrode of strip with source electrode, on the sidewall of each described groove, growth has nano wire to form nano-wire array, described substrate is provided with mask layer, described drain electrode and source electrode are located at the two ends of nano-wire array respectively and are connected with each nano wire is vertical, described substrate back preparation has gate dielectric layer, is formed with grid below described gate dielectric layer.
2. the integrated orderly GaN base nano-wire array HEMT of one according to claim 1, is characterized in that: be filled with insulating dielectric materials between the nano wire in each described groove, forms insulating medium layer.
3. the integrated orderly GaN base nano-wire array HEMT of one according to claim 1, is characterized in that: be provided with resilient coating between described recess sidewall and nano wire.
4. the integrated orderly GaN base nano-wire array HEMT of one according to claim 3, is characterized in that: described nano wire be included in resilient coating Epitaxial growth stratum nucleare, grow thin layer on stratum nucleare and the shell of growth on thin layer.
5. an integrated orderly GaN base nano-wire array HEMT preparation method, is characterized in that, comprise the following steps:
The groove of A, the multiple equidistant arrangement of etching formation on substrate;
B, at each recess sidewall Epitaxial growth nano wire, formed nano-wire array;
C, in each groove both sides nano wire between fill insulating dielectric materials and form insulating medium layer, and etching is carried out to insulating medium layer each nano wire upper end is exposed;
D, to prepare respectively at the two ends of nano-wire array and formed and the drain electrode connected vertically of each nano wire and source electrode;
E, substrate back preparation formed gate dielectric layer, and below gate dielectric layer preparation formed grid.
6. the integrated orderly GaN base nano-wire array HEMT preparation method of one according to claim 5, is characterized in that: described steps A comprises:
A1, substrate face prepare dielectric material formed mask layer;
A2, employing acetone and isopropyl alcohol clean mask layer surface and dry, and then at surperficial spin coating photoresist layer;
A3, by equidistant striped photoetching board to explosure carry out development treatment subsequently, and then carry out except glue process;
The etching depth that A4, basis are preset, carries out wet etching to the part after glue, forms the groove of multiple equidistant arrangement.
7. the integrated orderly GaN base nano-wire array HEMT preparation method of one according to claim 5, is characterized in that: described step B comprises:
B1, by Metalorganic Chemical Vapor Deposition at each recess sidewall Epitaxial growth resilient coating;
B2, on the buffer layer epitaxial growth stratum nucleare, and at stratum nucleare Epitaxial growth thin layer, then at thin layer Epitaxial growth shell, form nano wire, obtain nano-wire array.
8. the integrated orderly GaN base nano-wire array HEMT preparation method of one according to claim 5, is characterized in that: described step C comprises:
C1, employing acetone, isopropyl alcohol and deionized water clean nano-wire array, then adopt nitrogen to dry up and carry out baking to it to remove surface water molecule, and then carry out oxygen plasma treatment;
C2, insulating dielectric materials is filled to both sides in each groove by spin coating nano wire between, then it toasted and cool, and then carrying out oxygen plasma treatment;
C3, etching is carried out to insulating medium layer each nano wire upper end is exposed.
9. the integrated orderly GaN base nano-wire array HEMT preparation method of one according to claim 5, is characterized in that: described step D is specially:
Utilize the method for evaporation or sputtering to prepare respectively at the two ends of nano-wire array to be formed and the drain electrode connected vertically of each nano wire and source electrode.
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