KR101678874B1

KR101678874B1 - Manufacturing method for semiconductor device

Info

Publication number: KR101678874B1
Application number: KR1020150041417A
Authority: KR
Inventors: 이정희; 이준혁; 원철호; 조영우; 손동혁
Original assignee: 경북대학교 산학협력단
Priority date: 2015-03-25
Filing date: 2015-03-25
Publication date: 2016-11-23
Also published as: KR20160114923A

Abstract

A method of manufacturing a semiconductor device is disclosed. The present manufacturing method includes the steps of forming a semiconductor layer on a buffer layer, etching a semiconductor layer and a portion of a buffer layer to have a predetermined structure, forming an oxide film having a predetermined height lower than a height of a predetermined structure on the etched buffer layer Forming a gate insulating film on the oxide film and the predetermined structure, and forming a gate electrode on the gate insulating film.

Description

Technical Field [0001] The present invention relates to a method of manufacturing a semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device manufacturing method, and more particularly, to a method of manufacturing a semiconductor device capable of minimizing current leakage.

As the degree of integration of semiconductor devices increases, the design rule for the elements of the semiconductor device becomes more severe. In particular, for semiconductor devices requiring a large number of transistors, the gate length, which is the standard of the design rule, is reduced, and the channel length is also reduced. The reduction in the channel length of the transistor results in a so-called short channel effect .

The short channel effect means that the effective channel length of the transistor is reduced due to the effect of the drain potential and the threshold voltage is reduced. Due to the short channel effect, it is difficult to control the transistor, and the off current of the transistor tends to increase. As a result, the reliability of the transistor is lowered, for example, the refresh characteristic of the memory element can be adversely affected. Further, there is a problem that leakage current increases as the gate width becomes narrower.

In recent years, a pin-channel structure transistor, a so-called Fin-FET, has emerged in order to suppress the short channel effect which is a problem in the conventional planar transistor and to reduce the leakage current. Pinpets are a technology for designing and producing system semiconductors with a three-dimensional (3D) three-dimensional structure. The shape of the gate electrode protruding from the three-dimensional structure is similar to that of a shark fin (Fin). The application of the pin-pin technology enables operation at half the level voltage of the previous two-dimensional gate, and the leakage current is much smaller. Particularly, a device using a group III nitride semiconductor has various advantages such as a high breakdown field (~ 3 x 10 6 V / cm), maximum current density, stable high temperature operation, high thermal conductivity, It was spotlighted. Efforts have been continued to minimize the leakage current even in such pin-pets devices.

The present invention has been made in view of the above-mentioned efforts, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of minimizing current leakage.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming a semiconductor layer on a buffer layer; etching a portion of the semiconductor layer and the buffer layer to have a predetermined structure; Forming an oxide film having a predetermined height lower than a height of the predetermined structure on the etched buffer layer, forming a gate insulating film on the oxide film and the predetermined structure, and forming a gate electrode on the gate insulating film .

In this case, the forming of the oxide layer may include depositing an oxide layer so as to cover the buffer layer and the predetermined structure, depositing a photoresist by spin coating on the deposited oxide layer, and performing dry etching, Removing the photoresist and the oxide film deposited within the range exceeding the predetermined height.

The predetermined height may be equal to or greater than a height of the buffer layer in the predetermined structure and less than a height of the predetermined structure.

Meanwhile, the method for fabricating a semiconductor device according to an embodiment of the present invention may further include removing the oxide film after forming the gate electrode.

The etching step may include: forming a mask layer having a predetermined pattern on the semiconductor layer, dry-etching the semiconductor layer and the buffer layer, forming a mask layer having a predetermined width of the dry- Wet etching the sides of the dry etched structure to have a width less than the width of the dry etched structure, and removing the mask layer.

In this case, the wet-etching may be performed by wet-etching a tetra-methyl ammonium hydroxide (TMAH) solution with an etching solution.

Meanwhile, the semiconductor layer may be a structure in which a second semiconductor layer made of AlGaN or AlN is stacked on a first semiconductor layer made of GaN.

Meanwhile, the method of fabricating a semiconductor device according to an embodiment of the present invention may further include forming a source electrode and a drain electrode spaced from each other on the predetermined structure.

FIGS. 1A to 11 are views for explaining a method for manufacturing a semiconductor device according to various embodiments of the present invention; FIGS.
12 is a view for explaining a cross section of a semiconductor device manufactured according to an embodiment of the present invention,
13 is a view for explaining a cross section of a semiconductor device fabricated according to another embodiment of the present invention,
14 is a view for explaining a semiconductor device according to an embodiment of the present invention.

Various embodiments of the present invention will be described in detail with reference to the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the following embodiments can be modified into various other forms, and the technical scope of the present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Also, to "include" an element means that it may include other elements, rather than excluding other elements, unless specifically stated otherwise. Further, various elements and regions in the drawings are schematically drawn. Accordingly, the technical spirit of the present invention is not limited by the relative size or spacing depicted in the accompanying drawings.

Hereinafter, a semiconductor device according to various embodiments of the present invention, and a method for manufacturing a semiconductor device, will be described. In particular, the semiconductor device of the present invention can be realized as an element using a nitride semiconductor.

The nitride semiconductor is a semiconductor belonging to the III-V group semiconductor and containing nitrogen as the V group element. Gallium nitride (GaN), aluminum nitride (AIN), and indium nitride (InN). It is a wide-gap semiconductor having a larger band gap than that of the conventional semiconductor, and the bandgap can be largely changed by changing the concentration of gallium, indium and aluminum.

The semiconductor device in this specification uses such a nitride, and can be variously implemented as a transistor, a diode, and the like. Hereinafter, for ease of explanation, it is assumed that the semiconductor device is a transistor. Transistors control the current or voltage flow in an electronic circuit to amplify or act as a switch.

The term " deposition ", "growth ", and the like used hereinafter are used to mean the formation of a semiconductor material layer, and the layer or thin film formed through various embodiments of the present invention may be formed by an organometallic vapor deposition APCVD, LPCVD, UHCVD, PVD, electron beam (MOCVD), molecular beam epitaxy (MBE), and the like. Method, a resistance heating method, or the like. When the metal organic chemical vapor deposition (MOCVD) method is used, the flow rate of the gas injected into the MOCVD reaction chamber can be determined, and the thickness of the thin film grown according to the kind of the gas, the pressure inside the reaction chamber, The surface roughness, the doped concentration of the dopant, and the like. Particularly, the higher the temperature, the better the crystallinity of the thin film can be obtained, which should be limited in consideration of the physical properties of the reaction gas and the temperature at which the reaction occurs. In particular, ALD (Atomic layer deposition) can be used for precise growth. According to the ALD method, thin film growth can be controlled on an atomic basis.

As used herein, the term "semiconductor layer" refers to a layer composed of a semiconductor material and may be replaced by another term such as an epitaxial layer, a material layer, or the like.

1A to 11 are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, a substrate 100 is provided as shown in FIG. The substrate 100 is selected as a material capable of growing semiconductor material on its upper surface. In particular, if a nitride layer is intended to be grown, it is possible to have a hexagonal crystal system, for example a nitride layer sapphire (Al ₂ O ₃₎ used for the substrate, or a silicon carbide (SiC), silicon (Si), zinc oxide (ZnO), gallium arsenide (Ga), gallium nitride (GaN), spinel (MgAlO _4), such as a substrate material .

Then, a buffer layer 101 is formed on the substrate 100 as shown in Fig. The buffer layer 101 serves as a buffer layer for reducing crystal defects caused by the inconsistency of the crystal lattice of the substrate 100 and the crystal lattice formed thereon and serves as a resistance layer for preventing current leakage when a high voltage is applied can do. For example, the buffer layer 101 may be formed of a layer consisting of at least one of highly resistive GaN, GaN, InN, AlN, InGaN, AlGaN, InAlGaN and AlInN, The layer may consist of several kinds of nucleation layers to reduce the number of nucleation layers. The buffer layer 101 may be formed to a thickness of about 2 mu m, for example. On the other hand, the buffer layer 101 may be omitted.

Then, a semiconductor layer 102 is formed on the buffer layer 101 as shown in Fig. 1A. The semiconductor layer 102 may be an undoped GaN layer and, in some cases, may be a doped GaN layer. Doping with a high concentration of n-type dopant reduces the series resistance of the device and allows the current to flow better.

Meanwhile, according to another embodiment of the present invention, the semiconductor layer 102 may have a structure in which layers made of two different materials are stacked. That is, as shown in FIG. 1B, the first semiconductor layer 110 and the second semiconductor layer 120 may be stacked.

Referring to FIG. 1B, a first semiconductor layer 110 is formed on a buffer layer 101. The first semiconductor layer 110 may be composed of GaN. The first semiconductor layer 110 may be an undoped GaN layer, and in some cases, may be a doped GaN layer. Doping with a high concentration of n-type dopant reduces the series resistance of the device and allows the current to flow better. The first semiconductor layer 110 may be formed to a thickness of, for example, 60 nm.

Then, a second semiconductor layer 120 is formed on the first semiconductor layer 110 as shown in FIG. 1B. The second semiconductor layer 120 includes a semiconductor material different from the first semiconductor layer 110. In particular, the material of the second semiconductor layer 120 may differ from the material of the first semiconductor layer 110 by at least one of polarization property, energy bandgap and lattice constant. For example, at least one of the polarization ratio and the energy band gap of the second semiconductor layer 120 may be larger than that of the first semiconductor layer 110. For example, the second semiconductor layer 120 may be an AlGaN layer or an AlN layer. The second semiconductor layer 120 may be an undoped layer, but in some cases it may be a doped layer with certain impurities. The thickness of the second semiconductor layer 120 may be 20 nm to 30 nm.

The second semiconductor layer 120 may be formed to form a two dimensional electron gas (hereinafter, referred to as a 2DEG) on a part of the first semiconductor layer 110. The 2DEG may be formed in a region of the first semiconductor layer 110 below the heterojunction interface between the first semiconductor layer 110 and the second semiconductor layer 120. The 2DEG formed in the first semiconductor layer 110 may be used as a current path or channel between the source electrode and the drain electrode to be formed in a subsequent process. 2DEG is 8.8 × 10 ¹² cm ^- can have an electron mobility of Figure ¹ ^- ² ^{concentration, 1700 cm 2 · V -1 ·} s of.

GaN / AlGaN or GaN / AlN heterojunction is used. However, the present invention is not limited thereto, and any combination of materials capable of forming a 2DEG layer at the heterojunction interface may fall within the scope of the present invention. It is obvious to those skilled in the art that a detailed description thereof will be omitted.

The semiconductor device manufactured according to an embodiment of the present invention may be a high electron mobility transistor (HEMT) using the 2DEG as a channel. Alternatively, as described in FIG. 1A, a semiconductor layer 102 of the same material, which is not divided into the first and second semiconductor layers, may be used. Hereinafter, for convenience of explanation, the first semiconductor layer 110 and the second semiconductor layer In the case where the semiconductor layer 120 is used, the following processes will be described.

Next, a mask layer 130 having a predetermined pattern is formed on the second semiconductor layer 120 as shown in FIG. 2A. Specifically, the mask layer 130 having a predetermined pattern can be formed by using the exposure process. In this case, for example, an E-beam lithography technique can be used.

The pattern of the mask layer 130 includes a first region 20, a second region 22 spaced apart from the first region 20, and a third region 22 connecting the first region 20 and the second region 22, (21). The third region 21 of the mask layer 130 may have a width of about 500 nm, which is about 2 [mu] m in length (from the first region 20 to the second region 22). The thickness of the mask layer 130 may be about 50 nm.

Mask layer 130 is SiO _2, SiN _x (for example, Si ₃ N ₄₎ can be a dielectric or metal, Cr, Ni and the like, which cause a reaction in the etching solution used in the wet etching in a subsequent step It can be selected as a substance that does not exist.

On the other hand, FIG. 2A shows a part of the pattern of the mask layer 130, and is enlarged as shown in FIG. 2B. FIG. 2B illustrates a top view of the mask layer 130. FIG.

Referring to FIG. 2B, a flat zone or a notch is formed on the substrate 100, and the mask layer 130 is patterned in a direction perpendicular to FIG. 2B. That is, the third region 21 of the mask layer 130 is patterned to be perpendicular to the flat zone. The reason for this is to obtain a structure having a width of nano-size through wet etching to be performed in a subsequent step, taking advantage of the fact that the etching rate is significantly faster than the plane perpendicular to the flat zone.

2C shows a cross-section (A-A ') of the third region 21 of the mask layer 130. FIG.

Next, as shown in FIG. 3A, the first semiconductor layer 110 and the second semiconductor layer 120 under the mask layer 130 are dry-etched. Dry etching can be performed with a plasma using a halogen gas such as chlorine (Cl ₂ ), bromine (Br ₂ ), or iodine (I ₂ ). For example, TCP-RIE (transformer coupled plasma reactive ion etching) equipment can be used.

When dry etching is performed, a structure in which the first semiconductor layer 110 and the second semiconductor layer 120 are stacked under the mask layer 130 may be a trapezoidal structure as shown in FIG. 3A. According to another embodiment, the dry etching may be performed to the buffer layer 101 as shown in FIG. 3B. This is to widen the area of the side channel to be formed on the side of the first semiconductor layer 110 in the semiconductor device to be completed as will be described later. Hereinafter, it is assumed that the buffer layer 101 is dry-etched as shown in FIG. 3B and the subsequent processes will be described. However, this is for convenience of description, and a subsequent process may be performed without the buffer layer being etched as shown in FIG.

On the other hand, most of the side walls are not straight as shown in FIG. 3A or FIG. 3B only by dry etching. Its slanted angle is ~ 65 °. Accordingly, although not essential, according to an embodiment of the present invention, wet etching may be further performed to further narrow the width of the dry etched side wall while making the inclination thereof vertical.

More specifically, wet etching is performed using a tetra-methyl ammonium hydroxide (TMAH) solution. First, as shown in FIG. 4, the buffer layer 101, the second semiconductor layer 120, and the first semiconductor layer 110 are perpendicular to each other. This is because the etching rate of the upper region (region close to the mask layer 130) is slower than the lower region of the structure.

Then, as the wet etching time elapses, the width becomes narrow as shown in Fig. Such an etch selectively etched only in the lateral direction is anisotropic etching along the crystal planes of the Group III nitride semiconductor structures constituting the buffer layer 101, the first semiconductor layer 110 and the second semiconductor layer 120. [ etch) characteristics. Specifically, when wet etching is performed using a TMAH solution, the etching is performed only on the nitrogen face and not on the gallium face. The surface exposed by the dry etching in the previous step has a mostly nitrogen surface, so it can react strongly to the TMAH solution.

The directions of the side surfaces of the dry etched buffer layer 101, the first semiconductor layer 110 and the second semiconductor layer 120 are perpendicular to the flat zone of the substrate 100 and therefore have a higher etch rate than the horizontal surface . 5, the width of the buffer layer 101, the first semiconductor layer 110, and the second semiconductor layer 120 become narrower than the width of the mask layer 130 on the buffer layer 101, the first semiconductor layer 110, and the second semiconductor layer 120 as the wet etching proceeds.

On the other hand, as a result of experiments with different wet etching times, it was found that the width can be effectively controlled by controlling the wet time. In the experiment, immediately after dry etching, the structure was trapezoidal in shape, with an upper width of 400 nm and a lower width of ~ 550 nm. Then, wet etching was performed for 10, 25, 35 and 40 minutes respectively with TMAH solution (concentration 5%, 80 ° C), and the width of the structure was reduced to 300, 200, 100 and 50 nm, respectively. The etch rate was measured at 8.5 to 9 nm / min.

It is very difficult to precisely fabricate the width of the semiconductor layer to a nano level. However, according to the embodiment of the present invention which performs both the dry etching and the wet etching as described above, the width of the nano- Can be obtained. In addition, wet etching may also achieve additional effects such that the dry etched surface is planarized and the plasma damage induced on the dry etched surface can be removed.

As a result, the structure of the buffer layer 101, the first semiconductor layer 110, and the second semiconductor layer 120 having a width of nano-size smaller than the width of the mask layer 130 can be obtained.

Then, the mask layer 130 is removed as shown in FIG. As a result, a protruded structure as shown in Fig. 6 can be obtained. Hereinafter, the protruded structure will be referred to as a fin-shaped structure.

Then, the oxide film 140 is deposited on the portion removed by the wet etching and the dry etching. For example, as shown in FIG. 7, an oxide film 140 is deposited to cover the etched buffer layer 101 and the fin-shaped structure. The oxide film is an insulating material and is a structure for reducing a leakage current that can flow to the gate electrode or the buffer layer 101 to be generated in a subsequent process.

Oxide 140 may be configured to be selected from an insulating material such as _{SiO 2, Al 2 O 3,} Si 3 N 4, HfO 2.

Then, a photoresist 145 is deposited on the oxide film 140 as shown in FIG. The photoresist 145 may be deposited by spin coating. Spin coating is a coating method based on the principle that the fluid is spread by centrifugal force as the substrate is rotated at a very high speed. Since the photoresist has a constant viscosity, it can be applied relatively thick to the protruding region and relatively thick to the non-protruding region, depending on the nature of such photoresist when applied by a spin coating method. Thus, as shown in FIG. 8, a photoresist 145 is thinly deposited on the protruding fin-shaped structure, and the photoresist 145 is relatively thickly deposited on the other non-protruding regions.

Then, dry etching is performed. More specifically, when the dry etching is performed using the property that the photoresist 145 is deposited with a step difference, the photoresist 145 and the oxide film 140 are sequentially removed, and the photoresist 145 And the oxide film 140 deposited within a range exceeding a specific height can be removed.

This dry etching can be performed until the top surface of the fin-shaped structure, that is, the second semiconductor layer 120 is exposed. In the process, only the photoresist 145 is etched at portions where the photoresist 145 is relatively thickly deposited, and the oxide film 140 under the photoresist 145 can be protected. That is, after the dry etching is completed as shown in FIG. 9, the oxide film 140 having a constant height can be left beside the fin-shaped structure.

Using the property that the photoresist 145 is deposited with a step difference by spin coating as described above, the oxide film 140 having a constant height disposed next to the pin-shaped structure can be obtained by only dry etching without complicated processes have.

Then, as shown in FIG. 10, a gate insulating film 150 is deposited on the oxide film 140 and the fin-shaped structure. The gate insulating film 150 is a structure for electrically insulating the gate electrode and the fin-shaped structure. The gate insulating layer 150 may be formed of a material selected from Al ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , HfO _2, and the like.

A source electrode and a drain electrode, which are in contact with the second semiconductor layer 120, are formed with a region where a gate is to be formed therebetween. According to one example, a source electrode and a drain electrode can be formed in the following manner. Specifically, except for a region (contact hole) in which a source electrode and a drain electrode are to be formed, a mask layer is formed over the entire device. In this case, the gate insulating film deposited in the preceding step can be used as a mask layer without having to form a separate mask layer. The electrode can be deposited using a tron-beam evaporator in the mask layer and the contact hole. The electrode may be composed of an Au / Ni / Al / Ti metal layer. The electrode is then subjected to rapid thermal annealing. At this time, the heat treatment can be performed in an N ₂ atmosphere at 500 ° C (20 sec) - 800 ° C (30 sec). When the mask layer is lifted through the lift-off process, the source electrode and the drain electrode can be formed in the contact hole region.

Then, as shown in FIG. 11, a gate electrode 160 is formed on the gate insulating film 150. For example, the gate electrode 160 may be composed of an Au / Ni metal layer.

The completed semiconductor device has a 2DEG channel (i.e., Top channel) and side channels (i.e., Side-wall channels). This is shown in Fig.

12 is a cross-sectional view of a pin-shaped structure for explaining channels of a semiconductor device 1000 manufactured according to an embodiment of the present invention. 12, the semiconductor device 1000 has a 2DEG channel (i.e., Top channel) and side channels (i.e., Side-wall channels). Thus, on the I _D -V _G curve, two distinct transconductance peaks (g _m ) can be observed, one due to the side channels and the other due to the 2DEG channel.

Since the 2DEG channel and the side channels can be used simultaneously in this semiconductor device 1000, the number of electrons available at the time of device operation becomes relatively large, so that excellent device characteristics can be obtained. In addition to high frequency and high output devices, .

On the other hand, the height of the oxide film 140 may be equal to or higher than the height of the buffer layer 101 which is the lower portion of the fin-shaped structure. However, it does not exceed the height of the pin-shaped structure. For example, as shown in FIG. 12, if the height of the buffer layer 101 and the height of the oxide film 140 are equal to each other, the leakage current can be effectively blocked while maximizing the area of the side channel.

According to another embodiment of the present invention, a process of removing the oxide film 140 remaining under the gate electrode 160 may be further performed. A cross section of the semiconductor device according to this embodiment is shown in Fig.

Referring to FIG. 13, it can be seen that the lower portion of the gate electrode 150 of the semiconductor device 1000 'is an empty space 7 after the oxide film 140 is removed. In order to remove the oxide film 140, the structure may be treated with an etching solution that can selectively etch the oxide film 140. For example, when the oxide film 140 is SiO ₂ , hydrofluoric acid (HF) can be used as an etching solution. Since the oxide film 140 is removed, the lower portion of the gate electrode 160 becomes the void space 7 and the air forming the void space 7 is a perfect insulator. Therefore, The current can be blocked more completely.

Fig. 14 shows the overall structure of a semiconductor device that can be manufactured according to the above-described embodiment.

14, the semiconductor device 2000 includes a substrate 100, a buffer layer 101, a first semiconductor layer 110, a second semiconductor layer 120, an oxide film 140, a gate insulating film 150, An electrode 160, a source electrode 170, and a drain electrode 180. Here, the buffer layer 101 may be omitted. Since the configuration of the semiconductor device 2000 has been described above, repetitive description will be omitted in the overlapping range.

Although the first semiconductor layer 110 and the second semiconductor layer 120 are illustrated in FIG. 14, according to another embodiment, instead of the first semiconductor layer 110 and the second semiconductor layer 120 being stacked, , Or one semiconductor layer may be disposed.

Although the manufacturing method described with reference to FIGS. 1 to 13 has been described as manufacturing a single pin-shaped structure, as shown in FIG. 14, a plurality of pin-shaped structures can be manufactured. The pin-shaped structure operates as a path through which electrons can move when the semiconductor device 2000 is on, and conversely, when the semiconductor device 2000 is off, So as to prevent movement.

As the number of the pin shapes increases, the effect of increasing the channel is obtained, so that the current characteristics can be further improved. In addition, since the gate electrode 600 surrounds the pin-shaped structure of the present semiconductor device 2000, the electron moving area can be widened. Further, the 2DEG is formed in the first semiconductor layer by the second semiconductor layer 110, and a high concentration of electrons can be induced here, so that the electron mobility can be further increased. In addition, the semiconductor device 2000 can operate using both the channel formed by the 2DEG and the side channel formed in the first semiconductor layer 110. Therefore, the semiconductor device 2000 can be applied to a high-frequency device and a high-output power device.

The source electrode 170 is a structure for electrically connecting an external element and the present semiconductor element 2000 to supply a carrier (electron or hole) to the semiconductor element 2000.

The drain electrode 180 is spaced apart from the source electrode 170 with the gate electrode 160 interposed therebetween. The drain electrode 180 serves as a path through which the carriers supplied from the source electrode 160 move to the external device. The source electrode 170 and the drain electrode 180 are formed of an Au / Ni / Al / Ti metal layer for forming an ohmic contact with the first semiconductor layer 110 and / or the second semiconductor layer 120 . Here, an ohmic contact is a non-rectifying or resistive contact, in which the I-V curve follows the general Ohm's law.

The gate electrode 160 is configured such that a voltage for controlling on / off operation of the semiconductor device 1000 can be applied.

The semiconductor device 2000 manufactured according to the embodiment of the present invention has a structure in which the oxide film 140 is disposed under the gate electrode 160 to significantly reduce the leakage current that can flow to the gate electrode 160 and the buffer layer 101 . According to another embodiment, as described with reference to FIG. 13, the oxide film 140 may be removed to form an empty space under the gate electrode 160. In this case, a more perfect insulation effect can be obtained than when the oxide film 140 is present.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It goes without saying that the example can be variously changed. Accordingly, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. * * * * * Recently Added Patents

100: substrate 110: first semiconductor layer
120: second semiconductor layer 140: oxide film
150: gate insulating film 160: gate electrode

Claims

A method of manufacturing a semiconductor device,
Forming a semiconductor layer on the buffer layer;
Etching a portion of the semiconductor layer and the buffer layer to have a predetermined structure;
Forming an oxide layer on the etched buffer layer, the oxide layer having a predetermined height lower than the height of the predetermined structure;
Forming a gate insulating film on the oxide film and the predetermined structure;
Forming a gate electrode on the gate insulating film; And
And removing the oxide film after forming the gate electrode.

The method according to claim 1,
The forming of the oxide film may include:
Depositing an oxide layer to cover the buffer layer and the predetermined structure;
Depositing a photoresist on the deposited oxide layer by a spin coating method; And
Removing the photoresist and the oxide film deposited within a range exceeding the predetermined height by performing dry etching.

The method according to claim 1,
The predetermined height may be,
The height of the buffer layer in the predetermined structure is greater than or equal to the height of the buffer layer in the predetermined structure.

delete

The method according to claim 1,
Wherein the step of etching comprises:
Forming a mask layer having a predetermined pattern on the semiconductor layer, and dry-etching the semiconductor layer and the buffer layer;
Wet etching the sides of the dry etched structure such that the width of a particular region of the dry etched structure has a width less than the width of the mask layer; And
And removing the mask layer. &Lt; Desc / Clms Page number 19 >

6. The method of claim 5,
Wherein the wet etching comprises:
Wherein the tetra-methyl ammonium hydroxide (TMAH) solution is wet-etched with an etching solution.

The method according to claim 1,
Wherein:
And a second semiconductor layer made of AlGaN or AlN is stacked on the first semiconductor layer made of GaN.

The method according to claim 1,
And forming source and drain electrodes spaced apart from each other on the predetermined structure.