CN115579290A - Preparation method of p-GaN enhanced device - Google Patents
Preparation method of p-GaN enhanced device Download PDFInfo
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- CN115579290A CN115579290A CN202211592150.7A CN202211592150A CN115579290A CN 115579290 A CN115579290 A CN 115579290A CN 202211592150 A CN202211592150 A CN 202211592150A CN 115579290 A CN115579290 A CN 115579290A
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 172
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 81
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 28
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000002161 passivation Methods 0.000 claims description 127
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 38
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 37
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 35
- 229910052733 gallium Inorganic materials 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 18
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
The invention discloses a preparation method of a p-GaN enhancement type device, which relates to the technical field of semiconductor device manufacturing, wherein a second gallium nitride aluminum layer is formed in a region above a first gallium nitride aluminum layer except for p-GaN, because the thickness of the first gallium nitride aluminum layer below the p-GaN cannot be too thick, the p-GaN cannot completely exhaust two-dimensional electron gas below a grid electrode, and the second gallium nitride aluminum layer covers the region outside the p-GaN and is not below the p-GaN, in the region outside the p-GaN, the second gallium nitride aluminum layer can provide more two-dimensional electron gas, the higher the concentration of the two-dimensional electron gas is, the higher the current of the device is, and the current of the p-GaN enhancement type device is improved. The invention can improve the current of the device on the basis of not influencing the formation of the p-GaN enhancement type device.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a p-GaN enhanced device.
Background
The GaN material has the advantages of large forbidden band width, high breakdown field strength, high electron mobility, good thermal conductivity and the like, and has huge potential when being applied to high-temperature, high-frequency, high-breakdown-voltage and high-power switching devices. The AlGaN/GaN heterojunction based on GaN material system has very strong piezoelectric polarization and spontaneous polarization effects, and the two-dimensional electron gas surface density can reach 10 even if the AlGaN/GaN heterojunction is not modulated and doped by a barrier layer 13 cm -2 In order of magnitude, and the two-dimensional electron gas is separated from the doping center, so the electron mobility can reach up to 2000cm 2 V -1 S -1 Meanwhile, gaN can be epitaxially grown on a Si substrate in a large area, and the material cost is effectively reduced. Therefore, the GaN power device (GaN-based power device) has wide application prospect.
In the power device based on the AlGaN/GaN heterojunction, due to the polarization effect of a nitride material system, the GaN-based power device is a natural depletion device, but when the depletion device is applied to a circuit, a negative gate drive circuit needs to be designed to realize the on-off control of the device, so that the complexity and the cost of the circuit are greatly increased, and the depletion device has defects in the fail safety capability. Therefore, the development of the enhancement type GaN-based power device is the focus of research at present.
An enhancement type GaN power device based on a P-type gate is a mainstream technical scheme at present, and the scheme realizes enhancement by depending on the depletion effect of P-GaN on two-dimensional electron gas. In the conventional P-GaN enhancement type HEMT device, because two-dimensional electron gas below the gate needs to be depleted by P-GaN, the thickness of the AlGaN layer cannot be too thick, so that the two-dimensional electron gas density is high, and the P-GaN cannot completely deplete the two-dimensional electron gas below the gate, so that an enhancement type device cannot be formed, therefore, the current ratio of the conventional P-GaN enhancement type HEMT device (P-type gate enhancement type device) is small, which is a disadvantage of the P-type gate technology.
In summary, how to increase the current of the device without affecting the formation of the p-GaN enhancement device becomes a problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a preparation method of a p-GaN enhancement type device, which can improve the current of the device on the basis of not influencing the formation of the p-GaN enhancement type device.
In order to achieve the purpose, the invention provides the following scheme:
a method of fabricating a p-GaN enhanced device, the method comprising:
putting a silicon substrate into MOCVD equipment, and sequentially epitaxially growing a gallium nitride buffer layer, a gallium nitride channel layer and a first gallium nitride aluminum layer on the silicon substrate to obtain a wafer;
taking the wafer out of the MOCVD equipment, and depositing a first passivation layer on the surface of the first gallium nitride aluminum layer to obtain the wafer deposited with the first passivation layer;
etching the wafer deposited with the first passivation layer, and respectively etching away the first passivation layer of the source electrode region, the gate source region, the drain electrode region and the gate drain region to obtain the wafer etched with the first passivation layer; the gate source region is a region between the gate electrode and the source electrode; the gate drain region is a region between the gate electrode and the drain electrode;
putting the wafer etched with the first passivation layer into the MOCVD equipment again, and continuously growing a second gallium aluminum nitride layer on the surface of the wafer etched with the first passivation layer to obtain the wafer grown with the second gallium aluminum nitride layer;
taking the wafer on which the second layer of gallium aluminum nitride layer grows out of the MOCVD equipment, removing the first passivation layer of the grid electrode region and the second layer of gallium aluminum nitride layer above the first passivation layer of the grid electrode region, forming a grid groove, and obtaining the wafer on which the grid groove is formed;
depositing a second passivation layer on the surface of the wafer with the grid electrode groove formed to obtain the wafer with the second passivation layer deposited;
removing the second passivation layer of the gate electrode region from the wafer deposited with the second passivation layer, and exposing the first gallium aluminum nitride layer of the gate electrode region to obtain the wafer exposed with the first gallium aluminum nitride layer;
putting the wafer exposed with the first gallium aluminum nitride layer into the MOCVD equipment again, and continuously growing a p-type gallium nitride layer on the surface of the wafer exposed with the first gallium aluminum nitride layer to obtain the wafer grown with the p-type gallium nitride layer;
taking the wafer with the p-type gallium nitride layer grown out of the MOCVD equipment, removing the second passivation layer and the p-type gallium nitride layer above the second passivation layer from the wafer with the p-type gallium nitride layer grown out, and reserving the p-type gallium nitride layer in the grid electrode area to obtain the wafer with the electrode to be manufactured;
and manufacturing a source electrode, a grid electrode and a drain electrode on the wafer on which the electrode is to be manufactured to obtain the p-GaN enhancement device.
Optionally, the material of the first passivation layer is silicon dioxide or silicon nitride.
Optionally, the etching is performed on the wafer on which the first passivation layer is deposited, and the first passivation layer in the source electrode region, the gate source region, the drain electrode region, and the gate drain region is etched away respectively, so as to obtain the wafer on which the first passivation layer is etched, which specifically includes:
and etching the wafer deposited with the first passivation layer by utilizing photoetching and etching processes to etch the first passivation layer of the source electrode region, the gate source region, the drain electrode region and the gate drain region respectively, and only reserving the first passivation layer of the gate electrode region to obtain the wafer etched with the first passivation layer.
Optionally, the thickness of the second layer of aluminum gallium nitride layer in the wafer after the second layer of aluminum gallium nitride layer is grown is smaller than the thickness of the first passivation layer.
Optionally, the taking out the wafer on which the second layer of gallium nitride aluminum layer grows from the MOCVD equipment, removing the first passivation layer of the gate electrode region and the second layer of gallium nitride aluminum layer on the first passivation layer of the gate electrode region to form a gate groove, and obtaining the wafer on which the gate groove is formed specifically includes:
and taking the wafer on which the second layer of gallium aluminum nitride layer grows out of the MOCVD equipment, removing the first passivation layer of the grid electrode region in a wet etching mode, and removing the second layer of gallium aluminum nitride layer above the first passivation layer of the grid electrode region along with the first passivation layer of the grid electrode region to form a grid groove, thereby obtaining the wafer on which the grid groove is formed.
Optionally, the material of the second passivation layer is silicon nitride, silicon dioxide, aluminum nitride or aluminum oxide.
Optionally, the thickness of the p-type gallium nitride layer in the wafer after the p-type gallium nitride layer is grown is smaller than the thickness of the second passivation layer.
Optionally, the wafer after the p-type gallium nitride layer is grown is taken out of the MOCVD equipment, the second passivation layer and the p-type gallium nitride layer above the second passivation layer are removed from the wafer after the p-type gallium nitride layer is grown, the p-type gallium nitride layer in the gate electrode region is reserved, and the wafer of the electrode to be manufactured is obtained, which specifically includes:
and taking the wafer on which the p-type gallium nitride layer grows out of the MOCVD equipment, removing a second passivation layer in the wafer on which the p-type gallium nitride layer grows in a wet etching mode, removing the p-type gallium nitride layer above the second passivation layer along with the second passivation layer, and reserving the p-type gallium nitride layer in the grid electrode area to obtain the wafer on which the electrode is to be manufactured.
Optionally, the manufacturing of the source electrode, the gate electrode, and the drain electrode on the wafer on which the electrode is to be manufactured to obtain the p-GaN enhancement device specifically includes:
and finally, manufacturing a grid electrode in the grid electrode area on the wafer of the electrode to be manufactured, and obtaining the p-GaN enhancement device.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a preparation method of a p-GaN enhancement type device, which is characterized in that a second gallium nitride aluminum layer is formed in a region above a first gallium nitride aluminum layer and outside p-GaN, because the thickness of the first gallium nitride aluminum layer below the p-GaN cannot be too thick, the p-GaN cannot completely exhaust two-dimensional electron gas below a grid electrode, and the second gallium nitride aluminum layer covers the region outside the p-GaN and is not below the p-GaN, the second gallium nitride aluminum layer can provide more two-dimensional electron gas in the region outside the p-GaN, the higher the concentration of the two-dimensional electron gas is, the larger the current of the device is, and the current of the p-GaN enhancement type device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a flow chart of an embodiment of a method for fabricating a p-GaN enhancement device of the invention;
FIG. 2 is a schematic view of a wafer structure according to the present invention;
FIG. 3 is a schematic diagram of a wafer structure after etching a first passivation layer according to the present invention;
FIG. 4 is a schematic view of a wafer structure after a second GaN aluminum layer is grown according to the present invention;
FIG. 5 is a schematic view of a wafer structure after forming a gate trench according to the present invention;
FIG. 6 is a schematic view of a wafer structure after exposing a first GaN aluminum layer according to the present invention;
FIG. 7 is a schematic view of a wafer structure after a p-type GaN layer is grown according to the present invention;
FIG. 8 is a schematic diagram of a wafer structure to be processed with an electrode according to the present invention;
FIG. 9 is a schematic diagram of a p-GaN enhancement mode device of the invention.
Description of the symbols:
the structure of the solar cell comprises a 1-silicon substrate, a 2-gallium nitride buffer layer, a 3-gallium nitride channel layer, a 4-first gallium nitride aluminum layer, 5-two-dimensional electron gas, a 6-first passivation layer, a 7-second gallium nitride aluminum layer, an 8-grid groove, a 9-second passivation layer, a 10-p type gallium nitride layer, an 11-source electrode, a 12-grid electrode and a 13-drain electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a preparation method of a p-GaN enhancement type device, which can improve the current of the device on the basis of not influencing the formation of the p-GaN enhancement type device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
FIG. 1 is a flow chart of an embodiment of a method for fabricating a p-GaN enhancement device of the invention. Referring to fig. 1, the method for manufacturing the p-GaN enhanced device comprises the following steps:
step 101: and putting the silicon substrate into MOCVD equipment, and sequentially epitaxially growing a gallium nitride buffer layer, a gallium nitride channel layer and a first gallium nitride aluminum layer on the silicon substrate to obtain the wafer.
Step 102: and taking the wafer out of the MOCVD equipment, and depositing a first passivation layer on the surface of the first gallium nitride aluminum layer to obtain the wafer deposited with the first passivation layer.
In step 102, the material of the first passivation layer is silicon dioxide or silicon nitride.
Step 103: etching the wafer deposited with the first passivation layer, and respectively etching away the first passivation layer of the source electrode region, the gate source region, the drain electrode region and the gate drain region to obtain the wafer etched with the first passivation layer; the gate source region is a region between the gate electrode and the source electrode; the gate-drain region is a region between the gate electrode and the drain electrode.
The step 103 specifically includes:
and etching the wafer deposited with the first passivation layer by utilizing photoetching and etching processes to etch the first passivation layer of the source electrode region, the gate source region, the drain electrode region and the gate drain region respectively, and only reserving the first passivation layer of the gate electrode region to obtain the wafer etched with the first passivation layer.
In step 103, the source electrode region is a region where the source electrode is located, the gate source region is a region between the gate electrode and the source electrode, the drain electrode region is a region where the drain electrode is located, the gate drain region is a region between the gate electrode and the drain electrode, and the gate electrode region is a region where the gate electrode is located.
Step 104: and putting the wafer etched with the first passivation layer into MOCVD equipment again, and continuing to grow a second gallium nitride aluminum layer on the surface of the wafer etched with the first passivation layer to obtain the wafer grown with the second gallium nitride aluminum layer.
In step 104, the thickness of the second aluminum gallium nitride layer in the wafer after the second aluminum gallium nitride layer is grown is smaller than that of the first passivation layer.
Step 105: and taking the wafer on which the second gallium nitride aluminum layer grows out of the MOCVD equipment, removing the first passivation layer of the grid electrode region and the second gallium nitride aluminum layer above the first passivation layer of the grid electrode region to form a grid groove, and obtaining the wafer on which the grid groove is formed.
The step 105 specifically includes:
and taking the wafer on which the second layer of gallium aluminum nitride layer grows out of the MOCVD equipment, removing the first passivation layer of the grid electrode region in a wet etching mode, and removing the second layer of gallium aluminum nitride layer above the first passivation layer of the grid electrode region along with the first passivation layer of the grid electrode region to form a grid groove, so as to obtain the wafer on which the grid groove is formed.
Step 106: and depositing a second passivation layer on the surface of the wafer with the grid electrode groove to obtain the wafer with the second passivation layer deposited.
In step 106, the material of the second passivation layer is silicon nitride, silicon dioxide, aluminum nitride, or aluminum oxide.
Step 107: and removing the second passivation layer of the grid electrode region from the wafer deposited with the second passivation layer, and exposing the first gallium aluminum nitride layer of the grid electrode region to obtain the wafer exposed with the first gallium aluminum nitride layer.
Step 108: and putting the wafer exposed with the first gallium aluminum nitride layer into MOCVD equipment again, and continuously growing a p-type gallium nitride layer on the surface of the wafer exposed with the first gallium aluminum nitride layer to obtain the wafer grown with the p-type gallium nitride layer.
In step 108, the thickness of the p-type gallium nitride layer in the wafer after the p-type gallium nitride layer is grown is smaller than that of the second passivation layer.
Step 109: and taking the wafer on which the p-type gallium nitride layer grows out of the MOCVD equipment, removing the second passivation layer and the p-type gallium nitride layer above the second passivation layer from the wafer on which the p-type gallium nitride layer grows, and reserving the p-type gallium nitride layer in the grid electrode area to obtain the wafer on which the electrode is to be manufactured.
This step 109 specifically includes:
and taking the wafer on which the p-type gallium nitride layer grows out of the MOCVD equipment, removing a second passivation layer in the wafer on which the p-type gallium nitride layer grows in a wet etching mode, removing the p-type gallium nitride layer above the second passivation layer along with the second passivation layer, and reserving the p-type gallium nitride layer in the grid electrode area to obtain the wafer on which the electrode is to be manufactured.
Step 110: and manufacturing a source electrode, a grid electrode and a drain electrode on the wafer of which the electrode is to be manufactured to obtain the p-GaN enhancement device.
The step 110 specifically includes:
and finally, manufacturing a grid electrode in the grid electrode area on the wafer of the electrode to be manufactured, and obtaining the p-GaN enhancement device.
The technical solution of the present invention is illustrated by a specific example below:
the preparation method of the p-GaN enhanced device comprises the following process steps:
the process comprises the following steps: the silicon substrate 1 (Si substrate) is placed in MOCVD equipment, and a gallium nitride buffer layer 2 (GaN buffer layer), a gallium nitride channel layer 3 (GaN channel layer), and a first gallium aluminum nitride layer 4 (AlGaN-1 layer) are epitaxially grown in this order, so that a wafer (wafer) as shown in fig. 2 is obtained.
The process step 2: taking the wafer out of the MOCVD equipment, and depositing a passivation layer on the AlGaN-1 surface, wherein the passivation layer is a first passivation layer 6 (first passivation layer), and the material of the passivation layer can be silicon dioxide (SiO) 2 ) And silicon nitride (SiN), and the like, and then only the passivation layer of the gate region (gate electrode region) is retained by using the processes of photolithography, etching, and the like, so as to obtain the wafer with the first passivation layer 6 etched as shown in fig. 3.
And 3, a process step: and putting the wafer into the MOCVD equipment again, and continuing to grow the second gallium aluminum nitride layer 7 (AlGaN-2 layer) to obtain the wafer after the second gallium aluminum nitride layer 7 grows as shown in fig. 4. The thicker the thickness of the second gallium nitride aluminum layer 7 is, the higher the concentration of the two-dimensional electron gas is, but the thickness of the second gallium nitride aluminum layer is smaller than that of the first passivation layer 6, so that the first passivation layer 6 cannot be completely wrapped, and part of the side wall of the first passivation layer 6 needs to be exposed, thereby facilitating the subsequent removal of the first passivation layer 6.
After the AlGaN-1 layer 4 grows, the novel enhanced GaN power device needs to enter MOCVD equipment again to continue to grow the AlGaN-2 layer 7. The first AlGaN layer 4 (first gallium aluminum nitride layer) cannot be too thick, if too thick, the two-dimensional electron gas concentration is too high, and p-GaN cannot completely exhaust the two-dimensional electron gas below the gate, but the second AlGaN layer 7 (second gallium aluminum nitride layer) can be thicker, because the second AlGaN layer 7 covers the region outside the gate, the two-dimensional electron gas concentration is very high (which can improve the current of the device) in the region outside the gate, and the two-dimensional electron gas concentration below the gate is lower (only AlGaN-1 is below the gate), and p-GaN can completely exhaust the two-dimensional electron gas below the gate.
And 4, a process step: the first passivation layer 6 in the gate region is removed by wet etching, and after the removal, the AlGaN-2 layer 7 above the first passivation layer is also removed along with the first passivation layer, so that a gate groove is formed, and the wafer with the gate groove formed as shown in fig. 5 is obtained.
And 5, a process step: a second passivation layer 9 (second passivation layer) is deposited in one piece and serves as a gate dielectric for the gate electrode, and may be silicon nitride (SiN), silicon dioxide (SiO) 2 ) Aluminum nitride (AlN), aluminum oxide (Al) 2 O 3 ) And the passivation layers of the gate region are removed, and the AlGaN-1 layer 4 of the gate region is exposed, so as to obtain the wafer with the first gallium aluminum nitride layer 4 exposed as shown in fig. 6.
The process step 6: the wafer is placed into the MOCVD equipment again, and a p-type gallium nitride layer 10 (p-GaN layer) continues to grow, so that the wafer after the p-type gallium nitride layer 10 grows as shown in fig. 7 is obtained. The thickness of the p-GaN layer 10 is smaller than the thickness of the second passivation layer 9 for subsequent removal of the second passivation layer 9.
After the groove structure is formed on the grid electrode of the novel enhanced GaN power device manufactured by the invention, the novel enhanced GaN power device needs to enter MOCVD equipment again to continue to grow the p-GaN layer 10.
The process step 7: and removing the second passivation layer 9 by wet etching, and removing the p-GaN above the second passivation layer, and finally, only leaving the p-GaN in the gate region, thereby obtaining the wafer to be provided with the electrode as shown in fig. 8.
The process step 8: ohmic contacts are formed in the source and drain regions (source electrode region and drain electrode region), and a source electrode 11 and a drain electrode 13 are formed, and finally a gate electrode 12 (gate electrode) is formed on the gate (gate region), thereby obtaining a P-GaN enhancement type device (P-gate-based enhancement type GaN power device) as shown in fig. 9. The current of the P-type gate enhanced power device (P-GaN enhanced device) finally obtained by the preparation method is larger than that of the conventional P-type gate enhanced device.
Compared with the structure of the existing p-type gate enhancement type device, the novel enhancement type GaN power device (p-GaN enhancement type device) manufactured by the preparation method provided by the invention is additionally provided with an AlGaN-2 layer. According to the GaN enhanced power device, namely the p-GaN enhanced device, by utilizing MOCVD equipment, after AlGaN (gallium aluminum nitride) is extended outwards, a passivation layer is deposited on a grid, then the grid enters the MOCVD equipment again to grow AlGaN, so that a grid groove structure is formed, then the passivation layer is deposited outside a groove area, the grid enters the MOCVD equipment again to grow a p-GaN layer 10, after the growth is completed, the p-GaN outside the grid is removed, and a source electrode 11 (source electrode), a drain electrode 13 (drain electrode) and a grid electrode are respectively manufactured, so that the enhanced power device is formed. And finally, the p-GaN layer 10 of the grid electrode is reserved through epitaxial regrown p-GaN and a wet etching process, so that a conventional dry etching method is avoided, etching damage to the AlGaN surface cannot be formed, and the novel enhanced power device (enhanced device) manufactured by the method has larger conduction current, better dynamic performance (because no etching damage exists) and good application prospect.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principle and the embodiment of the present invention are explained by applying specific examples, and the above description of the embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (9)
1. A method for preparing a p-GaN enhancement type device is characterized by comprising the following steps:
putting a silicon substrate into MOCVD equipment, and sequentially epitaxially growing a gallium nitride buffer layer, a gallium nitride channel layer and a first gallium nitride aluminum layer on the silicon substrate to obtain a wafer;
taking the wafer out of the MOCVD equipment, and depositing a first passivation layer on the surface of the first gallium nitride aluminum layer to obtain the wafer deposited with the first passivation layer;
etching the wafer deposited with the first passivation layer, and etching the first passivation layer of the source electrode region, the gate source region, the drain electrode region and the gate drain region respectively to obtain the wafer etched with the first passivation layer; the gate source region is a region between the gate electrode and the source electrode; the gate drain region is a region between the gate electrode and the drain electrode;
putting the wafer etched with the first passivation layer into the MOCVD equipment again, and continuously growing a second gallium aluminum nitride layer on the surface of the wafer etched with the first passivation layer to obtain the wafer grown with the second gallium aluminum nitride layer;
taking the wafer on which the second layer of gallium aluminum nitride layer grows out of the MOCVD equipment, removing the first passivation layer of the grid electrode region and the second layer of gallium aluminum nitride layer above the first passivation layer of the grid electrode region, forming a grid groove, and obtaining the wafer on which the grid groove is formed;
depositing a second passivation layer on the surface of the wafer with the grid electrode groove formed to obtain the wafer with the second passivation layer deposited;
removing the second passivation layer of the grid electrode region from the wafer deposited with the second passivation layer, and exposing the first gallium aluminum nitride layer of the grid electrode region to obtain the wafer exposed with the first gallium aluminum nitride layer;
putting the wafer exposed with the first gallium aluminum nitride layer into the MOCVD equipment again, and continuously growing a p-type gallium nitride layer on the surface of the wafer exposed with the first gallium aluminum nitride layer to obtain the wafer grown with the p-type gallium nitride layer;
taking the wafer with the p-type gallium nitride layer grown out of the MOCVD equipment, removing the second passivation layer and the p-type gallium nitride layer above the second passivation layer from the wafer with the p-type gallium nitride layer grown, and reserving the p-type gallium nitride layer in the grid electrode area to obtain the wafer with the electrode to be manufactured;
and manufacturing a source electrode, a grid electrode and a drain electrode on the wafer on which the electrode is to be manufactured to obtain the p-GaN enhancement device.
2. The method of claim 1, wherein the first passivation layer is made of silicon dioxide or silicon nitride.
3. The method for manufacturing a p-GaN enhanced device according to claim 1, wherein the etching the wafer deposited with the first passivation layer to etch the first passivation layer of the source electrode region, the gate source region, the drain electrode region and the gate drain region respectively to obtain the wafer etched with the first passivation layer comprises:
and etching the wafer deposited with the first passivation layer by utilizing photoetching and etching processes, respectively etching the first passivation layers of the source electrode region, the gate source region, the drain electrode region and the gate drain region, and only reserving the first passivation layer of the gate electrode region to obtain the wafer etched with the first passivation layer.
4. The method of claim 1, wherein the thickness of the second aluminum gallium nitride layer in the wafer after the second aluminum gallium nitride layer is grown is smaller than the thickness of the first passivation layer.
5. The method for manufacturing a p-GaN enhanced device according to claim 1, wherein the step of taking out the wafer on which the second layer of gallium aluminum nitride layer is grown from the MOCVD equipment, removing the first passivation layer of the gate electrode region and the second layer of gallium aluminum nitride layer on the first passivation layer of the gate electrode region to form the gate groove, and obtaining the wafer on which the gate groove is formed specifically includes:
and taking the wafer on which the second layer of gallium aluminum nitride layer grows out of the MOCVD equipment, removing the first passivation layer of the grid electrode region in a wet etching mode, and removing the second layer of gallium aluminum nitride layer above the first passivation layer of the grid electrode region along with the first passivation layer of the grid electrode region to form a grid groove, thereby obtaining the wafer on which the grid groove is formed.
6. The method according to claim 1, wherein the passivation layer of the second layer is made of silicon nitride, silicon dioxide, aluminum nitride or aluminum oxide.
7. The method according to claim 1, wherein the thickness of the p-type gallium nitride layer in the wafer after the p-type gallium nitride layer is grown is smaller than that of the second passivation layer.
8. The method for preparing a p-GaN enhanced device according to claim 1, wherein the step of taking out the wafer after the growth of the p-type gallium nitride layer from the MOCVD equipment, removing the second passivation layer and the p-type gallium nitride layer on the second passivation layer from the wafer after the growth of the p-type gallium nitride layer, and reserving the p-type gallium nitride layer in the gate electrode region to obtain the wafer of the electrode to be manufactured specifically comprises the steps of:
and taking the wafer with the p-type gallium nitride layer grown out of the MOCVD equipment, removing a second passivation layer in the wafer with the p-type gallium nitride layer grown out in a wet etching mode, removing the p-type gallium nitride layer above the second passivation layer along with the second passivation layer, and reserving the p-type gallium nitride layer in the grid electrode area to obtain the wafer with the electrode to be manufactured.
9. The method of claim 1, wherein the fabricating a source electrode, a gate electrode and a drain electrode on the wafer on which the electrode is to be fabricated to obtain a p-GaN enhancement mode device comprises:
and finally, manufacturing a grid electrode in the grid electrode area on the wafer of the electrode to be manufactured, and obtaining the p-GaN enhancement device.
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