CN114447113A - Novel Fin structure GaN HEMT device based on under-grid imaging and preparation method thereof - Google Patents
Novel Fin structure GaN HEMT device based on under-grid imaging and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention discloses a novel Fin structure GaN HEMT device based on under-grid imaging and a preparation method thereof, wherein the device comprises: the epitaxial substrate, a source electrode region, a drain electrode region, a passivation layer, ohmic metal, a second barrier layer and a gate electrode; the epitaxial substrate comprises a substrate layer, a nucleating layer, a buffer layer and a first barrier layer from bottom to top; the first barrier layer is positioned above the buffer layer; the source electrode area and the drain electrode area are positioned on two sides of the buffer layer and the first barrier layer; the ohmic metal is positioned above the source electrode region and the drain electrode region; the passivation layer covers the first barrier layer and the ohmic metal, and a preset gate groove area is arranged in the middle of the passivation layer; the depth of the preset gate groove area is equal to or greater than the depth of the passivation layer; the first barrier layer comprises a preset array groove region; the second barrier layer covers the preset array groove area; the second barrier layer is covered with a gate electrode. The device has high current and high power output capability.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a novel Fin structure GaN HEMT device based on under-grid imaging and a preparation method thereof.
Background
The forbidden band width of the GaN (gallium nitride) material is about 3.4eV, and compared with the first and second generation semiconductor materials, the GaN (gallium nitride) material has higher breakdown field strength and breakdown voltage, so that the GaN (gallium nitride) material has obvious advantages in the aspect of large output power. In addition, GaN-based materials such as AlGaN, GaN, InAlN, and the like have the advantage of changing the material forbidden bandwidth by adjusting the material composition, and materials with different forbidden bandwidths can be combined to form a heterojunction, and even if doping is not performed, 2DEG (two-dimensional Electron gas) with High surface Electron density can be formed on the surface of the heterojunction, so that a GaN-based HEMT (High Electron Mobility Transistor) is suitable for manufacturing a microwave millimeter wave power amplifier and is mainly applied to radar and communication base stations. With the shifting of the communication frequency band to a higher band, the gate length of the device must be reduced and the high-speed flow of carriers in the channel must be ensured to meet the high-frequency performance. However, when the gate length is reduced to a deep submicron range, short channel effects are caused, which are reflected in threshold voltage drift, increased subthreshold swing, reduced drain induced barrier, and the like, mainly due to the weakened gate control capability above the channel and the enhanced effect of the drain electric field on the channel.
In order to solve the above problems, a Fin structure is proposed by those skilled in the art. The grid electrode of the Fin structure comprises a top grid and two side wall grids, and three sides surround the nano channel. The early Fin structure adopts a bulk silicon substrate and is applied to an MOS (Metal-Oxide-Semiconductor) device, and the defects that source and drain are penetrated, the process is complicated and extra isolation is required to be provided, so that the Fin structure is considered to be transplanted to a GaN-based device.
However, in the prior art, the GaN-based Fin HEMT etches partial region potential barriers in the preparation process, so that the effective gate width is reduced, the actual current conduction area is reduced, the actual current conduction capability is degraded, and the layout area is wasted along with the continuous improvement of the integration requirement; the etching damage also causes the problems of lattice stress release, 2DEG concentration reduction in a channel, output current density reduction, grid leakage increase, parasitic capacitance increase and the like. These problems can seriously affect the performance of the device, and the development and application range of the device in the high frequency field are limited.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a novel Fin structure GaN HEMT device based on under-grid imaging and a preparation method thereof.
The technical problem to be solved by the invention is realized by the following technical scheme:
a novel Fin structure GaN HEMT device based on under-gate patterning, the device comprising: the epitaxial substrate, a source electrode region, a drain electrode region, a passivation layer, ohmic metal, a second barrier layer and a gate electrode; the epitaxial substrate comprises a substrate layer, a nucleating layer, a buffer layer and a first barrier layer from bottom to top; the first barrier layer is located over the buffer layer; the source electrode area and the drain electrode area are positioned on two sides of the buffer layer and the first barrier layer; the ohmic metal is positioned above the source electrode region and the drain electrode region; the passivation layer covers the first barrier layer and the ohmic metal, and a preset gate groove area is arranged in the middle of the passivation layer; the depth of the preset gate groove area is equal to or greater than the depth of the passivation layer; the first barrier layer comprises a preset array groove region; the second barrier layer covers the preset array groove area; the second barrier layer is covered with a gate electrode.
The invention has the beneficial effects that:
according to the invention, a layer of barrier layer material can be further grown on the traditional fin structure, and the etching shape under the gate is changed, so that the high-performance GaN HEMT device with high current and power output capability is obtained. In the device, the actual current conduction area is the original channel area plus the two-dimensional electron gas conduction area generated by the side wall due to the heterojunction, the gate width can be greatly increased, the output current density and the power additional efficiency are greatly improved, and therefore a high-power device is realized; meanwhile, the side wall of the traditional Fin structure can be directly contacted with the grid metal, so that the current leakage of the grid is effectively isolated, namely, the electric leakage of the grid is reduced.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a novel GaN HEMT device with a Fin structure based on under-gate patterning according to an embodiment of the present invention
Fig. 2 is a front view of a cross-sectional structure of a novel GaN HEMT device of a Fin structure based on under-gate patterning according to an embodiment of the present invention;
fig. 3 is a side view of a cross-sectional structure of a novel Fin structure GaN HEMT device based on under-gate patterning according to an embodiment of the present invention;
fig. 4 is a schematic diagram of two-dimensional electron gas distribution in a period of one Fin in the gate width direction of a novel Fin structure GaN HEMT device based on under-gate patterning according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a method for manufacturing a novel GaN HEMT device with a Fin structure based on under-gate patterning according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of a manufacturing process of a novel Fin structure GaN HEMT device based on under-gate patterning according to an embodiment of the present invention.
The reference numbers illustrate:
the epitaxial substrate comprises an epitaxial substrate 1, a source electrode region 2, a drain electrode region 3, a passivation layer 4, ohmic metal 5, a second barrier layer 6, a gate electrode 7 and a metal interconnection open region 8; substrate layer 11, nucleation layer 12, buffer layer 13, first barrier layer 14.
Detailed Description
Aiming at the defect that the high-performance GaN-based HEMT is realized by the existing Fin structure, the invention provides a method for forming an array channel by covering a barrier layer on the traditional Fin structure by utilizing a regrowth technology, and the effective grid width of the GaN-based Fin HEMT is improved by changing the etching shape under the grid, the current circulation capacity is improved, and the application requirement of high frequency and high performance is met.
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a novel GaN HEMT device of a Fin structure based on under-gate patterning according to an embodiment of the present invention, where the device includes: the epitaxial substrate 1, a source electrode region 2, a drain electrode region 3, a passivation layer 4, ohmic metal 5, a second barrier layer 6 and a gate electrode 7;
the epitaxial substrate 1 comprises a substrate layer 11, a nucleation layer 12, a buffer layer 13 and a first barrier layer 14 from bottom to top;
the buffer layer is GaN. The materials of the substrate layer, the nucleation layer, the barrier layer and the passivation layer are not particularly limited. For example, the substrate is made of one of sapphire, SiC or Si, and the barrier layer is made of a strongly polarized material such as AlGaN, InAlN, AlN or ScAlN;
note that the first barrier layer is referred to as a conventional barrier layer, and the second barrier layer is referred to as a secondary epitaxial barrier layer.
The first barrier layer 14 is located above the buffer layer 13
The source electrode region 2 and the drain electrode region 3 are positioned on both sides of the buffer layer 13 and the first barrier layer 14;
the ohmic metal 5 is positioned above the source electrode region 2 and the drain electrode region 3;
the passivation layer 4 covers the first barrier layer 14 and the ohmic metal 5, and a preset gate groove region is arranged in the middle of the passivation layer 4; the depth of the preset gate groove area is equal to or greater than the depth of the passivation layer;
the first barrier layer 14 comprises a preset array groove region;
the second barrier layer 6 covers the preset array groove area;
the second barrier layer 6 is covered with a gate electrode 7.
Optionally, the metal interconnection opening region 8 and the metal interconnection layer may be further lithographically patterned based on the device of the present invention.
Optionally, a metal interconnect open region 8 is located on the source and drain electrode regions.
According to the invention, a source electrode and a drain electrode are arranged at two ends of a conventional barrier layer, metal interconnection layers are arranged on the source electrode and the drain electrode, a passivation layer covers the barrier layer, a grid electrode is arranged on one side, close to a source end, of the passivation layer, grid legs are arranged on the surface of the barrier layer subjected to secondary epitaxial growth, and Fin structures are arranged in the grid width direction under the grid legs according to a certain period, so that the Fin length, the Fin width, the Fin height and the etching proportion can be changed.
Referring to fig. 2, fig. 2 is a front view of a cross-sectional structure of a novel Fin structure GaN HEMT device based on under-gate patterning according to an embodiment of the present invention.
Referring to fig. 3, fig. 3 is a side view of a cross-sectional structure of a novel Fin structure GaN HEMT device based on under-gate patterning according to an embodiment of the present invention.
Referring to fig. 4, fig. 4 is a schematic diagram of two-dimensional electron gas distribution in a period of one Fin in the gate width direction of a novel Fin structure GaN HEMT device based on under-gate patterning according to an embodiment of the present invention.
In conclusion, the invention can grow a layer of barrier layer material (second barrier layer) on the traditional fin structure and change the etching shape under the gate so as to obtain the high-performance GaN HEMT device with high current and power output capability. In the device, the actual current conduction area is the original channel area plus the two-dimensional electron gas (2DEG) conduction area of the side wall generated due to heterojunction, the gate width can be greatly increased, the output current density and the power additional efficiency are greatly improved, and therefore a high-power device is realized; meanwhile, the side wall of the traditional Fin structure can be directly contacted with the grid metal, so that the current leakage of the grid is effectively isolated, namely, the electric leakage of the grid is reduced. In addition, the invention can adjust the peak transconductance and the gate voltage swing amplitude of the device by optimizing the fin length, the fin width, the fin height and the etching proportion in the gate width direction and upgrading the fin-shaped structure, and is used for different linearity requirements.
Example two
Referring to fig. 5, fig. 5 is a schematic view of a method for manufacturing a novel GaN HEMT device with a Fin structure based on under-gate patterning according to an embodiment of the present invention, where the method includes:
step 1: and sequentially growing a nucleation layer, a buffer layer and a first barrier layer based on the substrate layer to obtain the epitaxial substrate.
Fig. 6A is a schematic view of an epitaxial substrate.
Step 2: and photoetching both sides of the buffer layer and the first barrier layer to obtain a source electrode area and a drain electrode area, and depositing ohmic metal above the source electrode area and the drain electrode area.
Optionally, step 2 includes:
2a) source and drain electrode regions are lithographically patterned on the first barrier layer:
firstly, placing an epitaxial substrate on a hot plate at 200 ℃ for pre-baking for 5 min;
then, coating stripping glue (PMGI SF6) on the AlGaN barrier layer, rotating speed of a whirl coating table is 2000rad/min, whirl coating time is 40sec, whirl coating thickness is 0.35 mu m, and then placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, photoresist (EPI621) is coated on the stripping glue, the rotating speed of a spin coating table is 5000rad/min, the spin coating time is 30sec, the spin coating thickness is 0.77 mu m, and then the sample is placed on a hot plate at the temperature of 90 ℃ to be baked for 1 min;
then, the sample which is coated with glue and spun with glue is placed into a photoetching machine to expose the coated surface for 230ms, and the exposed sample is placed on a hot plate at 110 ℃ to be baked for 1 min;
finally, the substrate is placed into a developing solution (EPD1000) to remove photoresist and stripping glue for 45sec, and then ultra-pure water washing and nitrogen blow-drying are carried out on the substrate to obtain a defined source electrode area and a defined drain electrode area;
2b) evaporating ohmic metal on the AlGaN barrier layer in the source electrode area and the drain electrode area and on the photoresist outside the source electrode area and the drain electrode area to form a source electrode and a drain electrode:
firstly, putting a sample with a photoetching pattern of a source electrode and a drain electrode into a plasma photoresist remover for carrying out basement membrane treatment, wherein the power is 200W, the O2 is 100sccm, and the treatment time is 5 min;
then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6Evaporating ohmic metal on the AlGaN barrier layers in the source electrode area and the drain electrode area and on the photoresist outside the source electrode area and the drain electrode area after Torr to form a source electrode and a drain electrode, wherein the ohmic metal is sequentially from bottom to top
Finally, stripping the sample subjected to ohmic metal evaporation to remove ohmic metal, photoresist and stripping glue outside the source electrode and the drain electrode, flushing the sample with ultrapure water and drying the sample with nitrogen;
2c) putting a sample which finishes ohmic metal evaporation and stripping into a rapid thermal annealing furnace for annealing treatment so as to enable ohmic metal on the AlGaN barrier layer in the source electrode and the drain electrode to sink to the GaN buffer layer, thereby forming ohmic contact between the ohmic metal and the heterojunction channel, wherein the annealing process conditions are as follows: the annealing atmosphere was N2, the annealing temperature was 840 ℃ and the annealing time was 60 s.
As shown in fig. 6B, a source-drain pattern is etched on the first barrier layer and ohmic metal is deposited, followed by thermal annealing, and the ohmic metal used is Ti/Al/Ni/Au in this order.
After the step 2, the method further comprises:
an active electrical isolation region is lithographically formed on the first barrier layer.
Optionally, the lithographically forming an active electrical isolation region on the first barrier layer includes:
photoetching an electric isolation area on the AlGaN barrier layer:
firstly, placing a sample on a hot plate at 200 ℃ for pre-baking for 5 min;
then, coating stripping glue (PMGI SF6) on the AlGaN barrier layer, wherein the rotating speed of a whirl coating table is 5000rad/min, the whirl coating time is 30sec, and then placing a sample on a hot plate at 180 ℃ for baking for 8 min;
then, coating photoresist (AZ6130) on the stripping glue, rotating at a whirl coating table at a speed of 1500rad/min for 50sec, and baking the sample on a hot plate at 100 ℃ for 2 min;
then, the sample is placed into a photoetching machine to expose the photoresist in the electric isolation region for 230ms, the exposed sample is placed into a developing solution (EPD1000) to remove the photoresist and the stripping resist in the electric isolation region, the developing time is 180sec, and the sample is washed by ultrapure water and dried by nitrogen;
finally, the electrically isolated regions were etched and the film was hardened, and the samples were baked on a hot plate at 100 ℃ for 1 min.
Etching an electrically isolated region on the AlGaN barrier layer:
firstly, etching an AlGaN barrier layer and a GaN buffer layer in an electrical isolation region in sequence by utilizing an ICP (inductively coupled plasma) process to realize the mesa isolation of an active region, wherein the total etching depth is 100 nm;
and finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an isopropanol solution for cleaning to remove the photoresist outside the electric isolation region, then flushing the sample with ultrapure water and drying with nitrogen.
And step 3: growing a passivation layer over the first barrier layer and the ohmic metal.
Optionally, the step 3 includes:
3a) and (3) performing surface cleaning on the sample subjected to active area electrical isolation:
firstly, putting a sample into an acetone solution for ultrasonic cleaning for 5mim, wherein the ultrasonic intensity is 2.2;
then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 15 min;
then, putting the sample into an acetone solution and an isopropanol solution in sequence, and ultrasonically cleaning for 3min, wherein the ultrasonic intensity is 2.2;
finally, washing the sample with ultrapure water and drying the sample with nitrogen;
3b) on the AlGaN barrier layers of the source electrode, the drain electrode and the active area, a SiN passivation layer with the thickness of 120nm is grown by a PECVD process, and the growth process conditions are as follows: SiN (2% SiH)4/N2)＝200sccm，NH3＝2sccm，N2The deposition time is 25min at 250 deg.C, 22W, 200sccm, 600mT, 200sccm, and 600 mT.
Referring to FIG. 6C, a passivation layer is deposited with a dielectric of SiN and a thickness of 120nm (or 60nm or 20nm) by Plasma Enhanced Chemical Vapor Deposition (PECVD) of a silicon nitride (SiN) layer, wherein SiN (2% SiH)4/N2)＝200sccm，NH3＝2sccm，N2The deposition time is 25min at 250 deg.C and 22W, with He of 200sccm and pressure of 600 mT.
And 4, step 4: and etching the middle of the passivation layer to obtain a preset gate groove area, wherein the depth of the preset gate groove area is equal to or greater than the depth of the passivation layer.
As shown in fig. 6D, the etching method is: etching the SiN layer with Inductively Coupled Plasma (ICP) F-based on the gate pin mask to expose the gate pin window region, wherein CF4＝60sccm，O2The pressure is 1Pa, the upper electrode power is 100W, and the lower electrode power is 25W, 2 sccm. The etch depth is equal to or slightly greater than the SiN layer thickness.
Optionally, the step 4 includes:
4a) etching a gate trench region on the SiN passivation layer:
firstly, placing a sample on a hot plate at 200 ℃ for pre-baking for 5 min;
then, coating and spin coating the electron beam photoresist at a spin coating speed of 3500rad/mim, a spin coating time of 40sec and a glue layer thickness of 450nm, and baking the sample on a hot plate at 150 ℃ for 1 min;
then, putting the sample into an electron beam lithography machine to expose the photoresist in the gate groove area;
finally, putting the exposed sample into a developing solution to remove the photoresist in the grid groove area, and drying the photoresist by nitrogen;
4b) and removing the SiN passivation layer in the gate groove region by utilizing an ICP (inductively coupled plasma) etching process, wherein the etching conditions are as follows: CF (compact flash)4＝60sccm，O2Pressure of 2sccm, top electrode power of 100W, and bottom electrode power of 25W. The etch depth is equal to or slightly greater than the SiN layer thickness.
And 5: and etching the first barrier layer to obtain a preset array groove region so as to obtain a fin structure.
The shape of the preset array groove region is selected by a person skilled in the art according to business needs, and the invention is not limited. For example, a symmetrical Fin structure is realized by adopting a diamond shape or other symmetrical polygons, and an asymmetrical Fin structure can be formed by adopting a trapezoid shape, a triangle shape and the like, so that the electric field distribution under a gate can be changed, the channel carrier mobility can be regulated and controlled, the on-resistance and knee voltage can be further controlled, and the high-performance GaN-based HEMT device under different application ranges can be realized.
Optionally, step 5 includes:
5a) and photoetching is carried out on the first barrier layer to obtain the shape of the preset array groove.
Firstly, placing a sample on a hot plate at 200 ℃ for pre-baking for 5 min;
then, coating and whirl coating the electron beam photoresist at a whirl coating rotation speed of 3500rad/mim for 40sec with a glue layer thickness of 450nm, and baking the sample on a hot plate at 150 ℃ for 1 min;
then, putting the sample into an electron beam lithography machine to expose the photoresist in the groove area;
and finally, putting the exposed sample into a developing solution to remove the photoresist in the groove area, and carrying out nitrogen blow drying on the photoresist.
5b) And etching the first barrier layer according to the shape of the preset array groove so as to etch the first barrier layer to obtain a preset array groove region.
Removing the AlGaN barrier layer in the groove region by utilizing an ICP (inductively coupled plasma) etching process, wherein the etching conditions are as follows: wherein Cl is2＝25sccm，BCl3The pressure is 1Pa, the power of the upper electrode is 150W, the power of the lower electrode is 15W, and the etching depth is slightly larger than or equal to the thickness of the barrier layer, namely 10 nm-15 nm.
As shown in fig. 6E, a Fin mask is formed at the groove, and then the barrier layer with a certain thickness is etched to ensure that the barrier layer is etched through, so as to form a Fin groove with a rectangular shape and periodically arranged. The etching method comprises the following steps: etching the AlGaN layer using Inductively Coupled Plasma (ICP) Cl radicals to expose the Fin region (portion after etching), wherein Cl2＝25sccm，BCl3The pressure is 1Pa, the upper electrode power is 150W, and the lower electrode power is 15W, at 5 sccm.
And 6: and growing a second barrier layer on the preset array groove region.
A new Fin structure can be fabricated by step 6, forming a new heterojunction at the sidewall and the groove.
Optionally, the step 6 includes:
growing a second barrier layer on the groove region of the preset array by a molecular beam epitaxy technology; the second barrier layer covers the preset array groove area, and the shape of the second barrier layer corresponds to the shape of the preset array groove.
6a) And (3) regrowing barrier layer materials on the Fin structure by utilizing molecular beam epitaxy:
firstly, raising the degassing temperature of the cavity to 600-610 ℃;
then, the substrate temperature is raised to 590-600 ℃;
then, setting the growth time to 1280sec, and estimating the thickness to be 100 nm;
6b) the annealing treatment makes the material evenly distributed:
firstly, setting the annealing temperature at 600-610 ℃ and the annealing time at 5 min; wherein the Ga source temperature is 1040 ℃, and the Si source temperature is 1270 ℃.
As shown in fig. 6F, a layer of barrier layer material, i.e., a second barrier layer, is further grown on the Fin structure by using a molecular beam epitaxy technique. The process conditions are as follows: the degassing temperature is 600 ℃ and 610 ℃; the substrate temperature is 590-600 ℃; the growth time is 1280sec, and is estimated to be 100 nm; annealing temperature: 600 ℃ and 610 ℃; annealing time: 5 min; ga source temperature: 1040 ℃; si source temperature: 1270 ℃.
And 7: and photoetching a gate electrode on the second barrier layer.
Optionally, step 7 includes:
firstly, placing a sample on a hot plate at 200 ℃ for pre-baking for 5 min;
then, coating a stripping glue (PMGI SF6) on the SiN passivation layer, wherein the rotating speed of a whirl coating table is 2000rad/min, the whirl coating time is 40sec, the whirl coating thickness is 0.35 mu m, and then placing a sample on a hot plate at 200 ℃ for baking for 5 min;
then, photoresist (EPI621) is coated on the stripping glue, the rotating speed of a spin coating table is 5000rad/min, the spin coating time is 30sec, the spin coating thickness is 0.77 mu m, and then the sample is placed on a hot plate at the temperature of 90 ℃ to be baked for 1 min;
then, putting the sample which is subjected to glue coating and spin coating into a photoetching machine to expose the surface subjected to glue coating for 280ms, and baking the exposed sample on a hot plate at 110 ℃ for 1 min;
finally, the photoresist and the stripping resist are removed in a developing solution (EPD1000), the developing time is 60sec, and then ultra-pure water washing and nitrogen blow-drying are carried out on the photoresist and the stripping resist, so as to obtain a defined source electrode area and a defined drain electrode area;
7b) evaporating the gate electrode on the AlGaN barrier layer within the gate electrode region and on the photoresist outside the gate electrode region:
firstly, a sample with a gate electrode photoetching pattern is put into a plasma photoresist remover to be processed by a bottom film with the power of 200W and O2Processing time is 5min when the sccm is 100 sccm;
then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6Evaporating gate metal on the AlGaN barrier layer in the gate electrode area and the photoresist outside the gate electrode area after Torr, wherein the gate metal sequentially consists of
And finally, stripping the sample subjected to gate metal evaporation to remove the gate metal, the photoresist and the stripping glue outside the gate electrode area, flushing the sample with ultrapure water and drying the sample with nitrogen to form the gate electrode.
As shown in fig. 6G and 6H, a gate mask is made, gate metal is deposited by electron beam evaporation, and a T-shaped gate electrode is formed by lift-off to prepare the device of the present invention.
It should be noted that, in the present invention, the gate electrode is preferably located close to the source electrode region. The gate electrode can be an I-shaped gate, a T-shaped gate, a floating gate and the like, and the application requirement of high frequency and high performance is met.
Optionally, the gate electrode corresponds to a topography of the second barrier layer.
Optionally, after step 7, the method further includes:
and photoetching metal interconnection open regions on the source electrode region and the drain electrode region, wherein the metal interconnection open regions are positioned in the passivation layer. Wherein the metal interconnect open region is located on the source and drain electrode regions.
And photoetching a metal interconnection layer among the metal interconnection opening region, the source electrode region, the drain electrode region and the passivation layer.
It should be noted that the process parameters in fig. 6 and the steps are only preferred examples of the present invention, and the values can be set by those skilled in the art according to the business needs.
In conclusion, the invention has the beneficial effects that:
1. the invention can etch a certain depth of the barrier layer in a specific area along the width direction of the gate, for example, by utilizing an inductively coupled plasma etching technology (ICP). Therefore, the two-dimensional electron gas in the etching area can be guaranteed to be damaged and penetrate through the barrier layer immediately, the control capability of the unetched area on the channel is reserved, a Fin structure is formed, and the control effect of three-side ring grid lifting on the current is achieved;
2. the invention can utilize regrowth technology, such as a Molecular Beam Epitaxy (MBE) method, to epitaxially grow a layer of single crystal film on the barrier layer reserved in the non-etched region and the buffer layer exposed by etching on the existing Fin structure, and the material selection of the film is consistent with that of the barrier layer, thereby obtaining the novel Fin structure provided by the invention and realizing the high-frequency high-performance GaN-based HEMT.
3. The invention can fix three variable parameters by setting the gate length, the gate width and the source-drain spacing of the device to be constant through a control variable method, thereby obtaining the relation between the fourth parameter and the transconductance characteristic. Namely, as the fin length is reduced, the peak transconductance is increased, and the gate voltage swing is slightly increased; when the fin length is equal to the gate length, the peak transconductance greatly rises along with the reduction of the fin width, but the gate voltage swing is obviously reduced, and when the fin length is longer than the gate length, the influence of the fin width on the transconductance characteristic is weakened; as the fin height increases, the threshold voltage is shifted positive, the peak transconductance increases but the transconductance linearity weakens; changing the Fin structure period is also one of changing the etching proportion, the invention has obvious influence on transconductance characteristics, and the invention further researches a transconductance curve by fixing the Fin structure period and adjusting the proportion of etched and unetched regions in the period.
4. The invention realizes a symmetrical Fin structure by changing the shape of an etching area under a grid, such as a rectangle, a rhombus and the like, and forms an asymmetrical Fin structure such as a trapezoid, a triangle and the like, the width of the middle of a groove is larger than that of two sides, the middle of the Fin structure is narrow, two sides of the Fin structure are wide, the electric field distribution of a channel area from a drain to a source is shown to be converged and then diverged, so that the electric field is converged under the grid, a transverse electric field is effectively improved, the speed of a channel carrier is quickly saturated, knee voltage is effectively reduced, the device can work under low voltage, and meanwhile, the device has high linearity.
5. An arrayed channel structure is employed in the present invention. According to the structure, a layer of barrier layer material (a second barrier layer) is epitaxially grown for the second time, the actual current conduction area is the two-dimensional electron gas conduction area generated by the whole channel area and the side wall due to the heterojunction, and the output current density and the power additional efficiency are greatly increased. Meanwhile, the side walls of the gate metal and the Fin structure are isolated due to the deposition of the barrier layer material, so that an electron transport channel is prevented from being formed, and the electric leakage of the gate is effectively reduced.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. A novel Fin structure GaN HEMT device based on under-grid imaging is characterized by comprising:
the epitaxial substrate, a source electrode region, a drain electrode region, a passivation layer, ohmic metal, a second barrier layer and a gate electrode;
the epitaxial substrate comprises a substrate layer, a nucleating layer, a buffer layer and a first barrier layer from bottom to top;
the first barrier layer is positioned above the buffer layer;
the source electrode area and the drain electrode area are positioned on two sides of the buffer layer and the first barrier layer;
the ohmic metal is positioned above the source electrode region and the drain electrode region;
the passivation layer covers the first barrier layer and the ohmic metal, and a preset gate groove area is arranged in the middle of the passivation layer; the depth of the preset gate groove area is equal to or greater than the depth of the passivation layer;
the first barrier layer comprises a preset array groove region;
the second barrier layer covers the preset array groove area;
the second barrier layer is covered with a gate electrode.
2. A preparation method of a novel Fin structure GaN HEMT device based on under-grid imaging is characterized by comprising the following steps:
step 1: sequentially growing a nucleation layer, a buffer layer and a first barrier layer based on the substrate layer to obtain an epitaxial substrate;
step 2: photoetching both sides of the buffer layer and the first barrier layer to obtain a source electrode area and a drain electrode area, and depositing ohmic metal above the source electrode area and the drain electrode area;
and step 3: growing a passivation layer over the first barrier layer and the ohmic metal;
and 4, step 4: etching the middle of the passivation layer to obtain a preset gate groove area, wherein the depth of the preset gate groove area is equal to or greater than the depth of the passivation layer;
and 5: etching the first barrier layer to obtain a preset array groove region so as to obtain a fin structure;
step 6: growing a second barrier layer on the preset array groove region;
and 7: and photoetching a gate electrode on the second barrier layer.
3. The method of claim 2, wherein after step 7, the method further comprises:
photoetching metal interconnection open hole regions on the source electrode region and the drain electrode region, wherein the metal interconnection open hole regions are positioned in the passivation layer;
and photoetching a metal interconnection layer among the metal interconnection opening region, the source electrode region, the drain electrode region and the passivation layer.
4. The method of claim 2, wherein after step 2, the method further comprises:
an active electrical isolation region is lithographically formed on the first barrier layer.
5. The method of claim 2, wherein the step 5 comprises:
photoetching is carried out on the first barrier layer to obtain the shape of the preset array groove;
and etching the first barrier layer according to the shape of the preset array groove so as to etch the first barrier layer to obtain a preset array groove region.
6. The method of claim 2, wherein the step 6 comprises:
growing a second barrier layer on the groove region of the preset array by a molecular beam epitaxy technology; the second barrier layer covers the preset array groove area, and the shape of the second barrier layer corresponds to the shape of the preset array groove.
7. The method of claim 2, wherein the gate electrode corresponds to a topography of the second barrier layer.
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