CN113314416B - Preparation method of upper dip angle structure of GaN-HEMT device - Google Patents
Preparation method of upper dip angle structure of GaN-HEMT device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 104
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 84
- 229920005591 polysilicon Polymers 0.000 claims abstract description 77
- 238000005530 etching Methods 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 52
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 52
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 52
- 230000003647 oxidation Effects 0.000 claims abstract description 31
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 31
- 230000001590 oxidative effect Effects 0.000 claims abstract description 22
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims description 47
- 230000004888 barrier function Effects 0.000 claims description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 229910002704 AlGaN Inorganic materials 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 abstract description 23
- 238000009776 industrial production Methods 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 214
- 229910002601 GaN Inorganic materials 0.000 description 20
- 230000005684 electric field Effects 0.000 description 11
- 230000001276 controlling effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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Abstract
The invention provides a preparation method of an upper dip angle structure of a GaN-HEMT device, which comprises the following steps: sequentially growing a first SiN layer, a polycrystalline silicon layer, a silicon dioxide layer and a second SiN layer on the surface of a wafer with a GaN-HEMT epitaxial structure; photoetching an opening, and then sequentially etching the second SiN layer, the silicon dioxide layer and the polysilicon layer to form a deep trench so that the side wall of the polysilicon layer is exposed; oxidizing the GaN-HEMT after photoetching the opening to form an inclined angle structure on the polysilicon layer; etching to remove the second SiN layer and the silicon dioxide layer; etching the polysilicon layer and the first SiN layer to transfer the inclination angle structure morphology of the polysilicon layer to the first SiN layer. According to the invention, the inclination angle structure is formed by adopting the method for forming silicon dioxide by oxidizing polysilicon, the inclination angle structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated.
Description
Technical Field
The invention belongs to the technical field of semiconductors, relates to a preparation method of an inclination structure, and particularly relates to a preparation method of an upper inclination structure of a GaN-HEMT device.
Background
GaN is a novel semiconductor material for developing microelectronic devices and optoelectronic devices, has the characteristics of wide direct band gap, strong atomic bonds, high heat conductivity, good chemical stability and the like, and strong irradiation resistance, and has wide prospect in the application fields of photoelectrons, high-temperature high-power devices and high-frequency microwave devices.
GaN/AlGaN heterostructures are currently the most attractive device structures because of the extremely strong spontaneous and piezoelectric polarization effects between GaN and AlGaN, resulting in the formation of a two-dimensional electron gas (2-DEG) between GaN/AlGaN with high electron concentration and high electron mobility, with electron concentrations as high as 10 12 -10 13 cm -2 The electron mobility can reach 2000cm 2 V; this makes GaN/AlGaN High Electron Mobility Transistors (HEMTs) the most important device type in the field of gallium nitride devices.
In order to further improve the performance of the device, gaN HEMT devices with different structures are continuously proposed. In the radio frequency field, through etching AlGaN barrier layers at the inclination angles in the gate length direction, groove gate structures with different depths in the gate length direction are manufactured, and the structure can greatly improve the gain effect and linearity of the device. The GaN HEMT has a field plate structure with a certain inclination angle in the field of power electronic devices, can replace the traditional multi-field plate structure, and better reduces the electric field intensity at the grid electrode when the device works reversely.
CN 108417628A discloses a GaN HEMT device and a preparation method, the GaN HEMT device comprises a substrate, a GaN epitaxial layer and a gate dielectric layer are sequentially arranged on the upper surface of the substrate from bottom to top, and a gate electrode, a source electrode and a drain electrode which penetrate through the gate dielectric layer and are in contact with the GaN epitaxial layer; the gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer with different properties; a first gate groove is formed in the first gate dielectric layer, and a second gate groove is formed in the second gate dielectric layer; the first gate trench sidewall tilt angle is less than the second gate trench sidewall tilt angle. The structure ensures that the inclination angle of the side wall of the first gate groove is gentle, the inclination angle of the side wall of the second gate groove is steep, the holes formed by the gate metal barrier layer are reduced, and meanwhile, the parasitic capacitance is reduced. However, the method for forming the first gate groove and the second gate groove is a photoetching method, the exposure of different areas needs to be controlled, the requirements on the processing precision of the photoetching process are extremely high, the repeatability of the process is poor, and large-scale industrial application is difficult to realize.
CN 107634009a discloses a GaM MOS-HEMT device and a preparation method thereof, the method is: depositing a silicon nitride dielectric layer on the GaN epitaxial wafer to protect the surface of the material; etching to form a grid window; depositing a polysilicon layer on the surface of the silicon nitride dielectric layer and in the gate window; oxidizing the polysilicon layer to SiO 2 A gate dielectric layer; etching to form an ohmic contact hole; depositing ohmic metal and forming a source electrode and a drain electrode; depositing gate electrode metal and forming a gate electrode; the surface protects and opens the electrode window. Wherein the gate dielectric layer adopts SiO 2 The thin film has good compactness and less trap charge, can reduce gate leakage current of the GaN device, can enable the GaN device to have good dynamic characteristics, and can remarkably improve performance and stability of the device. But this method cannot be used to produce field plate structures with angled structures.
The process for preparing the dip angle structure in the prior art is complex, and industrial production with good repeatability cannot be performed under the condition of the existing process precision. Therefore, there is a need to provide a method for manufacturing a tilt gate structure with controllable precision and good repeatability.
Disclosure of Invention
The invention aims to provide a preparation method of an upper dip angle structure of a GaN-HEMT device, which can accurately regulate and control the dip angle morphology by regulating and controlling oxidation conditions and is convenient for industrial production of the GaN-HEMT device with the dip angle structure.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
the invention provides a preparation method of an upper dip angle structure of a GaN-HEMT device, which comprises the following steps:
(1) Sequentially growing a first SiN layer, a polysilicon layer, a silicon dioxide layer and a second SiN layer on the surface of the GaN-HEMT epitaxial structure wafer;
(2) Etching the second SiN layer, the silicon dioxide layer and the polysilicon layer in sequence to form a deep trench so that the side wall of the polysilicon layer is exposed;
(3) Oxidizing the GaN-HEMT after photoetching the opening to form an inclined angle structure on the polysilicon layer;
(4) Etching to remove the second SiN layer and the silicon dioxide layer;
(5) Etching the polysilicon layer and the first SiN layer to transfer the inclination angle structure morphology of the polysilicon layer to the first SiN layer.
The method comprises the steps of sequentially arranging a first SiN layer, a polysilicon layer, a silicon dioxide layer and a second SiN surface layer on the surface of a wafer with a GaN-HEMT epitaxial structure, wherein the first SiN is used as an oxidation barrier layer to prevent the GaN-HEMT epitaxial structure from being oxidized during oxidation treatment; the polysilicon layer is oxidized during the oxidation treatment; the thickness and compactness of the silicon dioxide layer influence the angle of the oxidized back inclination angle, and a person skilled in the art can set the thickness and compactness of the silicon dioxide layer reasonably according to the needs.
And (3) etching the polysilicon layer in the step (2) to a certain depth or until the first SiN layer is exposed according to the requirement. When etching to a certain depth, the polysilicon remaining at the bottom is completely oxidized to silicon dioxide in the oxidation treatment, and then removed in the etching treatment in step (5). Preferably, the method of growing the first SiN, the polysilicon layer, the silicon dioxide layer and the second SiN layer in the step (1) includes any one or a combination of at least two of chemical vapor deposition, atomic layer deposition, sputtering or oxidation growth.
The parameters of chemical vapor deposition, atomic layer deposition, sputtering and oxidation growth can be reasonably selected by a person skilled in the art according to the needs, and the invention is not limited herein.
Preferably, the etching in step (2) is: and after the photoresist mask is used, sequentially etching the second SiN layer, the silicon dioxide layer and the polysilicon layer by dry etching, and then removing the photoresist mask.
Preferably, the oxidation treatment of step (3) comprises dry oxygen oxidation and/or wet oxygen oxidation.
According to the invention, the partial oxidation of the polysilicon layer is realized through the oxidation treatment in the step (3), so that the polysilicon layer presents an inclination angle structure, and the conditions of dry oxygen oxidation and wet oxygen oxidation can be adjusted according to the morphology of the required inclination angle structure.
The temperature of the oxidation treatment in step (3) is 700 to 1200 ℃, and may be 700 ℃, 800 ℃, 850 ℃, 900 ℃, 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, 1150 ℃ or 1200 ℃, for example, but is not limited to the recited values, and other values not recited in the numerical range are equally applicable.
Preferably, the method of etching removal in step (4) comprises wet etching and/or dry etching.
The wet etching and dry etching methods of the present invention are conventional methods in the art, as long as the removal of the first SiN layer and the silicon dioxide layer can be achieved, and the present invention is not limited herein.
Preferably, the method of the etching treatment in the step (5) includes dry etching.
In the dry etching process, the polysilicon layer and the first SiN layer are etched at the same time, the dry etching is carried out to an end point, and the inclination angle structure morphology of the polysilicon layer is transferred to the first SiN layer.
The dry etching method of the present invention is a conventional dry etching method in the art, as long as simultaneous etching of the polysilicon layer and the first SiN layer can be achieved, and the present invention is not limited herein.
Preferably, the wafer with the GaN-HEMT epitaxial structure in the step (1) includes a substrate, a GaN epitaxial layer and a barrier layer which are stacked.
The material of the barrier layer includes any one or a combination of at least two of AlGaN, inGaN, or InAlGaN, and typical but non-limiting combinations include combinations of AlGaN and InGaN, combinations of InGaN and InAlGaN, combinations of AlGaN and InAlGaN, or combinations of AlGaN, inGaN, and InAlGaN.
Preferably, the preparation method further comprises a step (6) after the step (5): and etching the barrier layer and the first SiN layer with the dip angle structure to prepare the dip angle gate structure.
Preferably, the method of the etching treatment in the step (6) includes dry etching.
And (6) etching the barrier layer and the first SiN layer with the dip angle structure at the same time by the etching treatment, so as to realize the transfer of the dip angle structure to the AlGaN layer. The dry etching method used in the step (6) is a conventional etching method in the art, so long as the simultaneous etching of the AlGaN layer and the SiN layer can be realized, and the present invention is not particularly limited herein.
Preferably, the wafer with the GaN-HEMT epitaxial structure in the step (1) includes a substrate, a GaN epitaxial layer and an AlGaN epitaxial layer which are stacked.
Preferably, the preparation method further comprises a step (6) after the step (5): and etching the barrier layer and the first SiN layer with the dip angle structure to prepare the dip angle gate structure.
Preferably, the etching method in step (6) comprises dry etching.
According to the invention, the etching treatment in the step (5) enables the first SiN layer to form an inclination angle structure, and the dry etching scheme for controlling the etching selection ratio of the first SiN layer to the barrier layer is adopted through the dry etching in the step (6), so that the inclination angle structure of the first SiN layer is transferred to the barrier layer, and the preparation of the inclination angle gate structure is realized.
As a preferable technical scheme of the preparation method, the preparation method comprises the following steps:
(1) Sequentially growing a first SiN layer, a polycrystalline silicon layer, a silicon dioxide layer and a second SiN layer on the surface of a wafer with a GaN-HEMT epitaxial structure;
(2) Etching the second SiN layer, the silicon dioxide layer and the polysilicon layer in sequence to form a deep trench so that the side wall of the polysilicon layer is exposed; the etching is to use photoresist as a mask, sequentially etch the second SiN layer, the silicon dioxide layer and the polysilicon layer by dry etching, and then remove the photoresist mask;
(3) Oxidizing the GaN-HEMT after photoetching the opening to form an inclined angle structure on the polysilicon layer;
(4) Etching to remove the second SiN layer and the silicon dioxide layer; the etching removal method comprises wet etching and/or dry etching;
(5) Dry etching is carried out on the polysilicon layer and the first SiN layer to transfer the inclination angle structure morphology of the polysilicon layer to the first SiN layer;
(6) And dry etching the barrier layer and the first SiN layer with the dip angle structure to prepare the dip angle gate structure.
Compared with the prior art, the invention has the following beneficial effects:
(1) According to the invention, the inclination structure is formed by adopting a method for forming silicon dioxide by oxidizing polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, so that the precise control is easier to realize, and the industrial production is facilitated;
(2) The GaN-HEMT device with the dip angle structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
Drawings
FIG. 1 is a schematic diagram of a structure obtained by sequentially growing a first SiN layer, a polysilicon layer, a silicon dioxide layer and a second SiN layer;
FIG. 2 is a schematic diagram of the resulting structure after etching the polysilicon layer to expose the first SiN layer;
FIG. 3 is a schematic illustration of the resulting structure of the GaN-HEMT after the oxidation treatment of the lithographic opening;
FIG. 4 is a schematic diagram of the resulting structure after removal of the second SiN layer and the silicon dioxide layer;
FIG. 5 is a schematic diagram of the resulting structure after transferring the tilt angle morphology of the polysilicon layer to the first SiN layer;
FIG. 6 is a schematic diagram of the resulting structure after etching the barrier layer and SiN layer;
fig. 7 is a schematic diagram of the resulting structure after etching the polysilicon layer until the first SiN layer is not exposed.
Wherein: 1, a substrate; 2, gaN epitaxial layer; 3, a barrier layer; 4, a first SiN layer; 5, a polysilicon layer; 6, a silicon dioxide layer; 7, a second SiN layer.
Detailed Description
The technical scheme of the invention is further described by the following specific embodiments. It will be apparent to those skilled in the art that the examples are merely to aid in understanding the invention and are not to be construed as a specific limitation thereof.
Example 1
The embodiment provides a preparation method of an upper dip angle structure of a GaN-HEMT device, which comprises the following steps:
(1) Sequentially performing chemical vapor deposition on a first SiN layer 4, a polycrystalline silicon layer 5, a silicon dioxide layer 6 and a second SiN layer 7 on the surface of a GaN-HEMT epitaxial structure wafer to obtain a structure shown in figure 1;
(2) Etching the second SiN layer 7, the silicon dioxide layer 6 and the polysilicon layer 5 in sequence by dry etching after using a photoresist mask to form a deep trench, wherein the etching end point is to expose the first SiN layer 4, and then removing the photoresist mask to obtain the structure shown in figure 2;
(3) Dry-oxygen oxidizing the GaN-HEMT after the photoetching opening, and oxidizing the polysilicon layer 5 to form an inclined angle structure to obtain a structure shown in figure 3;
(4) Wet etching to remove the second SiN layer 7 and the silicon dioxide layer 6 to obtain a structure shown in fig. 4;
(5) And (3) processing the polysilicon layer 5 and the first SiN layer 4 by dry etching, so that the shape of the inclination angle structure of the polysilicon layer 5 is transferred to the first SiN layer 4, and the inclination angle structure shown in fig. 5 is obtained.
The wafer with the GaN-HEMT epitaxial structure in the step (1) comprises a substrate 1, a GaN epitaxial layer 2 and a barrier layer 3 which are stacked.
The material of the barrier layer 3 is AlGaN.
According to the embodiment, the inclination structure is formed by adopting the method for forming silicon dioxide by oxidizing the polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated. The GaN-HEMT device with the inclination angle structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
Example 2
The embodiment provides a preparation method of an upper dip angle structure of a GaN-HEMT device, which comprises the following steps:
(1) Sequentially depositing a first SiN layer 4, a polycrystalline silicon layer 5, a silicon dioxide layer 6 and a second SiN layer 7 on the surface of a GaN-HEMT epitaxial structure wafer in an atomic layer manner to obtain a structure shown in figure 1;
(2) Etching the second SiN layer 7, the silicon dioxide layer 6 and the polysilicon layer 5 in sequence by dry etching after using a photoresist mask to form a deep trench, wherein the etching end point is to expose the first SiN layer 4, and then removing the photoresist mask to obtain the structure shown in figure 2;
(3) Wet oxygen oxidizes the GaN-HEMT after photoetching the opening, so that the polysilicon layer 5 is oxidized to form an inclined angle structure, and the structure shown in figure 3 is obtained;
(4) Removing the second SiN layer 7 and the silicon dioxide layer 6 by dry etching to obtain a structure shown in figure 4;
(5) And (3) processing the polysilicon layer 5 and the first SiN layer 4 by dry etching, so that the shape of the inclination angle structure of the polysilicon layer 5 is transferred to the first SiN layer 4, and the inclination angle structure shown in fig. 5 is obtained.
The wafer with the GaN-HEMT epitaxial structure in the step (1) comprises a substrate 1, a GaN epitaxial layer 2 and a barrier layer 3 which are stacked.
The material of the barrier layer 3 is InGaN.
According to the embodiment, the inclination structure is formed by adopting the method for forming silicon dioxide by oxidizing the polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated. The GaN-HEMT device with the inclination angle structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
Example 3
The embodiment provides a preparation method of an upper dip angle structure of a GaN-HEMT device, which comprises the following steps:
(1) Sputtering a first SiN layer 4, a polycrystalline silicon layer 5, a silicon dioxide layer 6 and a second SiN layer 7 on the surface of the GaN-HEMT epitaxial structure wafer in sequence to obtain a structure shown in figure 1;
(2) Etching the second SiN layer 7, the silicon dioxide layer 6 and the polysilicon layer 5 in sequence by dry etching after using a photoresist mask to form a deep trench, wherein the etching end point is to expose the first SiN layer 4, and then removing the photoresist mask to obtain the structure shown in figure 2;
(3) Dry-oxygen oxidizing the GaN-HEMT after the photoetching opening, and oxidizing the polysilicon layer 5 to form an inclined angle structure to obtain a structure shown in figure 3;
(4) Removing the second SiN layer 7 and the silicon dioxide layer 6 by dry etching to obtain a structure shown in figure 4;
(5) And (3) processing the polysilicon layer 5 and the first SiN layer 4 by dry etching, so that the shape of the inclination angle structure of the polysilicon layer 5 is transferred to the first SiN layer 4, and the inclination angle structure shown in fig. 5 is obtained.
The wafer with the GaN-HEMT epitaxial structure in the step (1) comprises a substrate 1, a GaN epitaxial layer 2 and a barrier layer 3 which are stacked.
The material of the barrier layer 3 is InAlGaN.
According to the embodiment, the inclination structure is formed by adopting the method for forming silicon dioxide by oxidizing the polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated. The GaN-HEMT device with the inclination angle structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
Example 4
The embodiment provides a preparation method of an upper dip angle structure of a GaN-HEMT device, which comprises the following steps:
(1) Sequentially oxidizing and growing a first SiN layer 4, a polycrystalline silicon layer 5, a silicon dioxide layer 6 and a second SiN layer 7 on the surface of the GaN-HEMT epitaxial structure wafer to obtain a structure shown in figure 7;
(2) Etching the second SiN layer 7, the silicon dioxide layer 6 and the polysilicon layer 5 in sequence through dry etching after using a photoresist mask to form a deep trench, wherein the etching end point is half of the thickness of the polysilicon layer 5, and then removing the photoresist mask;
(3) Dry-oxygen oxidation treatment is carried out on the GaN-HEMT after photoetching the opening, so that the polysilicon layer 5 is oxidized to form an inclination angle structure;
(4) Wet etching to remove the second SiN layer 7 and the silicon dioxide layer 6;
(5) The polysilicon layer 5 and the first SiN layer 4 are subjected to dry etching, so that the shape of the inclination angle structure of the polysilicon layer 5 is transferred to the first SiN layer 4, and the first SiN layer 4 with the inclination angle structure is obtained;
the wafer with the GaN-HEMT epitaxial structure in the step (1) comprises a substrate 1, a GaN epitaxial layer 2 and a barrier layer 3 which are stacked.
The material of the barrier layer 3 is AlGaN.
According to the embodiment, the inclination structure is formed by adopting the method for forming silicon dioxide by oxidizing the polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated. The GaN-HEMT device with the inclination angle structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
Example 5
The embodiment provides a preparation method of an upper dip angle structure of a GaN-HEMT device, and the preparation method further comprises the following step (6) after the step (5) on the basis of the preparation method provided by the embodiment 1: the preparation of the inclined gate structure shown in fig. 6 is achieved by dry etching the barrier layer 3 and the first SiN layer 4 having the inclined structure.
In this embodiment, through the dry etching in step (6), a dry etching scheme for controlling the etching selection ratio of the first SiN layer 4 to the barrier layer 3 is adopted to transfer the tilt angle structure of the first SiN layer 4 to the barrier layer 3, thereby realizing the preparation of the tilt angle gate structure.
According to the embodiment, the inclination structure is formed by adopting the method for forming silicon dioxide by oxidizing the polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated. The GaN-HEMT device with the inclined angle gate structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
Example 6
The embodiment provides a preparation method of an upper dip angle structure of a GaN-HEMT device, and the preparation method further comprises the following step (6) after the step (5) on the basis of the preparation method provided by the embodiment 2: the preparation of the inclined gate structure shown in fig. 6 is achieved by dry etching the barrier layer 3 and the first SiN layer 4 having the inclined structure.
In this embodiment, through the dry etching in step (6), a dry etching scheme for controlling the etching selection ratio of the first SiN layer 4 to the barrier layer 3 is adopted to transfer the tilt angle structure of the first SiN layer 4 to the barrier layer 3, thereby realizing the preparation of the tilt angle gate structure.
According to the embodiment, the inclination structure is formed by adopting the method for forming silicon dioxide by oxidizing the polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated. The GaN-HEMT device with the inclined angle gate structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
Example 7
The embodiment provides a preparation method of an upper dip angle structure of a GaN-HEMT device, and the preparation method further comprises the following step (6) after the step (5) on the basis of the preparation method provided by the embodiment 3: the preparation of the inclined gate structure shown in fig. 6 is achieved by dry etching the barrier layer 3 and the first SiN layer 4 having the inclined structure.
In this embodiment, through the dry etching in step (6), a dry etching scheme for controlling the etching selection ratio of the first SiN layer 4 to the barrier layer 3 is adopted to transfer the tilt angle structure of the first SiN layer 4 to the barrier layer 3, thereby realizing the preparation of the tilt angle gate structure.
According to the embodiment, the inclination structure is formed by adopting the method for forming silicon dioxide by oxidizing the polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated. The GaN-HEMT device with the inclined angle gate structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
Example 8
The embodiment provides a preparation method of an upper dip angle structure of a GaN-HEMT device, and the preparation method further comprises the following step (6) after the step (5) on the basis of the preparation method provided by the embodiment 4: the preparation of the inclined gate structure shown in fig. 6 is achieved by dry etching the barrier layer 3 and the first SiN layer 4 having the inclined structure.
In this embodiment, through the dry etching in step (6), a dry etching scheme for controlling the etching selection ratio of the first SiN layer 4 to the barrier layer 3 is adopted to transfer the tilt angle structure of the first SiN layer 4 to the barrier layer 3, thereby realizing the preparation of the tilt angle gate structure.
According to the embodiment, the inclination structure is formed by adopting the method for forming silicon dioxide by oxidizing the polysilicon, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated. The GaN-HEMT device with the inclined angle gate structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
In summary, the inclination structure is formed by adopting the method of oxidizing the polysilicon to form the silicon dioxide, the inclination structure is regulated and controlled by regulating the condition of oxidation treatment, the precise control is easier to realize, and the industrial production is facilitated; the GaN-HEMT device with the dip angle structure has high gain and high linearity compared with the traditional structure when being applied to the radio frequency field; when the method is applied to the field of power electronics, the electric field intensity of the side, close to the drain electrode, of the grid electrode can be reduced better.
The applicant declares that the above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and it should be apparent to those skilled in the art that any changes or substitutions that are easily conceivable within the technical scope of the present invention disclosed by the present invention fall within the scope of the present invention and the disclosure.
Claims (10)
1. The preparation method of the upper dip angle structure of the GaN-HEMT device is characterized by comprising the following steps of:
(1) Sequentially growing a first SiN layer, a polysilicon layer, a silicon dioxide layer and a second SiN layer on the surface of the GaN-HEMT epitaxial structure wafer;
(2) Etching the second SiN layer, the silicon dioxide layer and the polysilicon layer in sequence to form a deep trench so that the side wall of the polysilicon layer is exposed;
(3) Oxidizing the GaN-HEMT after photoetching the opening to form an inclined angle structure on the polysilicon layer;
(4) Etching to remove the second SiN layer and the silicon dioxide layer;
(5) And etching the polysilicon layer and the first SiN layer to transfer the inclination angle structure morphology of the polysilicon layer to the first SiN layer.
2. The method of claim 1, wherein the growing the first SiN layer, the polysilicon layer, the silicon dioxide layer, and the second SiN layer in step (1) comprises any one or a combination of at least two of chemical vapor deposition, atomic layer deposition, sputtering, or oxide growth.
3. The method of claim 1, wherein the etching in step (2) is: and sequentially etching the second SiN layer, the silicon dioxide layer and the polysilicon layer by dry etching by using the photoresist as a mask, and then removing the photoresist mask.
4. The method of claim 1, wherein the oxidation treatment of step (3) comprises dry oxygen oxidation and/or wet oxygen oxidation.
5. The method of claim 1, wherein the etching removal in step (4) comprises wet etching and/or dry etching.
6. The method of claim 1, wherein the method of etching in step (5) comprises dry etching.
7. The method according to claim 1, wherein the wafer having a GaN-HEMT epitaxial structure in step (1) comprises a substrate, a GaN epitaxial layer and a barrier layer stacked;
the material of the barrier layer comprises any one or a combination of at least two of AlGaN, inGaN or InAlGaN.
8. The method of claim 1, further comprising step (6) after step (5): and etching the barrier layer and the first SiN layer with the dip angle structure to prepare the dip angle gate structure.
9. The method of claim 8, wherein the etching in step (6) comprises dry etching.
10. The preparation method according to claim 1, characterized in that the preparation method comprises the steps of:
(1) Sequentially growing a first SiN layer, a polycrystalline silicon layer, a silicon dioxide layer and a second SiN layer on the surface of a wafer with a GaN-HEMT epitaxial structure;
(2) Etching the second SiN layer, the silicon dioxide layer and the polysilicon layer in sequence to form a deep trench so that the side wall of the polysilicon layer is exposed; the etching is to use photoresist as a mask, sequentially etch the second SiN layer, the silicon dioxide layer and the polysilicon layer by dry etching, and then remove the photoresist mask;
(3) Oxidizing the GaN-HEMT after photoetching the opening to form an inclined angle structure on the polysilicon layer;
(4) Etching to remove the second SiN layer and the silicon dioxide layer; the etching removal method comprises wet etching and/or dry etching;
(5) Dry etching is carried out on the polysilicon layer and the first SiN layer to transfer the inclination angle structure morphology of the polysilicon layer to the first SiN layer;
(6) And dry etching the barrier layer and the first SiN layer with the dip angle structure to prepare the dip angle gate structure.
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| JP2004343001A (en) * | 2003-05-19 | 2004-12-02 | Alps Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2005116555A (en) * | 2003-10-02 | 2005-04-28 | Alps Electric Co Ltd | Method of manufacturing semiconductor device |
| KR20050083283A (en) * | 2004-02-23 | 2005-08-26 | 주식회사 하이닉스반도체 | Method of forming isolation film in flash memroy device |
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| JP2004343001A (en) * | 2003-05-19 | 2004-12-02 | Alps Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2005116555A (en) * | 2003-10-02 | 2005-04-28 | Alps Electric Co Ltd | Method of manufacturing semiconductor device |
| KR20050083283A (en) * | 2004-02-23 | 2005-08-26 | 주식회사 하이닉스반도체 | Method of forming isolation film in flash memroy device |
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