CN111430456A - Fin-like side wall modulation HEMT device based on transconductance compensation method and preparation method thereof - Google Patents
Fin-like side wall modulation HEMT device based on transconductance compensation method and preparation method thereof Download PDFInfo
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Abstract
The invention relates to a HEMT device modulated by a Fin-like side wall based on a transconductance compensation method and a preparation method thereof, wherein the HEMT device comprises: a substrate layer; an insertion layer on the substrate layer; a buffer layer on the insertion layer; a source electrode positioned at one end of the buffer layer; the drain electrode is positioned at the other end of the buffer layer; the barrier layer is positioned on the buffer layer and positioned between the source electrode and the drain electrode, wherein the barrier layer is provided with a plurality of grooves which are arranged along the width direction of the gate, and the depth of each groove is smaller than the thickness of the barrier layer; the passivation layer covers the source electrode, the drain electrode and the barrier layer, wherein a gate groove penetrates through the passivation layer along the width direction of the gate, and the grooves are positioned below the gate groove; the gate electrode is positioned in the grooves and the gate grooves and positioned on the surface of the passivation layer; and the metal interconnection layer penetrates through the passivation layer and is positioned on the source electrode and the drain electrode. According to the HEMT device, the grooves are arranged in the width direction of the grid to form a Fin-like structure, so that the application requirements of high-frequency high-linearity and high-voltage high-linearity can be met.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a Fin-like side wall modulation HEMT device based on a transconductance compensation method and a preparation method thereof.
Background
In recent years, with the rapid increase of the demand of the internet of things and the development of mobile devices, there is a higher requirement for the transmission efficiency of wireless communication technology, for example, in the field of millimeter wave applications such as 5G-L TE, WIMAX, satellite communication, radar, and space applications, and a Power Amplifier (PA) is an important component of a communication link transmitter, and in order to obtain sufficient transmission power, the PA must operate under a high-power output condition, but at this time, the PA consumes a large amount of power, and has poor linearity, which causes low transmission efficiency, signal distortion, and reduced transmission quality, so in order to improve the linearity of the PA, the Power Added Efficiency (PAE) is improved.
The application of the Si-based MOS transistor as the most mature device of the power amplifier is widely developed, but the problems of low working frequency, large power consumption, low conversion efficiency, poor high temperature resistance and the like are limited in the further development of the high-frequency and high-power field, and the GaN as a wide-bandgap semiconductor material has high saturated electron speed, high mobility and larger breakdown field strength, so that the development of the transistor device in the high-frequency and high-power field is promoted. However, as the integration degree is continuously improved and the device size is continuously reduced, the GaN-based HEMT device of the conventional planar structure is more and more significantly affected by the short channel effect, the gate leakage and the source driving resistance Rs, so that the device generates severe intermodulation distortion (IMD) when the device inputs power at a large Radio Frequency (RF), the device generates nonlinear gain, the transconductance is reduced, and the linearity is deteriorated.
For the above reasons, various methods have been proposed over the years to improve the nonlinear characteristics of transistors. In 1992, d.r.green of bell experiments proposed the fabrication of high linearity devices using multi-channel structures with different widths, different depths, and different carrier concentrations; in the method, channels with different quantum wells under a gate are conducted under different gate biases to achieve the purposes of adjusting the threshold of the device and improving the linearity of the device, but the method has limited control capability on the threshold, and simultaneously, in order to ensure the gradual starting of a plurality of channels, larger gate voltage needs to be applied, so that great gate leakage is generated before the channels on a lower layer are conducted, and the reliability problem of the device is caused.
In 2013, Dong Seup L ee and the like research the modulation effect of a source driving resistor Rs on the transconductance of a device.
At present, there are three methods for improving the linearity of devices in the prior art: 1. the linearity of the device is improved by using a Fin (Fin) structure; 2. the linearity of the device is improved by utilizing the gradient barrier layer; 3. the device linearity is improved with MIS HEMT structures.
The method is characterized in that a Fin structure is utilized to improve the linearity, and the core of the technology is that a barrier layer is etched in an Access region between a lower source and a lower drain of a grid to form a three-dimensional Fin structure, so that the source driving capability of the Access region is increased, and Rs is reduced; by the formula:
it can be seen that when the source resistance Rs is reduced, the intrinsic transconductance thereof is increased, and the linearity of the device is improved by connecting the devices with different widths Fin in parallel. However, in the etching process of the Fin structure, the method can bring about larger etching damage and introduce serious interface state problem, and more importantlyThe etching can release the lattice stress at the AlGaN/GaN heterojunction interface, so that the 2DEG concentration is reduced, the output current of the device is reduced, the working characteristics of the device are seriously influenced, in addition, the parasitic capacitance formed by the Fin structure also limits the application of the device under high frequency, and simultaneously, the current driving capability is reduced under the condition of the same grid width due to the Fin structure, and the output power of the device is degraded.
High linearity is achieved by a graded barrier layer, i.e. Al is achieved in the thickness direction during the growth of the materialxGa1-xThe gradual change of the Al component in the N potential barrier modulates the channel 2DEG through different Al components in the potential barrier layer, so that the gradual opening of a plurality of thresholds is realized, and the linearity is improved. However, the essence of this method is that in the process of material growth, barrier layers of different Al compositions are grown in an overlapping manner, so as to realize the gradual change of the whole barrier layer, this growth process will increase the process complexity, secondly, the barrier layers grown by this method are generally thicker, and in the design of high frequency devices, because the short channel effect is an important consideration factor, the thicker barrier layers bring a great hindrance to the improvement of the frequency characteristics of the devices, so the gradual change barrier layer technique is not suitable for manufacturing millimeter wave high linear devices, and it is mainly suitable for low frequency (below 10 GHz) high linear devices.
The MIS structure is used for improving the linearity of the device, a layer of high-K dielectric layer is grown under the grid of the conventional HEMT structure, and compared with the conventional HEMT device, the MIS structure can reduce grid leakage by about 4-6 orders of magnitude and well solve the problem of grid leakage, so that large grid voltage swing can be realized and the linearity of the device can be improved. However, the gate parasitic capacitance introduced by the insulating layer under the gate deteriorates the frequency characteristics of the device, and is not suitable for manufacturing high-frequency devices.
In summary, the method for improving the linearity of the device in the prior art has the problems of large etching damage of the device, thick barrier layer and large gate parasitic capacitance, and limits the application of the linear device in high frequency.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a Fin-like side wall modulated HEMT device based on a transconductance compensation method and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a HEMT device modulated by a Fin-like side wall based on a transconductance compensation method, which comprises the following steps:
a substrate layer;
an insertion layer on the substrate layer;
a buffer layer on the insertion layer;
a source electrode positioned at one end of the buffer layer;
the drain electrode is positioned at the other end of the buffer layer;
the barrier layer is positioned on the buffer layer and positioned between the source electrode and the drain electrode, wherein a plurality of grooves which are arranged along the width direction of the gate are arranged on the barrier layer, and the depth of each groove is smaller than the thickness of the barrier layer;
the passivation layer covers the source electrode, the drain electrode and the barrier layer, wherein a gate groove penetrates through the passivation layer along the gate width direction, and the grooves are positioned below the gate groove;
the gate electrode is positioned in the grooves and the gate grooves and positioned on the surface of the passivation layer;
and the metal interconnection layer penetrates through the passivation layer and is positioned on the source electrode and the drain electrode.
In an embodiment of the invention, the grooves and the unetched regions are arranged periodically, and each period includes at least one groove.
In one embodiment of the invention, the depth of the groove remains constant.
In one embodiment of the invention, the depth of the groove is gradual.
In one embodiment of the present invention, further comprising: and the insulating layer covers the side walls and the bottoms of the grooves, the side walls and the bottoms of the gate grooves and the surface of the passivation layer.
In one embodiment of the invention, the thickness of the insulating layer is 2-10 nm.
Another embodiment of the present invention provides a method for preparing a Fin-like sidewall modulated HEMT device based on a transconductance compensation method, comprising the steps of:
s1, sequentially growing an insertion layer, a buffer layer and a barrier layer on the substrate layer;
s2, preparing a source electrode at one end of the buffer layer, and preparing a drain electrode at the other end of the buffer layer;
s3, growing a passivation layer on the barrier layer, the source electrode and the drain electrode;
s4, etching the passivation layer between the source electrode and the drain electrode along the width direction of the gate to form a gate groove penetrating through the passivation layer;
s5, etching the barrier layer in the gate groove to form a plurality of grooves arranged along the width direction of the gate;
s6, depositing gate metal in the grooves, the gate grooves and the passivation layer to form gate electrodes;
s7, preparing metal interconnection layers of the source electrode and the drain electrode in the passivation layer.
In one embodiment of the present invention, step S5 includes:
s51, photoetching array groove regions on the barrier layer, and enabling the array groove regions to be periodically arranged along the gate width direction;
s52, removing the barrier layer in the groove area by utilizing an inductive coupling plasma etching process to form a plurality of grooves.
In an embodiment of the present invention, the step between the step S5 and the step S6 further includes the steps of:
and X, growing an insulating layer on the bottom and the side wall of the groove, the bottom and the side wall of the gate groove and the surface of the passivation layer.
In one embodiment of the invention, the thickness of the insulating layer is 2-10 nm.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the HEMT device, the plurality of grooves are arranged in the width direction of the gate to form a Fin-like structure, and the depth of the grooves is smaller than the thickness of the barrier layer, so that the 2DEG below the grooves is not damaged, and the HEMT device not only realizes larger current output, but also realizes higher linearity, thereby meeting the application requirements of high frequency and high linearity, and also meeting the application requirements of high frequency and high linearity.
2. In the HEMT device, high linear devices with different grid voltage swing amplitudes and different peak value transconductance can be realized by controlling the combination proportion of the groove and the non-etched region, the width of the groove and the depth of the groove, so that the customization of the grid voltage swing amplitude and the peak value transconductance can be realized, and different requirements can be met.
Drawings
Fig. 1 is a schematic structural diagram of a Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention;
fig. 2a to fig. 2c are cross-sectional views of a Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention;
fig. 3 a-3 b are cross-sectional side views of two Fin-like sidewall modulated HEMT devices based on a transconductance compensation method according to an embodiment of the present invention;
fig. 4 is a schematic diagram of multi-electric-field coupling of side wall modulation in a Fin-like period in the gate width direction of a Fin-like HEMT device based on Fin-like side wall modulation of a transconductance compensation method according to an embodiment of the present invention;
fig. 5 is a schematic flowchart of a method for manufacturing a Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention;
fig. 6a to fig. 6h are schematic process diagrams of a method for manufacturing a Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention;
fig. 7 is a schematic flow chart of a manufacturing method of another Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
The embodiment of the invention aims to provide a multi-field coupling regulation and control technology of Fin-like side wall modulation based on a transconductance compensation method aiming at the defects of the conventional high-linearity HEMT device, so as to realize the high-linearity HEMT device and meet the application requirements of high frequency and high linearity.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a HEMT device based on Fin-like sidewall modulation of a transconductance compensation method according to an embodiment of the present invention, where the HEMT device includes: the substrate layer 1, the insertion layer 2, the buffer layer 3, the source electrode 4, the drain electrode 5, the barrier layer 6, the passivation layer 7, the gate electrode 8 and the metal interconnection layer 9.
In particular, the substrate layer 1 comprises one or more of sapphire, SiC or Si. An insertion layer 2, which may be of AlN, is located on the substrate layer 1. A buffer layer 3, which may be GaN, is located on the insertion layer 2. The source electrode 4 is positioned at one end of the buffer layer 3, and the drain electrode 5 is positioned at the other end of the buffer layer 3; the source electrode 4 and the drain electrode 5 are made of ohmic metal and sequentially comprise Ti/Al/Ni/Au from bottom to top. The barrier layer 6 is positioned on the buffer layer 3, and the barrier layer 6 is positioned between the source electrode 4 and the drain electrode 5; the material of the barrier layer 6 may be AlGaN, InAlN, AlN, or the like. The passivation layer 7 covers the source electrode 4, the drain electrode 5 and the barrier layer 6; the passivation layer 7 is made of SiN, and the thickness of the SiN is 20-120 nm (for example, 20nm, 60nm or 120 nm).
The barrier layer 6 is provided with a plurality of grooves 61 arranged in the gate width direction, and the plurality of grooves 61 form a Fin-like structure.
A gate trench 71 penetrates the passivation layer 7 in the gate width direction, and the gate trench 71 is located right above the grooves 61 to expose the surface of the barrier layer 6.
A gate electrode 8 is arranged on the passivation layer 7 at a side close to the source electrode 4, and the gate electrode 8 is positioned in the grooves 61 and the gate groove 71. Since the groove 61 is located in the barrier layer 6 and the gate groove 71 penetrates the passivation layer 7, the gate leg of the gate electrode 8 is located on the surface of the barrier layer 6.
The metal interconnection layer 9 penetrates the passivation layer 7 and is located on the source electrode 4 and the drain electrode 5.
Referring to fig. 2a to fig. 2c, fig. 2a to fig. 2c are cross-sectional views of a Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention, where fig. 2a is a cross-sectional front view of an un-etched region, fig. 2b is a cross-sectional front view of a groove, and fig. 2c is a cross-sectional side view.
In one embodiment, the grooves 61 (i.e., the etched areas) are periodically arranged with the non-etched areas, and each period includes at least one groove 61.
Specifically, the barrier layer 6 is divided into a plurality of periods along the gate width direction, and the lengths of the periods may be the same, may have an increasing or decreasing trend, or may have a periodic variation. Specifically, the length of each period may be 0.2um to 50um, but the embodiment of the present invention is not limited thereto; preferably, the smaller the length of each period, the better the linearity of the device.
In each period, a part of the barrier layer 6 is etched away to form at least one groove 61, and the other part of the barrier layer 6 is not etched away to form at least one non-etched region; that is, in each period, one groove 61 and one unetched region may be formed, one groove 61 and a plurality of unetched regions may be formed, or a plurality of grooves 61 and a plurality of unetched regions may be formed; for example, in fig. 2c, one period may be defined as one groove 61 and one unetched region, or may be defined as 2 grooves 61 and 2 unetched regions. Further, in a plurality of periods in the gate width direction, the number of the grooves 61 and the number of the unetched regions may be the same or different in each period, for example, in the first period, the number of the grooves 61 is 1, the number of the unetched regions is also 1, in the second period, the number of the grooves 61 is plural, and the number of the unetched regions is also plural.
In one embodiment, the width of the groove 61 is determined by the ratio of the width of each period to the width of the non-etched region of the etched region in each period; preferably, the ratio of the width of groove 61 to the width of the unetched region in each period is greater than or equal to 5:5 and less than or equal to 8.5: 1.5. Further, when each period includes a plurality of grooves 61, the widths of the plurality of grooves may be equal, may also have an increasing or decreasing trend, and may also have a periodic variation; the widths of the grooves 61 in the plurality of periods may be equal, may have an increasing or decreasing trend, or may have a periodic variation.
In a specific embodiment, the depth of the recess 6 is less than the thickness of the barrier layer 6, ensuring that the 2DEG is not broken. When each period includes a plurality of grooves 61, the depths of the plurality of grooves may be equal, may have an increasing or decreasing trend, or may have a periodic variation; the depth of the grooves 61 may be equal, may have an increasing or decreasing trend, or may have a periodic variation. Specifically, the depth of the groove 61 may be 10 to 15 nm.
In one embodiment, the shape of the groove 61 includes, but is not limited to, rectangle, polygon, and semi-circular arc, and the specific shape can be etched according to the device requirement.
Referring to fig. 2c and fig. 3a to fig. 3b, fig. 3a to fig. 3b are cross-sectional side views of two kinds of Fin-like sidewall modulated HEMT devices based on the transconductance compensation method according to the embodiment of the present invention, wherein the depth of the grooves in fig. 3a is arranged in a V shape, and the depth of the grooves in fig. 3b is gradually increased in a step shape.
In fig. 2c, the depth of each groove 61 is constant, i.e. the bottom of each groove 61 is horizontal, and the depth at each position in the groove 61 is equal.
In fig. 3a and 3b, the depth of each groove 61 is tapered, with different depths at various locations within the groove 61. Specifically, each period includes one groove 61 and one unetched region; the width of the grooves 61 is equal in each period, and the grooves 61 have a gradually changing depth. Further, in fig. 3a, the groove 61 is an inverted triangle, the depth of the middle position of the groove 61 is the largest, the depths of the two sides are the smallest, and the unetched regions on the two sides of the groove 61 are in a slope shape. In fig. 3b, the recess 61 is in the shape of an oblique triangle, the deepest part of the recess is located at one side of the unetched region, and the depth of the recess gradually increases from one unetched region to another unetched region.
Referring to fig. 4, fig. 4 is a schematic diagram of multi-field coupling of sidewall modulation in a Fin-like period in the gate width direction of a Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention. For conventional HEMT devices, when a voltage is applied to the gate electrode, an electric field is formed across the gate metal, and the gate metal itself also has a depletion effect, affecting the 2DEG concentration under the gate. For the Fin-like structure in fig. 3, a groove 61 is arrayed under the gate electrode 8, schottky metal contacts can be formed in the groove 61 and on the side wall of the groove 61, and thus an electric field effect can be generated in the groove 61 and on the side wall; the side wall can generate accumulation of electrons under the action of an electric field, the current density of the side wall is enhanced, and the bottom of the groove has a more obvious depletion effect on electron gas because the bottom of the groove is closer to the 2 DEG.
Therefore, the point that the electric field action can be generated in the groove 61 and on the side wall can be utilized to design that two or more etching depths are combined in the same period to achieve the effect of gradual depletion of the 2DEG, so that the gradual starting of the device is realized, and the linearity is improved.
In summary, in this embodiment, the number of periods, the width of each period, the ratio of the width of the groove to the width of the un-etched region, and the depth of the groove may be adjusted and combined as required to meet different linearity requirements, thereby implementing the customization of device linearity.
Specifically, the present embodiment adjusts to achieve customization of device linearity from several angles:
firstly, two or more devices with different threshold voltages are connected in parallel by using a transconductance compensation method, namely, a specific region in the gate width direction of the barrier layer 6 is etched by a certain depth by using a coupled plasma etching technology, the control capability of the grooves is different due to different distances between the grooves 61, an un-etched region and the 2DEG channel, namely, different threshold voltages are formed at different etching depths, two or more devices are connected in parallel according to requirements to form a Fin-like structure, and therefore different devices are gradually started in the gate width direction.
And secondly, under the condition that the 2DEG below the etching region is not damaged, the etching depth is changed, so that the difference between the threshold voltage of a planar device formed in the non-etching region and the threshold voltage of a plurality of groove devices with different depths (the grooves 6 with different depths can be etched according to requirements) is about 2-3V, and a wider grid voltage swing is realized.
Thirdly, the ratio of the groove 6 in the gate width direction to the non-etched area is changed, so that the maximum transconductance (G) of the device at the groove 6 is increasedmR) Coefficient of proportionality to etching (R)R) Product of (c) and maximum transconductance (G) of the device in the unetched regionmN) Coefficient of proportionality to unetched (R)N) Are substantially equal (i.e., G)mR×RR＝GmN×RNWherein R isR+RN1) by changing RR(or R)N) The value of (3) can realize the adjustment of the transconductance peak value of the Fin-like HEMT device; when R isRWhen the etching depth is reduced within an allowable range, the etching depth is increased, and the overall peak value transconductance is increased; in the same way, when RNWhen the total peak transconductance is reduced within an allowable range, the etching depth is reduced, and the total peak transconductance is reduced.
Fourthly, the side wall modulation multi-electric field coupling effect is utilized to regulate and control the 2DEG of the groove 6 and the non-etched area. The transconductance compensation method is used for connecting a plurality of devices with different thresholds in parallel to realize gradual starting of the thresholds, the gate voltage swing amplitude of the devices can be obviously improved, but the process causes that the transconductance has a serious multi-peak problem, the transconductance flatness is not greatly improved, and the transconductance still has a large high-order transconductance peak value, but in the Fin-like structure of the embodiment, the strength of a side wall modulation coupling electric field can be changed by changing the width of an etching area in a certain period (T), in an etching period in the gate width direction, the electric field mainly comes from four directions of a transverse electric field generated by two side walls of the Fin-like structure, a vertical downward electric field generated by the top of a barrier layer and a downward electric field generated by a groove area, when the period (T) is fixed, the narrower the unetched area is in an allowable range, the number of the side walls is larger, the transverse electric field generated by the two side walls is stronger, the more obvious the coupling electric field effect is, the stronger the control effect on the 2DEG under the gate of the non-etched region is, the more gradual the descending trend of the transconductance of the non-etched region after reaching the peak point is, and the multimodal phenomenon of the transconductance of the combined device is improved and even eliminated.
Preferably, when the width of each period is 0.5 μm and the ratio of the width of the groove 61 to the width of the unetched region is 7:3, while ensuring that the 2DEG under the barrier layer 6 is not etched, the linearity of the device can be greatly improved.
The HEMT device of the embodiment forms a Fin-like structure by arranging the grooves in the width direction of the gate, and the depth of the grooves is smaller than the thickness of the barrier layer, so that the 2DEG below the grooves is not damaged, large current output is realized, high linearity is realized, the structure can be combined with various gate processes, the application requirement of high frequency and high linearity is realized, and the requirement of high voltage and high linearity can be realized by combining the MIS structure and the Fin-like structure.
The HEMT device of this embodiment can realize high-linearity devices with different gate voltage swings and different peak transconductance by optimizing the etching proportion, etching width, and etching depth of the gate width direction arrayed groove 61, and can realize customization of the gate voltage swings and the peak transconductance according to the above three key parameters to a certain extent, so as to meet different requirements.
Example two
On the basis of the first embodiment, please refer to fig. 5 and fig. 6a to fig. 6h, where fig. 5 is a schematic flow diagram of a method for manufacturing a Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention, and fig. 6a to fig. 6h are schematic process diagrams of a method for manufacturing a Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention. The preparation method comprises the following steps:
s1, sequentially growing an insertion layer 2, a buffer layer 3, and a barrier layer 6 on the substrate layer 1. Please refer to fig. 6 a.
In this embodiment, an epitaxial substrate including a substrate layer 1, an AlN insertion layer 2, a GaN buffer layer 3, and an AlGaN barrier layer 6 in this order from bottom to top is used as an initial material.
S2, preparing a source electrode 4 at one end of the buffer layer 3 and a drain electrode 5 at the other end of the buffer layer 3, as shown in fig. 6 b.
S21, source and drain electrode regions are patterned on the AlGaN barrier layer 6.
First, the epitaxial substrate was baked on a hot plate at 200 ℃ for 5 min.
Then, a lift-off glue was applied to the AlGaN barrier layer 6 with a spin thickness of 0.35 μm, and the sample was baked on a hot plate at 200 ℃ for 5 min.
Next, the resist was applied and spun on the resist to a thickness of 0.77 μm, and the sample was baked on a hot plate at 90 ℃ for 1 min.
And finally, putting the sample subjected to glue coating and spin coating into a photoetching machine to expose the coated surface, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue, and then carrying out ultra-pure water washing and nitrogen gas blowing on the sample to form a source electrode area and a drain electrode area.
S22, evaporating the source electrode 4 and the drain electrode 5 on the AlGaN barrier layer 6 in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region.
Firstly, a sample with a photoetching pattern of the active electrode 4 and the drain electrode 5 is put into a plasma photoresist remover for carrying out bottom film treatment, wherein the treatment time is 5 min.
Then, the sample is put into an electron beam evaporation table, and the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 × 10-6And Torr, evaporating ohmic metal on the AlGaN barrier layer in the source electrode area and the drain electrode area and the photoresist outside the source electrode area and the drain electrode area to form a source electrode 4 and a drain electrode 5, wherein the ohmic metal is Ti/Al/Ni/Au in sequence from bottom to top.
And finally, stripping the sample subjected to ohmic metal evaporation to remove the ohmic metal, the photoresist and the stripping glue outside the source electrode 4 and the drain electrode 5, flushing the sample with ultrapure water and drying the sample with nitrogen.
S23, putting the sample which completes the evaporation and stripping of the ohmic metal into a rapid thermal annealing furnace for annealing treatment so as to enable the source electrode 4 and the leakage currentAnd the ohmic metal on the AlGaN barrier layer 6 in the pole 5 sinks to the GaN buffer layer 3, so that ohmic contact between the ohmic metal and the heterojunction channel is formed, and the annealing process conditions are as follows: annealing atmosphere is N2The annealing temperature was 830 ℃ and the annealing time was 30 s.
And S3, etching the electric isolation area of the active area on the AlGaN barrier layer 3, and manufacturing the electric isolation of the active area of the device by utilizing an ICP (inductively coupled plasma) process.
S31, lithographically forming electrically isolated regions on the AlGaN barrier layer.
First, the sample was baked on a hot plate at 200 ℃ for 5 min.
Then, the photoresist was coated and spun at 3500 rpm, and the sample was baked on a 90 ℃ hot plate for 1 min.
Finally, the sample is put into a photoetching machine to expose the photoresist in the electric isolation area, the exposed sample is put into a developing solution to remove the photoresist in the electric isolation area, and the photoresist is washed by ultrapure water and dried by nitrogen;
and S32, etching an electric isolation area on the AlGaN barrier layer.
Firstly, an AlGaN barrier layer and a GaN buffer layer in an electrical isolation region are etched in sequence by utilizing an ICP (inductively coupled plasma) process to realize mesa isolation of an active region, wherein the total etching depth is 100 nm.
And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electric isolation area, washing the sample with ultrapure water and drying with nitrogen.
S4, growing a passivation layer 7 on the barrier layer 6 of the active region, the source electrode 4 and the drain electrode 5. Please refer to fig. 6 c.
And S41, performing surface cleaning on the sample subjected to active area electrical isolation.
First, the sample was put into an acetone solution and ultrasonically cleaned for 3mim at an ultrasonic intensity of 3.0.
Then, the sample was heated in a water bath for 5min in a stripping solution at a temperature of 60 ℃.
And then, putting the sample into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3min, wherein the ultrasonic intensity is 3.0.
Finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.
And S42, growing a passivation layer 7 with a thickness by utilizing a PECVD process on the source electrode 4, the drain electrode 5 and the AlGaN barrier layer 6 of the active region.
Specifically, in the present embodiment, the passivation layer 7 is made of SiN and has a thickness of 60 nm; the growth process conditions are as follows: by NH3And SiH4As the reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 22W.
And S5, etching the passivation layer 7 between the source electrode 4 and the drain electrode 5 along the gate width direction to form a gate groove 71 penetrating through the passivation layer 7. Please refer to fig. 6 d.
And S51, etching a gate groove area on the SiN passivation layer.
First, the sample was baked on a hot plate at 200 ℃ for 5 min.
Then, the photoresist was coated and spun at 3500 rpm, and the sample was baked on a 90 ℃ hot plate for 1 min.
And then, putting the sample into a photoetching machine to expose the photoresist in the gate groove area.
And finally, putting the exposed sample into a developing solution to remove the photoresist in the gate groove area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist, thereby forming the gate groove area along the width direction of the gate.
S52, removing the SiN passivation layer 7 in the gate trench region by using an Inductively Coupled Plasma (ICP) etching process to form a gate trench 71 penetrating through the SiN passivation layer 7; the etching conditions are as follows: the reaction gas being CF4And O2The pressure of the reaction chamber is 10mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 60nm till the surface of the AlGaN barrier layer 6.
S6, the barrier layer 6 in the gate trench 71 is etched to form a plurality of grooves 61 arranged in the gate width direction. Please refer to fig. 6 e.
And S61, photoetching array groove areas on the barrier layer, and enabling the array groove areas to be periodically arranged along the width direction of the gate.
First, the sample was baked on a hot plate at 200 ℃ for 5 min.
Then, the photoresist was coated and spun at 3500 rpm, and the sample was baked on a 90 ℃ hot plate for 1 min.
Next, the sample is placed in a photolithography machine to expose the photoresist in the groove region.
Finally, the exposed sample is put into a developing solution to remove the photoresist in the groove area, and the photoresist is washed by ultrapure water and dried by nitrogen.
S62, removing the AlGaN barrier layer 6 in the groove region by utilizing an ICP (inductively coupled plasma) etching process, so that the depth of the groove 61 is smaller than the thickness of the AlGaN barrier layer 6, and forming a Fin-like structure. The etching conditions are as follows: the reaction gas is Cl2And BCl3The pressure of the reaction chamber is 5mTorr, the radio frequency power of the upper electrode and the lower electrode is 80W and 10W respectively, and the etching depth is 10 nm-15 nm.
For a detailed structure of the groove 61, please refer to the first embodiment, which is not described in detail herein.
S7, depositing a gate metal in the grooves 61, in the gate groove 71 and on the passivation layer 7 to form a gate electrode 8. See fig. 6f and 6 g.
S71, a gate electrode region is etched on the AlGaN barrier layer 6.
First, the sample was baked on a hot plate at 200 ℃ for 5 min.
Then, the SiN passivation layer was coated with a release coating of 0.35 μm in thickness and spin-coated with a release coating, and the sample was baked on a hot plate at 200 ℃ for 5 min.
Next, the resist was applied and spun on the resist to a thickness of 0.77 μm, and the sample was baked on a hot plate at 90 ℃ for 1 min.
And then, putting the sample subjected to glue spreading and whirl coating into a photoetching machine to expose the photoresist in the gate electrode area.
And finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the gate electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue.
S72, evaporating the gate electrode on the AlGaN barrier layer 6 in the gate electrode region and on the photoresist outside the gate electrode region.
Firstly, a sample with a gate electrode photoetching pattern is placed in a plasma photoresist remover to be processed by a bottom film, and the processing time is 5 min.
Then, the sample is put into an electron beam evaporation table, and the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 × 10-6And evaporating gate metal on the AlGaN barrier layer 6 in the gate electrode area and the photoresist outside the gate electrode area after the Torr, wherein the gate metal is a metal stack structure consisting of three layers of Ni, Au and Ni from bottom to top in sequence.
And finally, stripping the sample subjected to gate metal evaporation to remove the gate metal, the photoresist and the stripping glue outside the gate electrode area, flushing the sample with ultrapure water and drying the sample with nitrogen to form the gate electrode 8.
S8, preparing metal interconnection layers 9 of the source electrode 4 and the drain electrode 5 in the passivation layer 7. Please see fig. 6 h.
S81, etching the metal interconnection opening region on the SiN passivation layer 7, and sequentially etching away the SiN passivation layer 7 in the interconnection opening region by using an ICP process.
And S811, etching a metal interconnection opening region on the SiN passivation layer 7.
First, the sample was baked on a hot plate at 200 ℃ for 5 min.
Then, the photoresist was coated and spun at 3500 rpm, and the sample was baked on a 90 ℃ hot plate for 1 min.
And then, putting the sample into a photoetching machine to expose the photoresist in the metal interconnection open hole area.
Finally, the exposed sample is placed into a developing solution to remove the photoresist in the interconnected opening area, and the photoresist is subjected to ultra-pure water washing and nitrogen blow-drying.
S812, utilizing ICP etching process to make the reaction gas be CF4And O2The pressure of the reaction chamber is 10mTorr, and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectivelyThe 60nm thick SiN passivation layer 7 in the interconnect opening region is removed.
And S82, photoetching a metal interconnection layer region on the source electrode 4 and the drain electrode 5 in the metal interconnection opening region and the SiN passivation layer 7 which is not subjected to opening etching, and manufacturing a metal interconnection layer 9 by using an electron beam evaporation process.
And S821, photoetching a metal interconnection layer on the source electrode 4 and the drain electrode 5 in the metal interconnection opening area and the SiN passivation layer 7 which is not subjected to opening etching.
First, the sample on which the metal interconnection open hole etching was completed was baked on a hot plate at 200 ℃ for 5 min.
Then, the source electrode 4 and the drain electrode 5 in the metal interconnection open hole region and the SiN not open hole etched are subjected to glue coating and spin coating of a stripping glue, wherein the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min.
Next, the resist was applied and spun on the resist to a thickness of 0.77 μm, and the sample was baked on a hot plate at 90 ℃ for 1 min.
And finally, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the metal interconnection area, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the metal interconnection area, and washing the photoresist and the stripping glue with ultra-pure water and drying the photoresist with nitrogen.
S822, evaporating the metal interconnection layer on the source electrode 4 and the drain electrode 5 within the metal interconnection region, the SiN passivation layer 7, and the photoresist outside the metal interconnection region.
Firstly, a sample with a metal interconnection area is placed in a plasma degumming machine to be subjected to bottom film treatment, and the treatment time is 5 min.
Then, the sample is put into an electron beam evaporation table, and the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 × 10-6And after the Torr, evaporating interconnection metal on the electrode and the SiN passivation layer 7 in the metal interconnection region and the photoresist outside the metal interconnection region to form a metal interconnection layer 9, wherein the metal interconnection layer 9 adopts a metal stack structure consisting of two layers of Ti and Au from bottom to top in sequence so as to lead out the electrode.
And finally, stripping the sample after the interconnection metal evaporation is finished to remove the metal, the photoresist and the stripping glue outside the metal interconnection zone layer, washing the sample with ultrapure water and drying with nitrogen to form a metal interconnection layer 9, and finishing the device manufacturing.
According to the preparation method of the embodiment, the AlGaN barrier layer 6 is etched in the gate width direction, the grooves which are periodically arranged are prepared, and the Fin-like structure is formed, and the depth of each groove is smaller than the thickness of the AlGaN barrier layer 6, so that the 2DEG below each groove is not damaged, large current output is realized, high linearity is realized, the structure can be combined with various gate processes, the application requirement of high frequency and high linearity is realized, and the requirement of high voltage and high linearity can be realized by combining the MIS structure and the Fin like structure.
In the preparation process of the preparation method of the embodiment, the high-linearity devices with different gate voltage swing amplitudes and different peak transconductance values can be realized by setting the etching proportion, the etching width and the etching depth of the gate width direction array groove 61, and the gate voltage swing amplitude and the peak transconductance values can be customized according to the three key parameters to a certain extent so as to meet different requirements; meanwhile, the preparation process of the embodiment is simple and has strong repeated etching performance.
EXAMPLE III
On the basis of the first embodiment and the second embodiment, please refer to fig. 7, and fig. 7 is a schematic flow chart of a method for manufacturing another Fin-like sidewall modulated HEMT device based on the transconductance compensation method according to the embodiment of the present invention. The preparation method comprises the following steps:
s1, sequentially growing an insertion layer 2, a buffer layer 3, and a barrier layer 6 on the substrate layer 1.
S2, a source electrode 4 is formed on one end of the buffer layer 3, and a drain electrode 5 is formed on the other end of the buffer layer 3.
And S3, etching the electric isolation area of the active area on the AlGaN barrier layer 3, and manufacturing the electric isolation of the active area of the device by utilizing an ICP (inductively coupled plasma) process.
S4, growing a passivation layer 7 on the barrier layer 6 of the active region, the source electrode 4 and the drain electrode 5.
And S5, etching the passivation layer 7 between the source electrode 4 and the drain electrode 5 along the gate width direction to form a gate groove 71 penetrating through the passivation layer 7.
S6, the barrier layer 6 in the gate trench 71 is etched to form a plurality of grooves 61 arranged in the gate width direction.
And S7, growing the insulating layer 10 on the bottom and the side wall of the groove 61, the bottom and the side wall of the gate groove 71 and the surface of the passivation layer 7.
S8, depositing a gate metal in the grooves 61, in the gate groove 71 and on the passivation layer 7 to form a gate electrode 8.
S9, preparing metal interconnection layers 9 of the source electrode 4 and the drain electrode 5 in the passivation layer 7.
Specifically, please refer to embodiment two for the specific operation steps of steps S1-S6 and S8-S9, which is not repeated in this embodiment.
Step S7 is prepared by an a L D process, specifically including the steps of:
and S71, cleaning the surface of the sample subjected to the gate groove etching.
First, the sample was put into an acetone solution and ultrasonically cleaned for 3mim at an ultrasonic intensity of 3.0.
Then, the sample was heated in a water bath for 5min in a stripping solution at a temperature of 60 ℃.
And then, putting the sample into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3min, wherein the ultrasonic intensity is 3.0.
Finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.
S72, putting the sample with the cleaned surface into a plasma enhanced atomic layer deposition PEA L D device, and carrying out in-situ pretreatment on the thin AlGaN barrier layer 6 at the bottom in the groove 61, the AlGaN barrier layer 6 on the inner side wall of the groove 6, the thicker AlGaN barrier layer 6 under the gate without groove etching and the surface of the SiN passivation layer 7 outside the gate groove 71, wherein the treatment process conditions are that the reaction gas is NH3And N2The gas mixture, substrate temperature 300 ℃, RF power set at 200W, process time 5 min.
S73, thin AlGaN barrier layer in the groove region, AlGaN barrier layer on the side wall of the groove region, thicker AlGaN barrier layer under gate without groove etching, and gate grooveThe SiN passivation layer outside the region is deposited on the surface of the passivation layer by PEA L D equipment to form an insulating layer 10 with a thickness of 2nm, wherein in the embodiment, the insulating layer 10 is made of Al3O2(ii) a The deposition process conditions are as follows: by NH3And TMA as a reactive precursor source, the substrate temperature was 300 ℃, the RF power was set at 50W, and the reaction chamber pressure was 0.3 Torr.
S74, putting the sample with the growth of the insulating layer 10 into a rapid thermal annealing furnace for annealing treatment, wherein the annealing process conditions are as follows: the annealing gas is N2The annealing temperature is 500 ℃, and the annealing time is 5 min.
Referring to fig. 8, fig. 8 is a schematic structural diagram of another Fin-like sidewall modulated HEMT device based on a transconductance compensation method according to an embodiment of the present invention. The HEMT device includes: the substrate layer 1, the insertion layer 2, the buffer layer 3, the source electrode 4, the drain electrode 5, the barrier layer 6, the passivation layer 7, the gate electrode 8, the metal interconnection layer 9 and the insulating layer 10.
Specifically, please refer to the first embodiment for the structure of the substrate layer 1, the insertion layer 2, the buffer layer 3, the source electrode 4, the drain electrode 5, the barrier layer 6, the passivation layer 7, the gate electrode 8, and the metal interconnection layer 9, which is not described in detail in this embodiment.
The insulating layer 10 covers the side walls and the bottom of the groove 61, the side walls and the bottom of the gate groove 71 and the surface of the passivation layer 7; that is, the insulating layer 10 covers the grooves 61, the gate grooves 71 and the surface of the passivation layer 7, instead of filling the grooves 61 and the gate grooves 71, and the thickness thereof is thin. Specifically, the thickness of the insulating layer 10 may be 2 to 10 nm; the material of the insulating layer is selected from high-K or low-K dielectric, including but not limited to Al2O3、HfO2、HfZrO、AlN。
In this embodiment, a thin insulating layer 10 covers the groove 61 and the gate groove 71, which can increase the gate control capability, reduce the gate leakage, and realize a high-linearity HEMT device at a lower frequency.
In this embodiment, a thin insulating layer 10 is grown below the gate electrode 8, which can increase the gate control capability, reduce the gate leakage, and realize a high-linearity HEMT device at a lower frequency.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A kind of Fin side wall modulated HEMT device based on transconductance compensation method, characterized by that, it includes:
a substrate layer (1);
an insert layer (2) located on the substrate layer (1);
a buffer layer (3) on the insertion layer (2);
a source electrode (4) located at one end of the buffer layer (3);
a drain electrode (5) located at the other end of the buffer layer (3);
the barrier layer (6) is positioned on the buffer layer (3) and positioned between the source electrode (4) and the drain electrode (5), wherein a plurality of grooves (61) arranged along the width direction of the gate are arranged on the barrier layer (6), and the depth of each groove (61) is smaller than the thickness of the barrier layer (6);
the passivation layer (7) covers the source electrode (4), the drain electrode (5) and the barrier layer (6), a gate groove (71) penetrates through the passivation layer (7) along the gate width direction, and the grooves (61) are located below the gate groove (71);
the gate electrode (8) is positioned in the grooves (61) and the gate grooves (71) and positioned on the surface of the passivation layer (7);
and the metal interconnection layer (9) penetrates through the passivation layer (7) and is positioned on the source electrode (4) and the drain electrode (5).
2. A Fin-like sidewall modulated HEMT device based on transconductance compensation method according to claim 1, wherein said recesses (61) are arranged periodically with the non-etched regions and each period comprises at least one of said recesses (61).
3. A Fin-like sidewall modulated HEMT device based on transconductance compensation method according to claim 2, wherein said recess (61) is of constant depth.
4. A Fin-like sidewall modulated HEMT device based on transconductance compensation method according to claim 1, wherein said recess (61) is tapered in depth.
5. A Fin-like sidewall modulated HEMT device based on transconductance compensation method according to claim 1 further comprising: and the insulating layer (10) covers the side walls and the bottoms of the grooves (61), the side walls and the bottoms of the gate grooves (71) and the surface of the passivation layer (7).
6. A Fin-like sidewall modulated HEMT device based on transconductance compensation method according to claim 5, characterized in that the thickness of the insulating layer (10) is 2-10 nm.
7. A preparation method of a HEMT device modulated by a Fin-like side wall based on a transconductance compensation method is characterized by comprising the following steps:
s1, sequentially growing an insertion layer (2), a buffer layer (3) and a barrier layer (6) on the substrate layer (1);
s2, preparing a source electrode (4) at one end of the buffer layer (3), and preparing a drain electrode (5) at the other end of the buffer layer (3);
s3, growing a passivation layer (7) on the barrier layer (6), the source electrode (4) and the drain electrode (5);
s4, etching the passivation layer (7) between the source electrode (4) and the drain electrode (5) along the gate width direction to form a gate groove (71) penetrating through the passivation layer (7);
s5, etching the barrier layer (6) in the gate groove (71) to form a plurality of grooves (61) arranged along the width direction of the gate;
s6, depositing gate metal in the grooves (61), the gate groove (71) and the passivation layer (7) to form a gate electrode (8);
s7, preparing a metal interconnection layer (9) of the source electrode (4) and the drain electrode (5) in the passivation layer (7).
8. The method for preparing a Fin-like sidewall modulated HEMT device based on the transconductance compensation method as claimed in claim 7, wherein the step S5 comprises:
s51, photoetching array groove areas on the barrier layer (6) to enable the array groove areas to be arranged periodically along the gate width direction;
s52, removing the barrier layer (6) in the groove area by utilizing an inductive coupling plasma etching process to form a plurality of grooves (61).
9. The method for preparing a Fin-like sidewall modulated HEMT device based on the transconductance compensation method as claimed in claim 7, wherein the step between the step S5 and the step S6 further comprises the steps of:
and X, growing an insulating layer (10) on the bottom and the side wall of the groove (61), the bottom and the side wall of the gate groove (71) and the surface of the passivation layer (7).
10. The preparation method of the Fin-like side wall modulated HEMT device based on the transconductance compensation method as claimed in claim 9, wherein the thickness of the insulating layer (10) is 2-10 nm.
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| CN111710650A (en) * | 2020-08-20 | 2020-09-25 | 浙江集迈科微电子有限公司 | GaN device based on double-channel gate and preparation method thereof |
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| CN113257890A (en) * | 2021-04-21 | 2021-08-13 | 厦门市三安集成电路有限公司 | High-linearity gallium nitride radio frequency device and manufacturing method thereof |
| TWI775648B (en) * | 2021-10-21 | 2022-08-21 | 力晶積成電子製造股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN116666219A (en) * | 2023-04-24 | 2023-08-29 | 遂宁合芯半导体有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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| CN111969055A (en) * | 2020-08-12 | 2020-11-20 | 无锡先仁智芯微电子技术有限公司 | GaN high electron mobility transistor structure and manufacturing method thereof |
| CN111710650A (en) * | 2020-08-20 | 2020-09-25 | 浙江集迈科微电子有限公司 | GaN device based on double-channel gate and preparation method thereof |
| CN112736127A (en) * | 2020-12-31 | 2021-04-30 | 厦门市三安集成电路有限公司 | Gallium nitride-based HEMT radio frequency device and manufacturing method thereof |
| CN112736129A (en) * | 2020-12-31 | 2021-04-30 | 厦门市三安集成电路有限公司 | Nitride HEMT radio frequency device and manufacturing method thereof |
| CN113113483B (en) * | 2021-03-15 | 2022-10-21 | 厦门市三安集成电路有限公司 | HEMT radio frequency device and manufacturing method thereof |
| CN113113483A (en) * | 2021-03-15 | 2021-07-13 | 厦门市三安集成电路有限公司 | HEMT radio frequency device and manufacturing method thereof |
| CN113113313A (en) * | 2021-03-15 | 2021-07-13 | 厦门市三安集成电路有限公司 | HEMT device and manufacturing method thereof |
| CN113257890A (en) * | 2021-04-21 | 2021-08-13 | 厦门市三安集成电路有限公司 | High-linearity gallium nitride radio frequency device and manufacturing method thereof |
| CN113257890B (en) * | 2021-04-21 | 2022-07-22 | 厦门市三安集成电路有限公司 | High-linearity gallium nitride radio frequency device and manufacturing method thereof |
| CN113257891A (en) * | 2021-04-27 | 2021-08-13 | 厦门市三安集成电路有限公司 | High electron mobility transistor and manufacturing method thereof |
| CN113257891B (en) * | 2021-04-27 | 2022-07-26 | 厦门市三安集成电路有限公司 | High electron mobility transistor and manufacturing method thereof |
| TWI775648B (en) * | 2021-10-21 | 2022-08-21 | 力晶積成電子製造股份有限公司 | Semiconductor device and method for manufacturing the same |
| WO2023237001A1 (en) * | 2022-06-09 | 2023-12-14 | 华为技术有限公司 | Semiconductor device and electronic equipment |
| CN116666219A (en) * | 2023-04-24 | 2023-08-29 | 遂宁合芯半导体有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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