CN111969055A - GaN high electron mobility transistor structure and manufacturing method thereof - Google Patents
GaN high electron mobility transistor structure and manufacturing method thereof Download PDFInfo
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- 238000005530 etching Methods 0.000 claims description 18
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- 238000000034 method Methods 0.000 claims description 6
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- 230000005684 electric field Effects 0.000 abstract description 3
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention relates to the technical field of electronic part manufacturing, in particular to a GaN high electron mobility transistor structure and a manufacturing method thereof, aiming at solving the problem that the edge of a gate electrode is a sharp-angled structure in the prior art and has electric field concentration, thereby influencing the performance and reliability of the GaN high electron mobility transistor; a channel layer on the substrate; a barrier layer on the channel layer; a source, a drain, and a gate on the barrier layer, the gate being between the source and the drain; the dielectric layer is positioned between the grid electrode and the barrier layer; and a groove is formed on the dielectric layer along the width direction of the gate, and the edge of the groove corresponding to the gate is a round angle. According to the invention, the stress concentration effect of the gate edge is solved by removing the sharp corner at the gate edge, so that the breakdown voltage of the GaN high electron mobility transistor and the performance of the high electron mobility transistor are further improved.
Description
Technical Field
The invention relates to the technical field of electronic part manufacturing, in particular to a GaN high-electron-mobility transistor structure and a manufacturing method thereof.
Background
Today, power electronics represented by silicon-based occupy the mainstream consumer market. However, with the continuous development of technology, the potential of Si materials in achieving higher withstand voltage, lower on-resistance and higher switching speed has been explored. The forbidden band width of GaN is about 3 times of that of Si, the critical breakdown field strength is 1 order of magnitude higher than that of Si, and the electron mobility and the thermal conductivity are better, so that the GaN-based high electron mobility transistor has remarkable advantages in high-voltage, large-current, high-frequency and high-temperature working occasions such as power conversion, microwave communication and the like. A large number of researchers have proposed various structures for solving the key problem of GaN high electron mobility transistors, and one of them is shown in fig. 1, which adds SiN under the Gate to suppress the Gate leakage current and increase the threshold voltage. Although this solution can solve the above problem, the present inventors have found that since the Gate edge is still in a "sharp corner" structure, there is a problem of electric field concentration, which affects the performance and reliability of the GaN high electron mobility transistor.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the problem of electric field concentration in the prior art in which the edge of the gate electrode is a sharp-angled structure, which may affect the performance and reliability of the GaN high electron mobility transistor, and to provide a GaN high electron mobility transistor structure and a method for manufacturing the same.
A first aspect of the present invention provides a GaN high electron mobility transistor structure, including:
a substrate;
a channel layer on the substrate;
a barrier layer on the channel layer;
a source, a drain, and a gate on the barrier layer, the gate being between the source and the drain;
the dielectric layer is positioned between the grid electrode and the barrier layer;
and a groove is formed on the dielectric layer at least along the length direction of the gate, and the edge of the groove corresponding to the gate is a round angle.
Optionally, the dielectric layer is an SiO layer.
Optionally, the dielectric layer includes SiN layers adjacent to the gate and the barrier layer, and a SiO layer is interposed between the SiN layers.
Optionally, the channel layer is a GaN layer.
Optionally, the barrier layer is an Al-GaN layer.
Optionally, the carrier concentration in the channel layer is not a fixed value in the gate width direction and does not change monotonically.
Optionally, the GaN hemt device is a multi-gate finger structure and the single gate finger width is greater than or equal to 100 μm.
Optionally, the carrier concentration in the channel layer varies periodically along the gate width direction.
Optionally, ions with different doses are implanted in the channel layer along the gate width direction.
The second scheme of the invention provides a manufacturing method based on the GaN high electron mobility transistor structure, which comprises the following steps:
s1, providing a substrate;
s2, forming a channel layer on the substrate;
s3, forming a barrier layer on the channel layer;
s4, forming a dielectric layer on the barrier layer;
s5, etching partial area of the dielectric layer to obtain a groove;
s6, carrying out secondary etching on the groove to smooth a sharp corner;
and S7, forming a grid electrode on the groove, and forming a source electrode and a drain electrode on the barrier layer at two sides of the grid electrode.
According to the scheme, the sharp corners at the edges of the grid are removed, so that the stress concentration effect at the edges of the grid is solved, and the breakdown voltage of the GaN high electron mobility transistor and the performance of the high electron mobility transistor are further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a prior art structure;
fig. 2 is a schematic structural view of a GaN hemt structure according to embodiment 1 of the present invention;
fig. 3A-3B are schematic views of the edge of the gate 6 before and after the trench 8 is formed according to embodiment 1 of the present invention;
FIG. 4 is a schematic diagram of a GaN HEMT device with multi-gate finger structure;
FIG. 5 is a schematic view of the periodic distribution of the depth of the trenches 8;
fig. 6 is a schematic structural view of a GaN hemt structure according to embodiment 2 of the present invention;
FIG. 7 is a flowchart of a method for fabricating a GaN HEMT structure according to embodiment 3 of the invention;
fig. 8 is a flowchart of a method for fabricating a GaN hemt structure according to embodiment 4 of the present invention.
Description of reference numerals:
1. a substrate; 2. a channel layer; 3. a barrier layer; 4. a source electrode; 5. a drain electrode; 6. a gate electrode; 7. a dielectric layer; 8. and (4) a groove.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1:
a GaN high electron mobility transistor structure is shown in FIG. 2, and includes a substrate 1, wherein the substrate 1 may be made of gallium nitride, silicon, sapphire, silicon carbide, aluminum nitride or other semiconductor materials; a channel layer 2 grows on the substrate 1, and the material of the channel layer 2 can be GaN; a barrier layer 3 is grown on the channel layer 2, and the material of the barrier layer 3 can be Al-GaN; a source electrode 4, a drain electrode 5 and a grid electrode 6 are grown on the barrier layer 3, wherein the grid electrode 6 is positioned between the source electrode 4 and the drain electrode 5, the source electrode 4, the drain electrode 5 and the grid electrode 6 are preferably a single-layer metal or a multilayer metal lamination, and the metal material can be any one or combination of more of Ti, Al, Ni, Au or Mo; a dielectric layer 7 grows between the grid electrode 6 and the barrier layer 3, a groove 8 is formed on the dielectric layer 7 at least along the grid length direction, and the edge of the groove 8 corresponding to the grid electrode 6 is a round angle.
In this embodiment of the present invention, as shown in fig. 2, the dielectric layer 7 is a SiO layer. The trench 8 may be formed along the gate length direction, the gate width direction, or both the gate length and the gate width direction. Fig. 3A-3B show schematic views of the edges of the gate 6 before and after the trench 8 is formed, and the trench 8 rounds the edges of the gate 6 to solve the stress concentration effect caused by sharp corners.
As shown in fig. 2, the channel layer 2 provides a channel for carrier movement, the barrier layer 3 supplies carriers to the channel layer 2 and blocks the carriers in the channel layer 2 from flowing to the barrier layer 3, specifically, the carrier concentration in the channel layer 2 is a non-fixed value along the gate length or the gate width direction and changes non-monotonically, and since the carrier concentration is not fixed and changes non-monotonically, the high electron mobility transistor device can be equivalent to a parallel connection of a plurality of different threshold voltage transistor devices, and the transconductance curve thereof becomes flat and is more beneficial to heat dissipation, thereby achieving the purposes of improving the linearity of the device and improving the reliability.
Taking the gate length as an example, the GaN hemt device has a multi-gate finger structure shown in fig. 4, and the length of a single gate finger is greater than or equal to 100 μm. For a device with a gate length of more than or equal to 100 μm, if the carrier concentration changes monotonically (monotonically increasing or monotonically decreasing) along the gate length direction, the current borne by the channel at the edge along the gate length direction is the largest and the temperature is the highest when the device is in operation, so that the device is more prone to failure. In order to solve the above problem, in this embodiment, the etching depth of the trench along the gate length direction is periodically changed, as shown in fig. 5, the carrier concentration in the corresponding channel layer below the gate electrode is periodically changed along the gate length direction, and such distribution causes current distribution to be dispersed along the gate length direction, so that heat dissipation is easier, and reliability of the device is higher. Ions with different doses are injected into the channel layer 2 along the length direction of the gate, so that the concentration of carriers in the range below the gate is controlled by a grooving or ion injection technology, specifically, the grooves with periodically changed etching depths can be used for injection, the positions with large etching depths are used for injecting ions with large concentration or dose into the channel layer 2, the positions with small etching depths are used for injecting ions with small concentration or dose into the channel layer 2, so that a transconductance curve is flattened, a high-electron-mobility transistor device can be equivalent to the parallel connection of a plurality of different threshold voltage transistor devices, the purpose of improving linearity is achieved, heat dissipation is easier, and high reliability is realized.
Example 2:
a GaN high electron mobility transistor structure is shown in FIG. 6, and includes a substrate 1, where the material of the substrate 1 may be gallium nitride, silicon, sapphire, silicon carbide, aluminum nitride or other semiconductor materials; a channel layer 2 grows on the substrate 1, and the material of the channel layer 2 can be GaN; a barrier layer 3 is grown on the channel layer 2, and the material of the barrier layer 3 can be Al-GaN; a source electrode 4, a drain electrode 5 and a grid electrode 6 are grown on the barrier layer 3, wherein the grid electrode 6 is positioned between the source electrode 4 and the drain electrode 5, the source electrode 4, the drain electrode 5 and the grid electrode 6 are preferably a single-layer metal or a multilayer metal lamination, and the metal material can be any one or combination of more of Ti, Al, Ni, Au or Mo; a dielectric layer 7 grows between the grid electrode 6 and the barrier layer 3, a groove 8 is formed on the dielectric layer 7 at least along the grid length direction, and the edge of the groove 8 corresponding to the grid electrode 6 is a round angle.
In this embodiment of the present invention, as shown in fig. 6, the dielectric layer 7 includes SiN layers adjacent to the gate 6 and the barrier layer 3, and a SiO layer is interposed between the SiN layers. Since SiN has good temperature stability, it is more preferable to use a SiN-SiO stacked structure because it also repairs N vacancies in GaN or Al-GaN.
As shown in fig. 6, the channel layer 2 provides a channel for carrier movement, the barrier layer 3 supplies carriers to the channel layer 2 and blocks the carriers in the channel layer 2 from flowing to the barrier layer 3, specifically, the carrier concentration in the channel layer 2 is a non-fixed value and non-monotonic change along the gate length or the gate width direction, and since the carrier concentration is not fixed and non-monotonic change, the high electron mobility transistor device can be equivalent to a parallel connection of a plurality of different threshold voltage transistor devices, and the transconductance curve thereof becomes flat and is more beneficial to heat dissipation, thereby achieving the purposes of improving the linearity of the device and improving the reliability.
Taking the gate length as an example, the GaN hemt device has a multi-finger structure, and the length of a single finger is greater than or equal to 100 μm. For a device with a gate length of more than or equal to 100 μm, if the carrier concentration changes monotonically (monotonically increasing or monotonically decreasing) along the gate length direction, the current borne by the channel at the edge along the gate length direction is the largest and the temperature is the highest when the device is in operation, so that the device is more prone to failure. In order to solve the above problem, in this embodiment, the etching depth of the trench along the gate length direction is periodically changed, and the carrier concentration in the corresponding trench layer below the gate electrode is periodically changed along the gate length direction, so that the current distribution along the gate length direction is dispersed, heat dissipation is easier, and the reliability of the device is higher. Ions with different doses are injected into the channel layer 2 along the length direction of the gate, so that the concentration of carriers in the range below the gate is controlled by a grooving or ion injection technology, specifically, the grooves with periodically changed etching depths can be used for injection, the positions with large etching depths are used for injecting ions with large concentration or dose into the channel layer 2, the positions with small etching depths are used for injecting ions with small concentration or dose into the channel layer 2, so that a transconductance curve is flattened, a high-electron-mobility transistor device can be equivalent to the parallel connection of a plurality of different threshold voltage transistor devices, the purpose of improving linearity is achieved, heat dissipation is easier, and high reliability is realized.
Example 3:
a method for fabricating a GaN high electron mobility transistor structure, as shown in fig. 7, includes the following steps:
s1, a substrate 1 is provided.
The substrate 1 may be sapphire, silicon carbide, silicon, lithium niobate, silicon on insulator, gallium nitride, or aluminum nitride, or a combination of any two or more of these.
S2, the channel layer 2 is formed on the substrate 1.
The channel layer 2 provides a channel for carrier movement, and in this embodiment of the invention, the channel layer 2 is unintentionally doped GaN.
S3, the barrier layer 3 is formed on the channel layer 2.
The barrier layer 3 acts as a barrier to block carriers in the channel layer 2 from flowing to the barrier layer 3, and in this embodiment of the present invention, the barrier layer 3 is unintentionally doped Al — GaN.
And S4, forming a dielectric layer 7 on the barrier layer 3, wherein the dielectric layer 7 is an SiO layer.
And S5, etching partial area of the SiO layer, and removing the mask to obtain the groove 8.
Wherein the depth distribution of the trench 8 is consistent with the concentration or dose distribution of ions in the channel layer 2, that is, the concentration or dose of ions implanted into the channel layer 2 is large at a position where the depth of the trench 8 is large, and the concentration or dose of ions implanted into the channel layer 2 is small at a position where the depth of the trench 8 is small.
S6, performing a second etching on the trench 8 to round sharp corners.
S7, a gate 6 is formed on the trench 8, and a source electrode 4 and a drain electrode 5 are formed on both sides of the gate 6 and on the barrier layer 3.
According to the scheme, the groove is formed below the grid electrode, the channel layer is injected by means of the periodic distribution of the depth of the groove, a channel for carrier movement is formed in the channel layer, the sharp corners at the edge of the grid electrode are removed through secondary etching of the groove, the stress concentration effect at the edge of the grid electrode is solved, the flat transconductance curve is obtained, and therefore the breakdown voltage of the GaN high electron mobility transistor and the performance of the high electron mobility transistor are further improved.
Example 4:
a method for fabricating a GaN high electron mobility transistor structure, as shown in fig. 8, includes the following steps:
s1, a substrate 1 is provided.
The substrate 1 may be sapphire, silicon carbide, silicon, lithium niobate, silicon on insulator, gallium nitride, or aluminum nitride, or a combination of any two or more of these.
S2, the channel layer 2 is formed on the substrate 1.
The channel layer 2 provides a channel for carrier movement, and in this embodiment of the invention, the channel layer 2 is unintentionally doped GaN.
S3, the barrier layer 3 is formed on the channel layer 2.
The barrier layer 3 acts as a barrier to block carriers in the channel layer 2 from flowing to the barrier layer 3, and in this embodiment of the present invention, the barrier layer 3 is unintentionally doped Al — GaN.
And S4, forming a dielectric layer 7 on the barrier layer 3.
The dielectric layer 7 is a SiN-SiO lamination layer, wherein the SiN layer is close to one side of the barrier layer 3.
And S5, doping partial area of the SiO layer by ion implantation, and obtaining the groove 8 by etching or etching the doped area and removing the mask.
S6, performing a second etching on the trench 8 to round sharp corners.
And S7, forming a SiN layer close to the grid on the SiO layer.
S8, a gate 6 is formed on the trench 8, and a source electrode 4 and a drain electrode 5 are formed on both sides of the gate 6 and on the barrier layer 3.
According to the scheme, the sharp corners at the edges of the grid are removed, so that the stress concentration effect at the edges of the grid is solved, and the breakdown voltage of the GaN high electron mobility transistor and the performance of the high electron mobility transistor are further improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A GaN hemt structure, comprising:
a substrate (1);
a channel layer (2) on the substrate (1);
a barrier layer (3) on the channel layer (2);
a source (4), a drain (5), and a gate (6) on the barrier layer (3), the gate (6) being located between the source (4) and the drain (5);
a dielectric layer (7) positioned between the gate (6) and the barrier layer (3);
and a groove (8) is formed in the dielectric layer (7) at least along the length direction of the gate, and the edge of the groove (8) corresponding to the gate (6) is a round angle.
2. The GaN hemt of claim 1, wherein said dielectric layer (7) is a SiO layer.
3. The GaN hemt structure of claim 1, wherein said dielectric layer (7) comprises SiN layers adjacent to said gate (6) and said barrier layer (3), with a SiO layer sandwiched therebetween.
4. A GaN hemt structure according to claim 1, wherein said channel layer (2) is a GaN layer.
5. A GaN hemt structure according to claim 1, wherein said barrier layer (3) is an Al-GaN layer.
6. A GaN hemt structure according to claim 1, wherein the carrier concentration in said channel layer (2) is a non-constant value in the gate width direction and varies non-monotonically.
7. The GaN hemt structure of claim 6, wherein said GaN hemt device is a multi-finger structure and the single finger width is greater than or equal to 100 μm.
8. A GaN HEMT structure according to claim 7, wherein the carrier concentration in the channel layer (2) varies periodically along the gate width.
9. A GaN hemt structure according to claim 8, wherein said channel layer (2) is implanted with ions of different doses in the gate width direction.
10. A method for fabricating a GaN hemt structure according to claims 1-9, comprising the steps of:
s1, providing a substrate (1);
s2, forming a channel layer (2) on the substrate (1);
s3, forming a barrier layer (3) on the channel layer (2);
s4, forming a dielectric layer (7) on the barrier layer (3);
s5, etching partial area of the dielectric layer (7) to obtain a groove (8);
s6, carrying out secondary etching on the groove (8) to smooth a sharp corner;
and S7, forming a gate (6) on the groove (8), and forming a source electrode (4) and a drain electrode (5) which are positioned on the barrier layer (3) on two sides of the gate (6).
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| CN112509917A (en) * | 2021-01-29 | 2021-03-16 | 度亘激光技术（苏州）有限公司 | Semiconductor structure preparation method and semiconductor structure |
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| 罗永伦，李滨编著: "《微波集成电路的设计》", 30 September 2014, 国防工业出版社, pages: 211 - 212 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112509917A (en) * | 2021-01-29 | 2021-03-16 | 度亘激光技术（苏州）有限公司 | Semiconductor structure preparation method and semiconductor structure |
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