WO2018103606A1

WO2018103606A1 - Gan fin-typed transistor having high linearity and high electron mobility, and manufacturing method thereof

Info

Publication number: WO2018103606A1
Application number: PCT/CN2017/114456
Authority: WO
Inventors: 张凯; 孔月婵; 周建军; 陈堂胜
Original assignee: 中国电子科技集团公司第五十五研究所
Priority date: 2016-12-08
Filing date: 2017-12-04
Publication date: 2018-06-14
Also published as: CN106684141A

Abstract

A GaN fin-typed transistor having high linearity and high electron mobility, and a manufacturing method thereof. The transistor has a structure comprising, from the bottom to the top: a substrate (1), a buffer layer (2), a depletion layer (3), and a passivation layer (6). A source electrode (4) is disposed above one end of the depletion layer, and a drain electrode (5) is disposed above the other end of the depletion layer. The passivation layer is disposed above the depletion layer between the source electrode and the drain electrode. A recess (7) is provided at the passivation layer and contains a T-shaped grating (9) disposed therein. The passivation layer is characterized in that: GaN-based three-dimensional fins (8) are etched on the buffer layer and the depletion layer limited only in a region below the recess and have a periodic arrangement; the GaN-based three-dimensional fins have lengths identical to that of the recess; and an isolation recess is formed by etching and provided between the GaN-based three-dimensional fins. The device has high linearity and a high output current, strong gate control, favorable heat dissipation performance, and a high frequency characteristic. The manufacturing method thereof is simple and reliable, and suitable for a large-power highly-linear microwave power device.

Description

GaN fin type high electron mobility transistor with high linearity and manufacturing method thereof

Technical field

The invention belongs to the technical field of semiconductor device fabrication, and in particular to a GaN fin high electron mobility transistor with high linearity and a manufacturing method thereof.

technical background

The third-generation semiconductor GaN-based high electron mobility transistor (HEMT) has the characteristics of high output power density, high efficiency, high temperature resistance, and radiation resistance. It has become a mainstream technology for manufacturing high-frequency, high-efficiency, high-power electronic devices. The performance of weapons and equipment represented by radar has increased. With the urgent need for high-linearity transistors for high-data-stream satellite communications and modern wireless communications applications such as 5G communications, high-linear devices are now a key development direction in the GaN field. High linearity will result in more efficient spectrum utilization and reduce the need for linearization modules, further increasing the efficiency and integration of the entire system.

The transconductance of the conventional GaN planar structure exhibits a typical peak characteristic, that is, the transconductance is severely degraded at a high current, resulting in rapid compression of the device gain at high input power, poor intermodulation characteristics, and low linearity. In order to overcome this shortcoming, in 2005, the Hong Kong University of Science and Technology proposed the Al _0.05 Ga _0.95 N/GaN composite channel, which improved the cross-wire property to some extent by reducing the longitudinal electric field of the channel (see document Jie Liu et al., Highly Linear). Al _0.3 Ga _0.7 N–Al _0.05 Ga _0.95 N–GaN Composite-Channel HEMTs, IEEE Electron Device Lett., vol. 26, no. 3, pp. 145-147, 2005). Subsequently, North Carolina State University found that nonlinear source resistance caused by space charge current limiting is a major factor limiting the linearity of GaN devices (see Robert J. Trew et al., Nonlinear Source Resistance in High-Voltage Microwave AlGaN/). GaN HFETs, IEEE Trans. Microw. Theory Tech., vol. 54, no. 5, pp. 2061-2067, 2006). Therefore, the composite channel structure is very limited in improving the linearity, and the channel thermal resistance is increased, and the output power, frequency, efficiency and the like of the device are significantly degraded.

GaN FinFET (or three-dimensional fin structure) has recently been closely watched by domestic and foreign research institutions. It has enhanced the control of channel electrons by introducing additional side gates on both sides of the channel, which is better than traditional structures. Subthreshold characteristics, off-state characteristics, and short-channel effects are also greatly suppressed (see Kota Ohi et al., Current Stability in Multi-Mesa-Channel AlGaN/GaN HEMTs, IEEE Trans. Electron Devices., vol. 60, No.10, pp. 2997-3004, 2013). Subsequently, MIT reported GaN FinFET devices with high transconductance and f _T linearity (see literature Kota Ohi Dong Seup Lee et al., Nanowire Channel InAlN/GaN HEMTs With High Linearity of g _m and f _T , IEEE Electron Devices. , vol. 34, no. 8, pp. 969-971, 2013), and pointed out that the fundamental reason for the high linearity of transconductance is that the three-dimensional fins are completely wrapped by the gate metal. However, in order to achieve this, the fins are prepared in a self-aligned manner, the process is complicated, and the process compatibility with the conventional GaN device is poor; most importantly, the gate electrode of the device prepared by this process is a straight gate structure, and the gate resistance is large. The resulting high oscillation frequency is low, which ultimately limits its application in microwave power circuits.

The Chinese patent application discloses a multi-channel fin structure AlGaN/GaN high electron mobility transistor structure and fabrication method, which mainly solves the problems of poor gate control capability and low current of FinFET devices in the existing multi-channel devices. The structure of the device includes a substrate (1), a first AlGaN/GaN heterojunction (2), a SiN passivation layer (4), and a source/drain gate electrode in this order from bottom to top, and the source and drain electrodes are respectively located in the SiN. A top layer of the AlGaN barrier layer on both sides of the passivation layer, wherein: a first layer of AlGaN/GaN heterojunction and a SiN passivation layer are provided with a GaN layer and an AlGaN barrier layer to form a second layer of AlGaN/GaN heterojunction (3); the gate electrode covers the top of the second layer heterojunction and the two sidewalls of the first layer and the second layer heterojunction. The device has strong gate control capability, large saturation current and good subthreshold characteristics, and can be used for low power consumption and low noise microwave power devices with short gate length.

The Chinese patent application discloses a T-gate N-plane GaN/AlGaN fin type high electron mobility transistor, which mainly solves the problems of low oscillation frequency, large ohmic contact resistance and serious short channel effect of the existing microwave power device. The structure of the device from bottom to top includes: substrate (1), GaN buffer layer (2), AlGaN barrier layer (3), GaN channel layer (4), gate dielectric layer (5), passivation layer ( 6) and source, drain, and gate electrodes, wherein the buffer layer and the channel layer are N-plane GaN materials; the GaN channel layer and the AlGaN barrier layer constitute a GaN/AlGaN heterojunction; the gate electrode is a T-gate and is wrapped A three-dimensional grid structure is formed on both sides and above the GaN/AlGaN heterojunction. The device has the advantages of good gate control capability, small ohmic contact resistance and high maximum oscillation frequency, and can be used as a small-sized microwave power device.

Although the above two solutions solve the problems of GaN multi-channel and N-plane structures respectively, there are still obvious deficiencies: mainly adopting the traditional GaN-based fin structure and preparation method, that is, first preparing GaN-based three-dimensional fins and then preparing concave The groove, the three-dimensional fin is located in the groove, and is located outside the groove, as shown in FIG. 1 of the “N-face GaN-based high electron mobility transistor and manufacturing method”. Studies have shown that the three-dimensional fins are completely covered by the gate metal is the key to the high linearity of the device transconductance, and the above two solutions can not meet this requirement, therefore, the existing devices do not have high transconductance and high linearity.

How to overcome the shortcomings of the prior art has become one of the key problems to be solved in the field of semiconductor device fabrication technology.

Summary of the invention

The object of the present invention is to provide a GaN fin type high electron mobility transistor with high linearity and a manufacturing method thereof, which overcomes the deficiencies of the prior art, and the present invention has a high manufacturing process with a simplified manufacturing process. Linearity and maximum oscillation frequency can meet the application needs of GaN high linearity microwave power devices.

A GaN fin type high electron mobility transistor having high linearity according to the present invention, the structure of the transistor including a substrate, a buffer layer, a barrier layer, and a passivation layer in order from bottom to top; the barrier layer The upper end is provided with a source and the other end is provided with a drain; a barrier layer is disposed above the barrier layer between the source and the drain, and the passivation layer is provided with a groove, the concave A T-type gate is disposed in the trench, and is characterized in that the barrier layer and the buffer layer in the region below the recess are etched with periodically arranged GaN-based three-dimensional fins, the GaN-based three-dimensional fins The length is equal to the length of the groove, and an isolation trench formed by etching is provided between adjacent GaN-based three-dimensional fins.

A further preferred embodiment of the GaN fin high electron mobility transistor with high linearity proposed by the present invention is:

The GaN-based three-dimensional fins (8) have a height of 10 to 300 nm and a width of 10 to 1000 nm.

A portion of the T-type gate (9) covers both sides above the GaN-based three-dimensional fin (8), and another portion of the T-type gate (9) covers an adjacent GaN-based three-dimensional fin (8) Above the isolation trench, a further portion of the T-gate (9) overlies the passivation layer (6).

The invention provides a GaN fin type high electron mobility transistor with high linearity and a preparation method of the preferred solution, which comprises the following specific steps:

1) sequentially growing a buffer layer and a barrier layer on the substrate;

2) etching a source/drain pattern on the barrier layer, depositing a source/drain metal, and then performing thermal annealing in an N ₂ atmosphere to separately form a source and a drain;

3) depositing a passivation layer on the barrier layer;

4) forming an active region mask on the passivation layer, and then performing isolation by means of etching or ion implantation to form an active region;

5) forming a gate mask on the passivation layer, and then etching the passivation layer by RIE, ICP, etc. to form a recess;

6) defining a GaN-based three-dimensional fin mask on the barrier layer only in the region below the recess, and then dry etching the barrier layer and the buffer layer to form a periodically arranged GaN-based three-dimensional fin;

7) defining a gate cap mask on the passivation layer, depositing a gate metal by evaporation or sputtering, and stripping to form a T-type gate;

8) defining an interconnect opening area mask on the passivation layer, and etching to form interconnect openings;

9) defining an interconnect metal region mask on the passivation layer to form a interconnect metal by an evaporation and lift-off process.

Implementation principle of the present invention: The present invention is based on the existing GaN groove gate device manufacturing process. After the passivation layer is opened, a fin photolithography mask is formed inside the groove, and then a GaN group is formed by etching. Three-dimensional fins, and finally the T-gate is completely wrapped around the GaN-based three-dimensional fins. The preparation process of the present invention can reliably ensure that the GaN-based three-dimensional fin is limited to the underside of the groove and completely covered by the gate, and the other regions have no three-dimensional fins, so according to the transconductance high linearity principle, the linearity of the device of the present invention is high due to Using the same T-gate as the conventional process, the gate resistance is small, so the highest oscillation frequency of the device is high.

The significant advantages of the present invention over the prior art are:

1. The process of the present invention is simple and reliable, and the object of the present invention can be achieved by adding a one-step fin preparation process based on the existing GaN groove gate process.

2. The device of the invention adopts a T-gate structure, which not only has high linearity, but also has the highest oscillation frequency, and can meet the requirements of the microwave power circuit.

3. The device of the present invention has higher current driving capability and output power capability because the degradation of the transconductance under high gate voltage is suppressed;

4. Since the GaN-based three-dimensional fins provide auxiliary sidewall heat dissipation, the device of the present invention has low thermal resistance and is suitable for high power and high linearity microwave power devices.

DRAWINGS

1 is a schematic view showing a three-dimensional structure of a GaN fin type high electron mobility transistor having high linearity according to the present invention.

2 includes FIG. 2a, FIG. 2b, FIG. 2c, FIG. 2d, FIG. 2e, FIG. 2f, and FIG. 2g, which are one of the present invention. A schematic diagram of a manufacturing process for a GaN fin high electron mobility transistor having high linearity.

3 is a schematic diagram of DC transfer characteristics of a conventional GaN planar device.

4 is a schematic illustration of the DC transfer characteristics of a high linearity GaN fin device fabricated in accordance with the present invention.

detailed description

The specific embodiments of the present invention will be further described in detail below with reference to the drawings and embodiments.

Referring to FIG. 1, a GaN fin type high electron mobility transistor with high linearity proposed by the present invention is based on a group III nitride semiconductor, and has a structure including a substrate 1, a buffer layer 2, and a barrier layer 3 from bottom to top. a passivation layer 6; one end of the barrier layer 3 is provided with a source 4 and the other end is provided with a drain 5; and a barrier layer 3 between the source 4 and the drain 5 is provided with a passivation The layer 6 is provided with a recess 7 in the passivation layer 6 , and a T-shaped gate 9 is disposed in the recess 7 , and the barrier layer 3 and the buffer layer 2 are limited to the region below the recess 7 . There are a plurality of periodically arranged GaN-based three-dimensional fins 8 which are only present under the recesses 7 and have no fins in other regions. The length of the GaN-based three-dimensional fins 8 is The grooves 7 are of equal length, and an isolation trench formed by etching is provided between adjacent GaN-based three-dimensional fins. among them:

The GaN-based three-dimensional fin 8 has a height of 10 to 300 nm (including selection of 10 nm, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm, etc.) and a width of 10 to 1000 nm (including selection of 10 nm, 100 nm, 300 nm, 600 nm, or 1000 nm, etc.) Wherein the height of the GaN-based three-dimensional fin 8 is greater than the thickness of the barrier layer 3.

A portion of the T-shaped gate 9 covers both sides above the three-dimensional fin 8, and another portion of the T-shaped gate 9 covers the isolation trench between adjacent GaN-based three-dimensional fins 8, T-type A further portion of the gate 9 overlies the passivation layer 6.

Referring to FIG. 2, a method for fabricating a GaN fin high electron mobility transistor with high linearity according to the present invention includes the following specific steps:

1) sequentially growing a buffer layer 2 and a barrier layer 3 on the substrate 1, as shown in FIG. 2a; wherein: the substrate 1 is made of any one of sapphire, SiC, Si, diamond or GaN self-supporting substrates. The buffer layer 2 is one or a combination of GaN, AlGaN, AlN, and InGaN; and the barrier layer 3 is one or a combination of AlGaN, InAlN, InAlGaN, and AlN.

2) etching a source/drain pattern on the barrier layer 3, depositing a source/drain metal, and then performing thermal annealing in an N ₂ atmosphere to form a source 4 and a drain 5, respectively, as shown in FIG. 2b; The metals of the source 4 and the drain 5 include, but are not limited to, Ti/Al, Ti/Au, Ti/Al/W, Ti/Al/Mo/Au, Ti/Al/Ni/Au, Si/Ti. Any of the multilayer metals of /Al/Ni/Au, Ti/Al/TiN.

3) depositing a passivation layer 6 on the barrier layer 3, as shown in FIG. 2c; wherein: the material of the passivation layer 6 is one or a combination of SiN, SiO ₂ , SiON, AlN, and the thickness is 30 to 300 nm (including selection of 30 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, etc.), the growth method is plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or low pressure chemical vapor deposition ( LPCVD).

4) forming an active region mask on the passivation layer 6, and then performing isolation by means of etching or ion implantation to form an active region;

5) forming a gate mask on the passivation layer 6, and subsequently removing the passivation layer 6 by RIE, ICP or the like to form a recess 7, as shown in FIG. 2d;

6) defining a GaN-based three-dimensional fin mask on the barrier layer 3 limited only in the region below the recess 7, as shown in FIG. 2e, followed by dry etching the barrier layer 3 and the buffer layer 2 to form a periodic arrangement GaN-based three-dimensional fins 8, as shown in FIG. 2f; wherein: the GaN-based fin mask is fabricated by optical lithography or electron beam direct writing, and the barrier layer 3 and the buffer layer 2 are etched by dry methods such as RIE and ICP. Etching method

7) defining a gate cap mask on the passivation layer 6, depositing a gate metal by evaporation or sputtering, and stripping to form a T-type gate 9, as shown in FIG. 2g; wherein: the gate metal includes but is not limited to Ni/Au, Ni /Au/Ni, Pt/Au, Ni/Pt/Au, W/Ti/Au, Ni/Pt/Au/Pt/Ti, TiN/Ti/Al/Ti/TiN, any of the multilayer metals, The thickness of the gate metal is 50 to 700 nm (including selection of 50 nm, 100 nm, 300 nm, 500 nm or 700 nm, etc.).

8) defining a interconnection opening mask on the passivation layer 6 and etching to form interconnect openings;

9) An interconnect metal region mask is defined on the passivation layer 6, and a interconnect metal is formed by an evaporation and lift-off process.

According to the structure and manufacturing method of the present invention described above, the present invention provides the following two embodiments, but is not limited to these embodiments.

Example 1: Preparation of SiC substrate, buffer layer is AlN/GaN, barrier layer is AlGaN, passivation layer is SiN, GaN-based three-dimensional fin width is 100 nm, and gate metal is Ni/Au/Ni with high linearity Degree of GaN fin high electron mobility transistor, the process is:

1) on the SiC substrate 1, using metal organic chemical vapor deposition (MOCVD), first growing 100 nm of AlN at 1050 ° C, and then growing 2 μm of unintentionally doped GaN layer at 1000 ° C to form a buffer layer 2, Subsequently, an AlGaN barrier layer 3 having a thickness of 22 nm was grown on the buffer layer 2, and the Al composition was 30%.

2) forming a photolithographic mask on the barrier layer 3, then depositing the metal stack by electron beam evaporation, obtaining an isolated metal block at both ends thereof by a lift-off process, and finally performing rapid thermal annealing to form a source in a N ₂ atmosphere. Pole 4 and drain 5. The deposited metal is Ti, Al, Ni, and Au from bottom to top, and has thicknesses of 20 nm, 150 nm, 60 nm, and 50 nm, respectively. The conditions for electron beam evaporation are as follows: vacuum degree ≦ 2.0 × 10 ^-6 Torr, deposition rate is less than

The process conditions for rapid thermal annealing are: temperature 840 ° C, time 30 s.

3) using a PECVD technique to deposit SiN on the barrier layer 3 to form a passivation layer 6; the deposition process conditions are: SiH ₄ , NH ₃ , He and N ₂ , respectively, flow rates of 8 sccm, 2 sccm, 100 sccm, and 200 sccm, respectively. The pressure was 500 mTorr, the temperature was 260 ° C, the power was 25 W, and the thickness of the passivation layer was 100 nm.

4) An active region mask is formed on the passivation layer 6, and then device isolation is performed by ion implantation to form an active region. The implantation conditions were as follows: ion was B ⁺ , current was 10 μA, energy was 100 KeV, and dose was 5e14.

5) A mask is formed on the upper portion of the passivation layer 6, and a recess 7 is formed in the passivation layer 6 between the source 4 and the drain 5 by a plasma enhanced etching technique RIE. The process conditions for etching the groove are: gas is SF ₆ , flow rate is 20 sccm, pressure is 0.2 Pa, and time is 200 s.

6) Using ZEP520 glue to make a GaN-based three-dimensional fin mask inside the groove 7, dry etching AlGaN/GaN by ICP, removing the ZEP520 rubber mask, and forming a GaN-based three-dimensional fin 8 having a width of 100 nm; The etching conditions were as follows: gas was BCl ₃ and Cl ₂ respectively, flow rates were 25 sccm and 5 sccm, pressure was 30 mTorr, temperature was 25 ° C, upper electrode power was 100 W, lower electrode was 3 W, etching time was 5 minutes, and etching depth was 50 nm.

7) forming a gate mask on the upper portion of the passivation layer 6, depositing the metal stack by electron beam evaporation technology, and forming a T-type gate 9 by a lift-off process; wherein: the process condition for depositing the metal stack is: vacuum degree ≦1.5×10 ^-6 Torr, the deposition rate is less than

Wherein: the deposited metal stack is Ni, Au, Ni from bottom to top, and the thicknesses are 20 nm, 500 nm and 30 nm, respectively.

8) An interconnect opening area lithography mask is defined on the passivation layer 6, and interconnect openings are formed by RIE dry etching. The etching process conditions were as follows: the gas was SF ₆ , the flow rate was 20 sccm, the pressure was 0.2 Pa, and the time was 200 s.

9) An interconnect metal region mask is defined on the passivation layer 6, and a interconnect metal is formed by an evaporation and lift-off process. The process conditions for depositing the metal stack are: vacuum degree ≦1.5×10 ^-6 Torr, and the deposition rate is less than

The deposited metal stack was Ti and Au from bottom to top and had thicknesses of 30 nm and 500 nm, respectively.

Example 2: A Si substrate was prepared, the buffer layer was an AlN/AlGaN/GaN layer, the barrier layer was AlN/InAlN, the passivation layer was SiO ₂ , the GaN-based three-dimensional fin width was 400 nm, and the gate metal was TiN/Ti/ Al/Ti/TiN high-linearity GaN fin high electron mobility transistor, the process is:

1) On a Si substrate, a metal organic chemical vapor deposition technique MOCVD is used to grow 200 nm of AlN at 1050 ° C, and then grow a 1 μm unintentionally doped AlGaN layer (Al group 15%) at 1000 ° C and A 500 nm GaN layer was formed to form a buffer layer 2, and then an AlN layer having a thickness of 1 nm and 8 nm of InAlN were grown on the buffer layer 2 at 800 ° C to form a barrier layer 3 having an Al composition of 83%.

2) forming a photolithographic mask on the barrier layer 3, then depositing the metal stack by electron beam evaporation, obtaining an isolated metal block at both ends thereof by a lift-off process, and finally performing rapid thermal annealing to form a source in a N ₂ atmosphere. The electrode 4 and the drain 5; the deposited metal is Ti, Al and TiN from bottom to top, and the thickness thereof is 20 nm, 200 nm and 100 nm, respectively; the conditions for electron beam evaporation are: vacuum degree × 2.0 × 10 ^-6 Torr , the deposition rate is less than

The process conditions for rapid thermal annealing are: temperature 550 ° C, time 90 s.

3) A passivation layer 6 is formed by depositing SiO ₂ on the barrier layer 3 by a PECVD technique. The deposition process conditions were as follows: gas was SiH ₄ , N ₂ O, flow rate was 120 sccm, 200 sccm, pressure was 500 mTorr, temperature was 320 ° C, power was 35 W, and the thickness of the passivation layer was 150 nm.

4) The fourth step of the second embodiment is the same as the fourth step of the first embodiment.

5) forming a mask on the upper portion of the passivation layer 6, and using the plasma enhanced etching technique RIE to form a recess 7 on the passivation layer 6 between the source 4 and the drain 5; wherein: the process of etching the recess The conditions are: gas is SF ₆ , flow rate is 20sccm, pressure is 0.2pa, time is 600s.

6) A fin mask is formed inside the recess 7 by deep ultraviolet lithography, AlGaN/GaN is dry-etched by ICP, and the photoresist mask is removed to form a fin 8 having a width of 400 nm. Among them: the etching process conditions are: gas is BCl ₃ and Cl ₂ respectively, flow rate is 25sccm and 5sccm respectively, pressure is 30mTorr, temperature is 25°C, upper electrode power is 100W, lower electrode is 3W, etching time is 5 minutes, etching depth 50nm.

7) A gate mask is formed on the upper portion of the passivation layer 6, a metal laminate is deposited by electron beam evaporation, and a T-gate 9 is formed by a lift-off process. Wherein: the process conditions for depositing the metal stack are: vacuum degree ≦1.5×10 ^-6 Torr, and the deposition rate is less than

The deposited metal stack was TiN/Ti/Al/Ti/TiN from bottom to top and had thicknesses of 20 nm, 30 nm, 300 nm, 30 nm, and 100 nm, respectively.

8) defining a photolithographic mask of the interconnect opening region on the passivation layer 6, and forming an interconnect opening by RIE dry etching; wherein: the etching process condition is: the gas is SF ₆ , the flow rate is 20 sccm, and the pressure is 0.2 Pa. Time is 600s.

9) The ninth step of the second embodiment is the same as the ninth step of the first embodiment.

The effects of the present invention can be further illustrated by FIGS. 3 and 4.

Figure 3 shows the DC transfer characteristics of a GaN planar device. It can be seen that the device transconductance exhibits typical peak characteristics with a maximum current of 1.2 A/mm and a maximum transconductance G _m of 0.48 S/mm. 4 is a DC transfer characteristic of a high linearity GaN fin device prepared according to the present invention, the device transconductance G _m is flatter, the linearity is greatly improved, and the maximum current is 2 A/mm, and the maximum transconductance G _m is 0.74 S/mm. . As can be seen from the above comparison, the maximum current and transconductance values of the high linearity GaN fin device of the present invention are greatly improved compared with the planar device, and the cross-wire property is greatly improved.

Descriptions not mentioned in the Detailed Description of the Invention are well known in the art and can be implemented with reference to known techniques.

The invention has been verified by repeated experiments and has achieved satisfactory trial results.

The above specific embodiments and examples are specific support for the technical idea of a GaN fin type high electron mobility transistor with high linearity and a manufacturing method thereof, which are proposed by the present invention, and the scope of protection of the present invention cannot be limited thereto. Any equivalent changes or equivalent modifications made on the basis of the technical solutions of the present invention are still within the scope of protection of the technical solutions of the present invention.

Claims

A GaN fin type high electron mobility transistor having high linearity, the structure of the transistor including a substrate (1), a buffer layer (2), a barrier layer (3), and a passivation layer (7) in this order from bottom to top One end of the barrier layer (3) is provided with a source (4) and the other end is provided with a drain (5); a barrier between the source (4) and the drain (5) A passivation layer (6) is disposed above the layer (3), a recess (7) is disposed in the passivation layer (6), and a T-type gate (9) is disposed in the recess (7). The feature is that the barrier layer (3) and the buffer layer (2) in the region below the recess (7) are etched with periodically arranged GaN-based three-dimensional fins (8), the GaN-based The length of the three-dimensional fin (8) is equal to the length of the groove (7), and an isolation trench formed by etching is provided between adjacent GaN-based three-dimensional fins (8).
The GaN fin type high electron mobility transistor having high linearity according to claim 1, wherein the GaN-based three-dimensional fin (8) has a height of 10 to 300 nm and a width of 10 to 1000 nm.
A GaN fin type high electron mobility transistor having high linearity according to claim 2, wherein a part of said T-type gate (9) covers said GaN-based three-dimensional fin (8) On the upper side, another portion covers the isolation trench between adjacent GaN-based three-dimensional fins (8), and a further portion of the T-gate (9) overlies the passivation layer (6).
A method of fabricating a GaN fin high electron mobility transistor having high linearity according to any one of claims 1 to 3, comprising the following specific steps:

1) sequentially growing a buffer layer (2) and a barrier layer (3) on the substrate (1);

2) lithography of the source and drain patterns on the barrier layer (3), and deposition of source and drain metal, and then thermal annealing in N2 atmosphere, respectively, the source (4) and the drain (5);

3) depositing a passivation layer (6) on the barrier layer (3);

4) forming an active region mask on the passivation layer (6), and then performing device isolation by etching or ion implantation to form an active region;

5) forming a gate mask on the passivation layer (6), and then removing the passivation layer (6) by RIE, ICP etching to form a recess (7);

6) defining a GaN-based three-dimensional fin mask on the barrier layer (3) limited only in the region below the recess (7), followed by dry etching the barrier layer (3) and the buffer layer (2), Forming a periodically arranged GaN-based three-dimensional fin (8);

7) defining a gate cap mask on the passivation layer (6), depositing a gate metal by evaporation or sputtering, and stripping to form a T-type gate (9);

8) defining a interconnect opening area mask on the passivation layer (6), etching to form interconnect openings;

9) An interconnect metal region mask is defined on the passivation layer (6), and a interconnect metal is formed by an evaporation and lift-off process.
The method for fabricating a GaN fin type high electron mobility transistor having high linearity according to claim 4, wherein the substrate (1) is made of sapphire, SiC, Si, diamond. Or GaN self-supporting substrate Any one of the buffer layer (2) is one or a combination of GaN, AlGaN, AlN, InGaN; the barrier layer (3) is one or a combination of AlGaN, InAlN, InAlGaN, AlN .
The method for fabricating a GaN fin type high electron mobility transistor having high linearity according to claim 5, wherein the step 2) the metal of the source (4) and the drain (5) are both included Any of Ti/Al, Ti/Au, Ti/Al/W, Ti/Al/Mo/Au, Ti/Al/Ni/Au, Si/Ti/Al/Ni/Au, Ti/Al/TiN Multi-layer metal.
The method for fabricating a GaN fin type high electron mobility transistor having high linearity according to claim 6, wherein the material of the passivation layer (6) is SiN, SiO 2 , SiON One or several combinations of AlN, the passivation layer (6) has a thickness of 30 to 300 nm, and the passivation layer (6) is grown by plasma enhanced chemical vapor deposition, atomic layer deposition or low pressure. Chemical vapor deposition.
The method for fabricating a GaN fin type high electron mobility transistor having high linearity according to claim 7, wherein the step of the fin mask is performed by optical lithography or electron beam direct writing. The method is dry etching using RIE or ICP.
A method of fabricating a GaN fin type high electron mobility transistor having high linearity according to claim 8, wherein the step metal of the step 7) comprises Ni/Au, Ni/Au/Ni, Pt/ Any one of Au, Ni/Pt/Au, W/Ti/Au, Ni/Pt/Au/Pt/Ti, TiN/Ti/Al/Ti/TiN, the gate metal has a thickness of 50 ~700nm.