CN110098255B - Localized channel field effect transistor and preparation method thereof - Google Patents
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- CN110098255B CN110098255B CN201810144810.2A CN201810144810A CN110098255B CN 110098255 B CN110098255 B CN 110098255B CN 201810144810 A CN201810144810 A CN 201810144810A CN 110098255 B CN110098255 B CN 110098255B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 238000005530 etching Methods 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 33
- 230000005669 field effect Effects 0.000 claims abstract description 26
- 238000001259 photo etching Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 238000001311 chemical methods and process Methods 0.000 claims description 2
- 230000003321 amplification Effects 0.000 abstract description 8
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 8
- 238000000206 photolithography Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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Abstract
The invention discloses a field effect transistor of a localized channel and a preparation method thereof, wherein the transistor comprises a source electrode, a drain electrode and a grid electrode between the source electrode and the drain electrode, a channel well with a certain duty ratio is formed in a channel region covered by a grid pin in an etching way, and the channel well is filled with a medium; the channel wells are arranged at equal intervals along the extending direction of the channel, and the radial width of the channel wells is smaller than the length of the gate; the preparation method comprises the following steps: preparing a source electrode and a drain electrode; (2) Eliminating conductivity outside the active region and forming a channel well in the channel region; (3) Growing a medium on the surface of the device, and etching the medium in the gate pin and outside the channel well through an etching process; and (4) preparing a grid electrode. The invention can increase the equivalent conductive sectional area outside the channel of the field effect transistor, reduce the source and drain resistance of the field effect transistor, and relieve the limitation of the limited conductive capacity outside the channel on the channel current under the bias of the large forward gate; the gain and the linearity of the radio frequency amplification field effect transistor are improved; the minimum noise figure is reduced.
Description
Technical Field
The invention relates to a semiconductor device, in particular to a field effect transistor with a localized channel, and also relates to a preparation method of the field effect transistor.
Background
The radio frequency amplifying circuit based on the field effect transistors of Si, gaAs and GaN has important application in the wide fields of communication, navigation, identification, measurement and control, broadcast television, remote sensing and telemetering, radio astronomy, early warning detection, precise tracking, electronic countermeasure, fire control guidance and the like. In related applications such as 5G communication, millimeter wave amplification and the like, higher requirements are put forward on the linearity, the gain characteristic and the like of the device;
at present, the technology for improving the radio frequency amplification linearity of the field effect transistor mainly comprises aspects such as analog predistortion, digital predistortion, novel circuit structure design and novel device structure design; analog predistortion compensates for the nonlinearity of a radio frequency amplifier with the nonlinearity of a predistortion element by introducing a nonlinear predistortion element at the input of the radio frequency amplification device, such as a diode or diode network based linearizer; the digital predistortion principle is very similar to the channel coding in communication, and the input signal of the radio frequency amplification device is sampled and digitized, a compensation signal is generated under the control of the digital control module, and the compensation signal is sent to the radio frequency amplification device; examples of novel circuit structure designs include Doherty amplification circuits; the novel device structure design comprises a device semiconductor material design and a device longitudinal and transverse structure design. However, no method for improving the linearity and gain of the field effect transistor by the design of a novel device structure has appeared in the prior art.
Disclosure of Invention
The invention aims to: in view of the problems of the prior art, it is an object of the present invention to provide a field effect transistor with a localized channel that can improve gain and linearity and reduce the minimum noise figure, and to provide a method for fabricating the field effect transistor.
The technical scheme is as follows: a field effect transistor with a localized channel comprises a substrate, a buffer layer, a channel layer and a barrier layer, wherein the buffer layer and the channel layer are arranged above the substrate, the barrier layer is arranged above a channel region and the buffer layer, a source electrode and a drain electrode are respectively arranged at two ends above the barrier layer, a grid electrode is arranged between the source electrode and the drain electrode, a channel well with a certain duty ratio is formed in the channel region covered by a grid pin of the grid electrode through etching, and the channel well is filled with a medium; the channel wells are arranged at equal intervals along the extending direction of the channel, the radial width of the channel wells is less than the length of the gate, and the structure ensures that the conductive sectional area outside the channel is larger than the effective conductive sectional area of the channel; the duty cycle is determined by the longitudinal length of the well and the well-to-well spacing.
The field effect transistor is made of GaN HEMT, si or GaAs semiconductor material.
The channel well is rectangular, the depth is 10-100nm, the width is 20-500nm, and the dimension along the extending direction of the channel is 20-1000nm.
The preparation method of the field effect transistor comprises the following steps:
(1) Preparing a source electrode and a drain electrode on the surface of the semiconductor epitaxial material through photoetching, metallization and alloy processes;
(2) Eliminating the conductivity outside the active region through a physical and/or chemical process, and forming a channel well in the channel region;
(3) And growing a medium on the surface of the device, and etching the medium in the gate pin and outside the channel well through an etching process.
4) And completing the preparation of the grid electrode by photoetching a grid cap and a grid metallization process.
Preferably, in the step (2), the conductivity outside the active region is removed through a photolithography and plasma implantation process or a photolithography and etching process, and then a channel well is formed in the channel region through a photolithography and etching process.
The step (3) specifically comprises two steps: growing a medium on the surface of the device for the first time, filling the channel well with the medium after the medium is grown, etching the medium except the channel well through photoetching and etching processes, growing the medium again, and etching the gate feet through subsequent photoetching and etching processes, wherein the etching region comprises a channel well region. Preferably, the SiN dielectric is grown using PECVD.
Has the advantages that: compared with the prior art, the invention has the following remarkable progress: the equivalent conductive sectional area outside the channel of the field effect transistor can be increased, the source resistance and the drain resistance of the field effect transistor are reduced, and the limitation of the limited conductive capacity outside the channel on the channel current under the bias of the large forward gate is relieved; the gain and the linearity of the radio frequency amplification field effect transistor are improved; the minimum noise figure is reduced.
Drawings
FIGS. 1 (a) - (b) are top and cross-sectional views, respectively, of a GaN HEMT device structure;
FIGS. 2 (a) - (j) are schematic views of a GaN HEMT fabrication process with localized channel structures;
FIG. 3 is a schematic view of the carrier distribution in the active region of a localized channel structure GaN HEMT.
Detailed Description
The technical solution of the present invention is further described in detail with reference to the following examples and drawings.
In this embodiment, the field effect transistor is a GaN High Electron Mobility Transistor (HEMT), and a GaN HEMT structure of a localized channel structure is shown in fig. 1, where fig. 1 (a) is a top view of a device structure and fig. 1 (b) is a cross-sectional view of the device structure; 101 is a source electrode, 102 is a drain electrode, 103 is a grid electrode, 104 is a channel well, the channel well 104 is filled with a medium and covered by grid metal, 105 is an AlGaN barrier layer, 106 is a GaN channel and a buffer layer, and a substrate layer is not drawn in the figure; the localized channel field effect transistor structure provided by the invention is not limited to a GaN HEMT, and can be based on semiconductor materials such as Si, gaAs and the like; the localized channel structure GaN HEMT obviously increases the ratio of the equivalent conductive sectional area outside the channel to the channel sectional area (the ratio depends on the duty ratio of a channel well in the channel), and can achieve the effects of reducing the source resistance and the drain resistance of a field effect transistor, relieving the limitation of the limited conductive capacity outside the channel on the channel current under large forward gate bias, and improving the gain and the linearity of a device.
FIGS. 2 (a) -2 (j) are schematic diagrams of a GaN HEMT fabrication process with localized channel structures; the preparation process comprises the following steps: .
(1) First, a source electrode and a drain electrode are prepared on the surface of an epitaxial material through photolithography, metallization and alloying processes, and as shown in fig. 2 (a) and 2 (b), a top view and a cross-sectional view of a device structure are respectively shown.
(2) Then eliminating the conductivity outside the active region through two processes of photoetching and plasma implantation (or photoetching and etching), and forming a channel well in the channel region through photoetching and etching processes, wherein as shown in top views and cross sectional views shown in fig. 2 (c) and 2 (d), the channel well 104 is typically 10-100nm deep, the channel well is typically rectangular, the x-direction is typically 20-500nm (slightly less than the gate length), the y-direction is typically 20-1000nm, the size of the y-direction well and the space between the well and the well determine the duty ratio of the channel well in the channel; it should be noted that the channel well of the localized channel device structure introduced in the example of the present invention is realized by filling a medium after performing local etching on a channel to lose conductivity of the channel locally, and other physical and chemical methods are used to lose conductivity of the channel locally to realize the localized channel structure, which also belongs to the content of the present invention.
(4) Growing a medium on the surface of the device, wherein in this embodiment, a PECVD is used to grow a SiN medium with a size of 100nm, the trench well is filled with the medium after the medium is grown, and then the medium outside the trench well is etched by a photolithography and etching process to form the structures shown in fig. 2 (e) and 2 (f), wherein the trench well 104 is filled and covered by the medium; then growing the SiN medium again by 100nm, and performing gate foot etching (the etching region comprises a channel well region) by subsequent photoetching and etching processes, wherein the etched structure is shown in fig. 2 (g) and 2 (h), wherein 501 is the SiN medium, and w1 is the gate foot width; also can use the same materials as shown in FIG. 2 (e)
2 (h) combining two steps into one step, only carrying out medium growth and etching once, and etching the medium in the gate pin and outside the channel well in the etching process. In fig. 2 (f), the trench well filled and covered by the dielectric forms a bump that functions to reduce the parasitic capacitance of the trench well, so that the bump is preferably completely retained in the subsequent process; in actual process manufacturing, however, the subsequent trench etching often causes the bump to become smaller.
(5) The gate is fabricated by photolithography and gate cap metallization, and the final structure of the transistor is shown in fig. 2 (i) and 2 (j), where 103 is the gate and w2 is the gate cap width.
For a traditional uniform channel GaN HEMT device, when the forward gate source bias is increased until the channel carrier density exceeds the channel outer carrier density, the low carrier concentration outside the device channel forms current limiting, resulting in the device transconductance curve compressing. Fig. 3 is a schematic view showing the distribution of carriers in the active region of a localized channel structure GaN HEMT, wherein 701 channel carriers are, 702 and 703 are channel outer carriers; even with the increased forward gate-source bias to a channel carrier density that exceeds the off-channel carrier density, the total off-channel carrier concentration may still be greater than the off-channel carrier concentration due to the larger conductive cross-sectional area outside the channel.
Claims (5)
1. A localized channel field effect transistor comprising a source (101), a drain (102), and a gate (103) between the source and drain, characterized by: etching a channel region covered by the gate pin to form a channel well (104) with a certain duty ratio, wherein the channel well (104) is filled with a medium, and the medium filling and covering the channel well forms a bulge relative to the channel region so as to reduce the parasitic capacitance of the channel well; the channel wells (104) are arranged at equal intervals along the extension direction of the channel, the radial width of the channel wells is smaller than the length of the grid, so that the conductive sectional area outside the channel is larger than the effective conductive sectional area of the channel, and the field effect transistor adopts a GaN HEMT.
2. The field effect transistor of claim 1, wherein: the channel well (104) is rectangular, the depth is 10-100nm, the width is 20-500nm, and the length along the extending direction of the channel is 20-1000nm.
3. A method of manufacturing a field effect transistor according to any of claims 1-2, comprising the steps of:
(1) Preparing a source electrode and a drain electrode on the surface of the semiconductor epitaxial material through photoetching, metallization and alloy processes;
(2) Eliminating the conductivity outside the active region through a physical and/or chemical process, and forming a channel well in the channel region;
(3) Growing a medium on the surface of the device, and etching the medium in the gate pin and outside the channel well through an etching process; the method specifically comprises the following steps:
(3.1) growing a medium on the surface of the device for the first time, filling the channel well with the medium after the medium is grown, etching the medium outside the channel well through photoetching and etching processes, and forming a bulge on the medium filling and covering the channel well relative to the channel region so as to reduce the parasitic capacitance of the channel well;
(3.2) growing a medium again, and etching the gate pin through subsequent photoetching and etching processes, wherein the etching region comprises a channel well region;
(4) And completing the preparation of the grid electrode by photoetching a grid cap and a grid metallization process.
4. The method for manufacturing a field effect transistor according to claim 3, wherein: in the step (2), the conductivity outside the active region is eliminated through the photoetching and plasma implantation process or the photoetching and etching process, and then a channel well is formed in the channel region through the photoetching and etching process.
5. The method for manufacturing a field effect transistor according to claim 3, wherein: and (3) growing the SiN medium by adopting PECVD.
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| CN104167438A (en) * | 2013-05-20 | 2014-11-26 | 北京天元广建科技研发有限责任公司 | GaN-based HEMT device |
| CN104409497A (en) * | 2014-11-26 | 2015-03-11 | 西安电子科技大学 | La base gate based AlGaN/GaN high electron mobility transistor and manufacturing method |
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| CN103681831B (en) * | 2012-09-14 | 2017-02-08 | 中国科学院微电子研究所 | High-electron mobility transistor and manufacturing method for same |
| WO2014134490A1 (en) * | 2013-02-28 | 2014-09-04 | Massachusetts Institute Of Technology | Improving linearity in semiconductor devices |
| CN106684141A (en) * | 2016-12-08 | 2017-05-17 | 中国电子科技集团公司第五十五研究所 | High linearity GaN fin-type high electron mobility transistor and manufacture method thereof |
| CN106898640A (en) * | 2017-02-20 | 2017-06-27 | 中国科学院半导体研究所 | A kind of enhanced nitride field-effect transistor and preparation method thereof |
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| CN104167438A (en) * | 2013-05-20 | 2014-11-26 | 北京天元广建科技研发有限责任公司 | GaN-based HEMT device |
| CN104409497A (en) * | 2014-11-26 | 2015-03-11 | 西安电子科技大学 | La base gate based AlGaN/GaN high electron mobility transistor and manufacturing method |
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