CN110098255A - A kind of field effect transistor and preparation method thereof of localization channel - Google Patents
A kind of field effect transistor and preparation method thereof of localization channel Download PDFInfo
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- CN110098255A CN110098255A CN201810144810.2A CN201810144810A CN110098255A CN 110098255 A CN110098255 A CN 110098255A CN 201810144810 A CN201810144810 A CN 201810144810A CN 110098255 A CN110098255 A CN 110098255A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 230000004807 localization Effects 0.000 title claims abstract description 16
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 3
- 238000005530 etching Methods 0.000 claims abstract description 27
- 230000005669 field effect Effects 0.000 claims abstract description 25
- 239000000945 filler Substances 0.000 claims abstract description 9
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims abstract description 6
- 102000013275 Somatomedins Human genes 0.000 claims abstract description 6
- 238000001259 photo etching Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000005275 alloying Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 230000003321 amplification Effects 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The invention discloses a kind of field effect transistor and preparation method thereof of localization channel, transistor includes the grid between source electrode, drain electrode and source-drain electrode, the raceway groove trap to form certain duty ratio is etched in the channel region of grid foot covering, the raceway groove trap is by media filler；The raceway groove trap is equidistantly arranged along channel extending direction, and radial width is less than grid length；Preparation method includes: (1) preparation source electrode and drain electrode；(2) electric conductivity other than active area is eliminated, forms raceway groove trap in channel region；(3) in device surface somatomedin, the medium in grid foot, other than raceway groove trap is performed etching by etching technics；(4) grid is prepared.The present invention can increase the equivalent conductive cross-sectional area outside fieldistor channel, reduce field-effect tube source, drain resistance, alleviate limitation of the limited conductive capability to big positive gate bias lower channel electric current outside channel；Improve the gain and the linearity of radio frequency amplification field effect transistor；Reduce Minimum noises coefficients.
Description
Technical field
The present invention relates to semiconductor devices more particularly to a kind of field effect transistors of localization channel, also relate to
The preparation method of the field effect transistor.
Background technique
Radio frequency amplifying circuit based on Si, GaAs, GaN field effect transistor is in communication, navigation, identification, observing and controlling, broadcast electricity
It is important depending on having in the wide range of areas such as, remote sensing telemetering, radio astronomy, early warning detection, precision tracking, electronic countermeasure, fire control guidance
Using.In related application such as 5G communication, millimeter wave amplification etc., the linearity, the gain characteristic etc. of device are put forward higher requirements；
Currently, the technology for improving the field effect transistor radio frequency amplification linearity mainly includes analog predistortion, the pre- mistake of number
Very, novel circuit configuration design, new device structure design etc.；Analog predistortion passes through in radio frequency amplifier device input terminal
Non-linear predistortion element is introduced, non-linear with predistortion element compensates the non-linear of radio frequency amplifier, such as base
In diode or the linearizer of diode network；The principle of digital pre-distortion and the channel coding in communication are very similar, lead to
It crosses and radio frequency amplifier device input signal is sampled and is digitized, generate thermal compensation signal under the control of digital control module,
Thermal compensation signal is sent into radio frequency amplifier device；The example of novel circuit configuration design includes Doherty amplifying circuit；New device
Structure design includes device semiconductor material design, the design of device portraitlandscape structure.But not yet pass through in the prior art
The design of new device structure is to improve the linearity of field effect transistor and the method for gain.
Summary of the invention
Goal of the invention: in view of the problems of the existing technology, the object of the present invention is to provide one kind can be improved gain and
The linearity, reduce Minimum noises coefficients localization channel field effect transistor, it is a further object of the present invention to provide this
The preparation method of effect transistor.
Technical solution: a kind of field effect transistor of localization channel, including substrate, buffering disposed above the substrate
Layer, channel layer, and it is set to the barrier layer above channel region and buffer layer, it is respectively set at the top both ends of the barrier layer
Source and drain electrode are grid between the source electrode and drain electrode, etch to form certain duty ratio in the channel region of its grid foot covering
Raceway groove trap, the raceway groove trap is by media filler；The raceway groove trap is equidistantly arranged along channel extending direction, and radial width is less than
Grid length, this structure make effective conductive cross-sectional area of the conductive cross-sectional area outside channel greater than channel；The duty ratio is by the vertical of trap
It is determined to length and the spacing of trap and trap.
The field effect transistor uses GaN HEMT, Si GaAs semiconductor material.
The raceway groove trap is rectangle, and depth 10-100nm, width 20-500nm, the size along channel extending direction is
20nm-1000nm。
The preparation method of the field effect transistor, includes the following steps:
(1) source electrode and drain electrode is prepared in semiconductor epitaxial material surface by photoetching, metallization and alloying technology；
(2) electric conductivity other than active area is eliminated by physically and/or chemically technique, and forms raceway groove trap in channel region；
(3) in device surface somatomedin, the medium in grid foot, other than raceway groove trap is performed etching by etching technics.
(4) preparation of grid is completed by photoetching grid cover, grid metal chemical industry skill.
Preferably, in the step (2), have by photoetching and the elimination of Plasma inpouring technique or lithography and etching technique
Electric conductivity other than source region, then raceway groove trap is formed in channel region by photoetching, etching technics.
The step (3) specifically includes two steps: carrying out somatomedin for the first time in device surface, has grown ditch after medium
Road trap is etched the medium other than raceway groove trap by photoetching, etching technics later, is regrowed medium later by media filler, and
Grid foot etching is carried out by subsequent photoetching, etching technics, etch areas includes raceway groove trap region.It is preferred that being grown using PECVD
SiN medium.
The utility model has the advantages that compared to the prior art, the present invention has following marked improvement: can increase field effect transistor pipe trench
Equivalent conductive cross-sectional area outside road, reduce field-effect tube source, drain resistance, alleviate channel outside limited conductive capability to greatly just
Limitation to gate bias lower channel electric current；Improve the gain and the linearity of radio frequency amplification field effect transistor；Reduce minimum
Noise coefficient.
Detailed description of the invention
Fig. 1 (a)-(b) is respectively the top view and section view of GaN HEMT device structure；
Fig. 2 (a)-(j) is the GaN HEMT preparation process schematic diagram of localization channel structure；
Fig. 3 is localization channel structure GaN HEMT active area carriers distribution schematic diagram.
Specific embodiment
Technical solution of the present invention is described in further detail below with reference to embodiment and attached drawing.
In the present embodiment, field effect transistor is GaN high electron mobility transistor (HEMT), localization channel structure
For GaN HEMT structure as shown in Figure 1, wherein Fig. 1 (a) is device architecture top view, Fig. 1 (b) is device architecture sectional view；101 are
Source electrode, 102 be drain electrode, 103 be grid, 104 be raceway groove trap, raceway groove trap 104 is covered by media filler and by gate metal, 105
For AlGaN potential barrier, 106 be GaN channel and buffer layer, and substrate layer is not drawn in the figure；Localization channel proposed by the present invention
Field-effect tube structure is not limited to GaN HEMT, while can also be based on semiconductor materials such as Si, GaAs；The localization channel junction
Structure GaN HEMT significantly increases the ratio long-pending with channels cross-section of the equivalent conductive cross-sectional area outside channel, and (this ratio depends on channel
Duty ratio of the trap in channel), it can achieve and reduce field-effect tube source, drain resistance, alleviate limited conductive capability pair outside channel
The limitation of big forward direction gate bias lower channel electric current, the effect for improving device gain and the linearity.
Fig. 2 (a) -2 (j) is the schematic diagram of the GaN HEMT preparation process of localization channel structure；Preparation process includes such as
Lower step:
(1) first by photoetching, metallization and alloying technology epitaxial material surface prepare source electrode, drain electrode, as Fig. 2 (a),
It is respectively the top view and section view of device architecture shown in 2 (b).
(2) pass through the conduction other than photoetching and Plasma inpouring (or lithography and etching) two-step process elimination active area after
Property, then raceway groove trap, the top view and section view as shown in Fig. 2 (c), 2 (d), ditch are formed in channel region by photoetching, etching technics
The exemplary depth of road trap 104 is 10-100nm, and raceway groove trap is generally rectangular, and the direction x typical sizes are that 20-500nm (is slightly less than
Grid length), the direction y typical sizes are 20-1000nm, and the size and trap of the direction y trap and the spacing of trap determine raceway groove trap in channels
Duty ratio；It should be noted that the raceway groove trap for the localization channel device structure introduced in present example is by ditch
Filled media makes channel local lose electric conductivity realization after road carries out localized etching, makes ditch using other physics, chemical method
Road local loses electric conductivity and realizes localization channel structure, it should also belong to the contents of the present invention.
(4) SiN medium 100nm is grown using PECVD in device surface somatomedin, the present embodiment, has grown medium
Raceway groove trap etches the medium other than raceway groove trap by media filler, then by photoetching, etching technics afterwards, forms Fig. 2 (e), 2 (f) institutes
The structure shown, wherein raceway groove trap 104 is by media filler and covering；SiN medium 100nm is regrowed later, and passes through subsequent optical
It carves, etching technics carries out grid foot etching (etch areas includes raceway groove trap region), structure such as Fig. 2 (g), 2 (h) institutes after etching
Show, wherein 501 be SiN medium, w1For grid foot width；Two steps shown in Fig. 2 (e) -2 (h) can also be combined into a step, only into
Dielectric growth of row and etching, perform etching the medium in grid foot, other than raceway groove trap in etching technics.In Fig. 2 (f),
One protrusion is formed by media filler and the raceway groove trap of covering, which is the parasitic capacitance of reduction raceway groove trap, therefore best
The case where be exactly that protrusion is fully retained in the subsequent process；But in the manufacture of actual technique, in subsequent channel etching
Can often make that protrusion is caused to become smaller.
(5) preparation that grid is completed by photoetching grid cover, grid metal chemical industry skill, obtains the final structure of transistor such as at this time
Fig. 2 (i), shown in 2 (j), wherein 103 be grid, w2For grid cover width.
For traditional uniform channel GaN HEMT device, it is more than when increase positive grid source biases to channel carrier density
Outside channel when carrier density, low carrier concentration forms current limliting outside device channel, leads to device transconductance curve compression.Fig. 3
It is shown localization channel structure GaN HEMT active area carriers distribution schematic diagram, wherein 701 channel carriers, 702,
703 be the outer carrier of channel；Even if biasing to channel carrier density more than carrier density outside channel increasing positive grid source
In the case where, due to having bigger conductive cross-sectional area outside channel, total carrier concentration can still be greater than current-carrying under channel outside channel
Sub- concentration.
Claims (7)
1. a kind of field effect transistor of localization channel, including the grid between source electrode (101), drain electrode (102) and source-drain electrode
(103), it is characterised in that: the raceway groove trap (104) to form certain duty ratio, the raceway groove trap are etched in the channel region of grid foot covering
(104) by media filler；The raceway groove trap (104) equidistantly arranges along channel extending direction, and radial width is less than grid length, with
The conductive cross-sectional area outside channel is set to be greater than effective conductive cross-sectional area of channel.
2. field effect transistor according to claim 1, it is characterised in that: the field effect transistor uses GaN
HEMT, Si or GaAs semiconductor material.
3. field effect transistor according to claim 1, it is characterised in that: the raceway groove trap (104) is rectangle, and depth is
10-100nm, width 20-500nm, the length along channel extending direction are 20-1000nm.
4. the method for preparing the field effect transistor as described in claim 1-3, which comprises the steps of:
(1) source electrode and drain electrode is prepared in semiconductor epitaxial material surface by photoetching, metallization and alloying technology；
(2) electric conductivity other than active area is eliminated by physically and/or chemically technique, and forms raceway groove trap in channel region；
(3) in device surface somatomedin, the medium in grid foot, other than raceway groove trap is performed etching by etching technics；
(4) preparation of grid is completed by photoetching grid cover and grid metal chemical industry skill.
5. field effect transistor tube preparation method according to claim 4, it is characterised in that: in the step (2), pass through light
Quarter and Plasma inpouring technique or lithography and etching technique eliminate the electric conductivity other than active area, then pass through lithography and etching work
Skill forms raceway groove trap in channel region.
6. field effect transistor tube preparation method according to claim 4, it is characterised in that: the step (3) specifically includes
Following content:
(3.1) somatomedin for the first time is carried out in device surface, raceway groove trap passes through photoetching by media filler later after having grown medium
The medium other than raceway groove trap is etched with etching technics；
(3.2) medium is regrowed, and grid foot etching is carried out by subsequent photoetching and etching technics, etch areas includes raceway groove trap
Region.
7. the field effect transistor tube preparation method according to claim 4 or 6, it is characterised in that: the step (3) uses
PECVD grows SiN medium.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2018100832985 | 2018-01-29 | ||
| CN201810083298 | 2018-01-29 |
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| Publication Number | Publication Date |
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| CN110098255A true CN110098255A (en) | 2019-08-06 |
| CN110098255B CN110098255B (en) | 2022-10-28 |
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| CN201810144810.2A Active CN110098255B (en) | 2018-01-29 | 2018-02-12 | Localized channel field effect transistor and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111969046A (en) * | 2020-07-15 | 2020-11-20 | 西安电子科技大学 | High-linearity enhanced gallium nitride high-electron-mobility transistor and preparation method thereof |
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| CN104167438A (en) * | 2013-05-20 | 2014-11-26 | 北京天元广建科技研发有限责任公司 | GaN-based HEMT device |
| CN104409497A (en) * | 2014-11-26 | 2015-03-11 | 西安电子科技大学 | La base gate based AlGaN/GaN high electron mobility transistor and manufacturing method |
| US20150372081A1 (en) * | 2013-02-28 | 2015-12-24 | Massachusetts Institute Of Technology | Improving linearity in semiconductor devices |
| CN106684141A (en) * | 2016-12-08 | 2017-05-17 | 中国电子科技集团公司第五十五研究所 | High linearity GaN fin-type high electron mobility transistor and manufacture method thereof |
| CN106898640A (en) * | 2017-02-20 | 2017-06-27 | 中国科学院半导体研究所 | A kind of enhanced nitride field-effect transistor and preparation method thereof |
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2018
- 2018-02-12 CN CN201810144810.2A patent/CN110098255B/en active Active
Patent Citations (6)
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|---|---|---|---|---|
| CN103681831A (en) * | 2012-09-14 | 2014-03-26 | 中国科学院微电子研究所 | High-electron mobility transistor and manufacturing method for same |
| US20150372081A1 (en) * | 2013-02-28 | 2015-12-24 | Massachusetts Institute Of Technology | Improving linearity in semiconductor devices |
| CN104167438A (en) * | 2013-05-20 | 2014-11-26 | 北京天元广建科技研发有限责任公司 | GaN-based HEMT device |
| CN104409497A (en) * | 2014-11-26 | 2015-03-11 | 西安电子科技大学 | La base gate based AlGaN/GaN high electron mobility transistor and manufacturing method |
| CN106684141A (en) * | 2016-12-08 | 2017-05-17 | 中国电子科技集团公司第五十五研究所 | High linearity GaN fin-type high electron mobility transistor and manufacture method thereof |
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| CN111969046A (en) * | 2020-07-15 | 2020-11-20 | 西安电子科技大学 | High-linearity enhanced gallium nitride high-electron-mobility transistor and preparation method thereof |
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