CN102130159B - High electron mobility transistor - Google Patents
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- CN102130159B CN102130159B CN201110001515XA CN201110001515A CN102130159B CN 102130159 B CN102130159 B CN 102130159B CN 201110001515X A CN201110001515X A CN 201110001515XA CN 201110001515 A CN201110001515 A CN 201110001515A CN 102130159 B CN102130159 B CN 102130159B
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Abstract
The invention discloses a high electron mobility transistor, and mainly solves the problems of serious current collapse and high source/drain ohmic contact resistance in the prior art. From bottom to top, the high electron mobility transistor comprises a substrate (1), a nucleation layer (2), a main channel layer (3), a barrier layer (4) and a dielectric layer (13), wherein both sides of the top end of the barrier layer (4) are respectively provided with a source (10) and a drain (12), and the middle of the top end of the barrier layer (4) is provided with a gate (11); an auxiliary channel layer (5), a graded barrier layer (6), a high barrier layer (7), an isolation channel layer (8) and an isolation barrier layer (9) are sequentially added onto the barrier layer (4); the gate (11) is positioned in a groove (14) between the barrier layer and the isolation barrier layer; and both sides and the bottom of the gate are respectively provided with the dielectric layer (13). Two-dimensional electron gas (2DEG) is respectively formed on the interface of the isolation barrier layer and isolation channel layer, the interface of the graded barrier layer and auxiliary channel layer, and the interface of the barrier layer and main channel layer. The invention can avoid current collapse under high field stress and reduce the source/drain ohmic contact resistance, and can be used as a high-temperature high-frequency high-reliability high-power device.
Description
Technical field
The invention belongs to microelectronics technology, relate to semiconductor device.Specifically a kind of high electron mobility transistor (HEMT) can be used as the highly reliable high power device of high temperature high frequency.
Background technology
As the typical case of semiconductor material with wide forbidden band representative, the GaN sill has that energy gap is big, the electronics saturation drift velocity is high, disruptive field intensity is high and characteristics such as good heat conductivity, can be used for making high temperature, high frequency and high-power electronic device.The more important thing is; The GaN sill can form the AlGaN/GaN heterostructure of modulation doping; This structure at room temperature can obtain very high electron mobility; High peak value velocity of electrons and saturated electrons speed, and obtain the two-dimensional electron gas 2DEG density higher than second generation compound semiconductor heterostructure.Therefore, the high electron mobility transistor (HEMT) based on the AlGaN/GaN heterojunction has extraordinary application prospect aspect the HIGH-POWERED MICROWAVES device.Simultaneously, have huge demand prospect and application potential in application systems such as radar, communication, high temperature and radioresistance and field.
Since first AlGaN/GaN HEMT device in 1993 came out, AlGaN/GaN HEMT device had just obtained great attention and extensive studies, and achievement is abundant.But go deep into along with what HEMT was studied, found current collapse phenomenon wherein, this phenomenon is defined as: leakage current ID is than the phenomenon of anticipation value decline under certain condition.
Since the current collapse phenomenon comes to light; People have just carried out deep analysis to it; And proposed some reasonable model and explain the current collapse phenomenon, wherein empty bar phantom is generally received at present, also is the most ripe, the most convictive a kind of model.1999, people such as Kohn just proposed to form empty grid between grid, the drain electrode when analyzing the high frequency dispersion phenomenon of GaN base MODFET, have limited channel current; Thereby reduced the empty bar phantom of microwave output power, with reference to Kohn E, Daumiller I, Schmid P; Et al, Large signal frequency dispersion ofAlGaN/GaN heterostructure field effect transistors, Electron Letters; 1999,35 (12), p1022.But they do not launch to go deep into detailed discussion to this model at that time.Up to calendar year 2001; During the surface state effect of human floating boom method research AlGaN/GaN HEMT such as Vetury; Found that there is the phenomenon of a large amount of negative electrical charges and surface potential negative bias in device surface; And propose the surface state trapped electron thus and form empty grid, finally cause the empty bar phantom of current collapse under the high-field stress.People such as Vetury think, because there is more intense polarization in the AlGaN/GaN heterojunction structure, will obtain concentration＞10 in heterojunction boundary GaN one side
13/ cm
2Two-dimensional electron gas, according to the electric neutrality requirement, device surface will inevitably induce a large amount of positive charge attitudes, these positive charges are trapped electron in the device course of work.This is like between the grid leak electrode, having another grid, promptly so-called empty grid.Because the time that discharges and recharges of these surface state energy levels is very big usually, the frequency of being unable to catch up with the RF signal is so under the RF signal; Empty grid can be modulated the concentration of channel electrons, and device output current is reduced, and knee-point voltage increases; Output power density and power added efficiency reduce, and form avalanche.List of references Ramakrishna Vetury, Naiqain Q.Zhang, Stacia Keller; Et al; The Impact of Surface States on the DC and RF Characteristics of AlGaN/GaN HFETs, IEEE Transactions on electron devices, 2001.3; 48 (3), p560.
Current, the method that can reduce current collapse effectively mainly contains two kinds: device surface passivation method and the method that adds the cap layer.Wherein:
The method of device surface passivation is a kind of method relatively more commonly used.2000, the people such as Green of UCSB university used the Si of PECVD method deposit one bed thickness as 350nm at the device surface of accomplishing electrode
3N
4Film is as passivation layer.Experimental result is found, through Si
3N
4The output power density of the AlGaN/GaN HEMT of passivation is doubled.Afterwards, a plurality of research groups have also successively confirmed Si
3N
4The method of passivation can suppress current collapse effectively.But this method complex process; And just reduce current collapse to a certain extent; Can not stop the influence of surface state to two-dimensional electron gas in the tap drain road fully, two-dimensional electron gas still can be captured by surface state during high electric field, thereby influences the stable and reliability of device performance.
The method that adds the cap layer is at the AlGaN/GaN material surface GaN cap layer that extension one deck is thicker again, and purpose is to come isolation channel and surface with this GaN cap layer, reduces the influence of surface to two-dimensional electron gas in the raceway groove, and then plays the effect that reduces current collapse.But the defective of this method is: some traps that this cap layer contains itself under high-field stress can be to raceway groove in two-dimensional electron gas certain influence is arranged; And the introducing of this cap layer can make that two-dimensional electron gas density reduces in the raceway groove, thereby reduces device performance.
Summary of the invention
The objective of the invention is to overcome the defective of above-mentioned prior art, propose a kind of HEMT,, improve device performance to avoid current collapse from the optimization angle of device vertical structure.
For realizing above-mentioned purpose, the device architecture that the present invention adopts comprises from bottom to top: substrate, nucleating layer, main channel layer, barrier layer, dielectric layer; Both sides, barrier layer top are respectively source electrode and drain electrode, and the centre is a grid, it is characterized in that: increasing successively on the barrier layer has auxilliary channel layer, gradual barrier layer, high barrier layer, isolation channel layer and isolation barrier layer; In the groove of grid between barrier layer and isolation barrier layer, the both sides and the bottom of grid are provided with dielectric layer.
On described isolation barrier layer and the isolation channel bed boundary, on gradual barrier layer and the auxilliary channel layer interface, be formed with two-dimensional electron gas 2DEG respectively on barrier layer and the bed boundary, tap drain road.
Described isolation barrier layer and barrier layer are Al
xIn
yGa
(1-x-y)N, and 0＜x＜1,0≤y≤0.18, x+y≤1, isolation channel layer, auxilliary channel layer and main channel layer are In
zGa
1-zN, and 0≤z≤0.05.
Described high barrier layer is Al
0.5Ga
0.5N.
Described gradual barrier layer is Al
mGa
1-mN, 0≤m≤0.5, and from gradual barrier layer and high barrier layer interface to gradual barrier layer and auxilliary channel layer interface, the Al component m of gradual barrier layer by 0.5 gradual be 0.
Described nucleating layer is Al
mGa
1-mN, and 0≤m≤1.
Grid media of both sides thickness is 5～30nm in the described groove, and the gate bottom thickness of dielectric layers is 0～5nm, and the thickness range of isolation barrier layer top dielectric layer is 30～500nm.
For realizing above-mentioned purpose, the method for making HEMT provided by the invention comprises following process:
The first step, on substrate, adopting metallo-organic compound chemical vapor deposition MOCVD technology epitaxial thickness is the nucleating layer of 30～100nm, wherein the composition of nucleating layer is Al
mGa
1-mN, and 0≤m≤1, the temperature that extension adopts is 980 ℃, pressure is 20Torr;
In second step, on nucleating layer, adopting MOCVD technology epitaxial thickness is the main channel layer of 1～5 μ m, and wherein the composition in tap drain road is In
zGa
1-zN, and 0≤z≤0.05, the temperature that extension adopts is 500～920 ℃, pressure is 40～200Torr;
In the 3rd step, on main channel layer, adopting MOCVD technology epitaxial thickness is the barrier layer of 20nm, and wherein the composition of barrier layer is Al
xIn
yGa
(1-x-y)N, and 0＜x＜1,0≤y≤0.18, x+y≤1, the temperature that extension adopts is 600～1000 ℃, pressure is 40～200Torr;
In the 4th step, on barrier layer, adopting MOCVD technology epitaxial thickness is the auxilliary channel layer of 10nm, and wherein the composition of auxilliary channel layer is In
zGa
1-zN, and 0≤z≤0.05, the temperature that extension adopts is 500～920 ℃, pressure is 40～200Torr;
In the 5th step, on auxilliary channel layer, adopting MOCVD technology epitaxial thickness is the gradual barrier layer of 10nm, and wherein the composition of gradual barrier layer is Al
mGa
1-mN, 0≤m≤0.5, al compsn from the substrate direction upwards by 0% gradual be 50%, the temperature that extension adopts is 920 ℃, pressure is 40Torr;
In the 6th step, on gradual barrier layer, adopting MOCVD technology epitaxial thickness is the high barrier layer of 5nm, and wherein the composition of high barrier layer is Al
0.5Ga
0.5N, the temperature that extension adopts is 920 ℃, pressure is 40Torr;
In the 7th step, on high barrier layer, adopting MOCVD technology epitaxial thickness is the isolation channel layer of 10nm, and wherein the composition of isolation channel layer is In
zGa
1-zN, and 0≤z≤0.05, the temperature that extension adopts is 500～920 ℃, pressure is 40～200Torr;
In the 8th step, on the isolation channel layer, adopting MOCVD technology epitaxial thickness is the isolation barrier layer of 20nm, and wherein the composition of isolation barrier layer is Al
xIn
yGa
(1-x-y)N, and 0＜x＜1,0≤y≤0.18, x+y≤1, the temperature that extension adopts is 600～1000 ℃, pressure is 40～200Torr;
In the 9th step, photoetching also adopts reactive ion etching RIE technology to etch groove, is etched to barrier layer, reacting gas CF
4Flow be 20sccm, O
2Flow be 5mT for 2sccm pressure, power is 50W;
In the tenth step, it is the dielectric layer of 30～500nm that using plasma strengthens chemical vapour deposition (CVD) PECVD equipment deposition thickness, and this dielectric layer covers isolation barrier laminar surface and groove inwall;
The 11 step; Photoetching also etches source electrode, grid and drain region; Wherein source electrode and drain region begin to be etched to barrier layer from the dielectric layer surface; Area of grid is in groove, and etched recesses medium layer to bottom portion of groove thickness of dielectric layers is 0～5nm, and both sides, groove inner grid zone remain with dielectric layer respectively;
In the 12 step, evaporated metal forms source electrode, grid and drain electrode, and source electrode and drain metal adopt the Ti/Al/Ni/Au combination, and wherein the thickness of Ti is 10～40nm, and the thickness of Al is 30～160nm, and the thickness of Ni is 20～120nm, and the thickness of Au is 60～150nm; And gate metal adopts the Ni/Au combination, and wherein the thickness of Ni is 10～40nm, and the thickness of Au is 80～400nm.
The thickness of dielectric layers that described groove both sides keep is 5～30nm.
The present invention has following advantage:
1. more effectively avoid the current collapse phenomenon.
The present invention is owing to improve the device vertical structure; Adopt the isolation channel layer to come the various influences of response surface attitude; Avoided the 2DEG in the tap drain road to be captured, avoided effectively reducing the current collapse phenomenon that causes because of two-dimensional electron gas 2DEG in the tap drain road under the High-Field by surface trap.
2. leakage ohmic contact resistance in source is littler.
Owing in isolation channel layer, auxilliary channel layer, main channel layer, all be formed with two-dimensional electron gas 2DEG, the mobility of these 2DEG is much larger than the body electronics of three-dimensional state among the present invention, thereby reduces the source-drain electrode ohmic contact resistance greatly, improves device performance.
Description of drawings
Fig. 1 is a HEMT cross-sectional view of the present invention;
Fig. 2 is the making flow chart of HEMT of the present invention.
Embodiment
With reference to Fig. 1, HEMT of the present invention is based on the heterojunction structure of wide bandgap compound semiconductor material, and this structure is specially: be nucleating layer 2 above the substrate 1, nucleating layer 2 is Al
mGa
1-mN, and 0≤m≤1; Nucleating layer 2 tops are main channel layers 3, and main channel layer 3 is In
zGa
1-zN, and 0≤z≤0.05; 3 tops, tap drain road are barrier layers 4, and barrier layer 4 is Al
xIn
yGa
(1-x-y)N, and 0≤x≤1,0≤y≤1, x+y≤1; Both sides, barrier layer 4 top are respectively source electrode 10 and drain electrode 12, and the centre is a grid 11; Barrier layer 4 tops are auxilliary channel layers 5, and auxilliary channel layer 5 is In
zGa
1-zN, and 0≤z≤0.05; Auxilliary channel layer 5 tops are gradual barrier layers 6, and gradual barrier layer 6 is Al
mGa
1-mN, 0≤m≤0.5, and the Al component m of gradual from bottom to top barrier layer 6 by 0 gradual be 0.5; Gradual barrier layer 6 tops are high barrier layers 7, and high barrier layer 7 is Al
0.5Ga
0.5N; High barrier layer 7 tops are isolation channel layers 8, and isolation channel layer 8 is In
zGa
1-zN, and 0≤z≤0.05; Isolation channel layer 8 top are isolation barrier layers 9, and isolation barrier layer 9 is Al
xIn
yGa
(1-x-y)N, and 0≤x≤1,0≤y≤1, x+y≤1; Grid 11 is in the groove 14 between isolation barrier layer 9 and the top barrier layer 4; All there is dielectric layer 13 grid both sides and bottom and isolation barrier layer 9 top; Wherein, The thickness of grid media of both sides layer is 5～30nm in the groove, and the thickness of gate bottom dielectric layer is 0～5nm, and the thickness of isolation barrier layer 9 top dielectric layer is 30～500nm; On isolation barrier layer (9) and isolation channel layer (8) interface, on gradual barrier layer (6) and auxilliary channel layer (5) interface, be formed with two-dimensional electron gas 2DEG respectively on barrier layer (4) and main channel layer (3) interface.
Embodiment 1
Nucleating layer adopts GaN, and main channel layer, auxilliary channel layer and isolation channel layer adopt GaN, and barrier layer adopts Al
0.25Ga
0.75N, the isolation barrier layer adopts Al
0.2Ga
0.8N.With reference to Fig. 2, manufacturing process is following:
Step 1 goes up extension nucleating layer (2) at substrate (1), like Fig. 2 (a).
Substrate adopts sapphire, and to adopt metallo-organic compound chemical vapor deposition MOCVD technology extension one layer thickness above that be the GaN nucleating layer of 100nm.The process conditions of extension GaN nucleating layer are: temperature is 980 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 20 μ mol/min.
Step 2 goes up extension master channel layer (3) at nucleating layer (2), like Fig. 2 (b).
On nucleating layer (2), adopting MOCVD technology epitaxial thickness is GaN master's channel layer (3) of 5 μ m.The process conditions of extension GaN master channel layer are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 105 μ mol/min.
Step 3 goes up extension barrier layer (4) at main channel layer (3), like Fig. 2 (c).
On main channel layer (3), adopting MOCVD technology epitaxial thickness is the Al of 20nm
0.25Ga
0.75N barrier layer (4).Extension Al
0.25Ga
0.75The process conditions of N barrier layer are: temperature is 1000 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10 μ mol/min, and the gallium source flux is 36 μ mol/min.
Step 4 goes up the auxilliary channel layer (5) of extension at barrier layer (4), like Fig. 2 (d).
On barrier layer (4), adopting MOCVD technology epitaxial thickness is the auxilliary channel layer (5) of GaN of 10nm.The process conditions of the auxilliary channel layer of extension GaN are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 100 μ mol/min.
Step 5 goes up the gradual barrier layer of extension (6) at auxilliary channel layer (5), like Fig. 2 (e).
On auxilliary channel layer (5), adopting MOCVD technology epitaxial thickness is the gradual barrier layer (6) of 10nm, and wherein the composition of gradual barrier layer is Al
mGa
1-mN, 0≤m≤0.5, al compsn m from the substrate direction upwards by 0 gradual be 0.5.The process conditions of the gradual barrier layer of extension are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and to 13 μ mol/min, the gallium source flux is 20 μ mol/min to the aluminium source flux by 0 μ mol/min.
Step 6 goes up the high barrier layer of extension (7) at gradual barrier layer (6), like Fig. 2 (f).
On gradual barrier layer (6), adopting MOCVD technology epitaxial thickness is the Al of 5nm
0.5Ga
0.5The high barrier layer of N (7).Extension Al
0.5Ga
0.5The process conditions of the high barrier layer of N are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 13 μ mol/min, and the gallium source flux is 20 μ mol/min.
Step 7 goes up epitaxial isolation channel layer (8) at high barrier layer (7), like Fig. 2 (g).
On high barrier layer (7), adopting MOCVD technology epitaxial thickness is the GaN isolation channel layer (8) of 10nm.The process conditions of the auxilliary channel layer of extension GaN are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 100 μ mol/min.
Step 8 goes up extension isolation barrier layer (9) at isolation channel layer (8), like Fig. 2 (h).
On isolation channel layer (8), adopting MOCVD technology epitaxial thickness is the Al of 20nm
0.2Ga
0.8N isolation barrier layer (9).Extension Al
0.2Ga
0.8The process conditions of the high barrier layer of N are: temperature is 1000 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 4 μ mol/min, and the gallium source flux is 20 μ mol/min.
Step 9, photoetching also adopts dry etching to go out groove (14) zone, like Fig. 2 (i).
Photoetching also adopts reactive ion etching RIE technology to etch grooved area, and etching depth is 55nm.The process conditions that adopt in the etched recesses zone are: reacting gas CF
4Flow be 20sccm, O
2Flow be 2sccm, pressure is 5mT, power is 50W.
Step 10, deposit one deck dielectric layer (13) is like Fig. 2 (j).
It is the SiN dielectric layer (13) of 30nm that using plasma strengthens chemical vapour deposition (CVD) PECVD equipment deposition thickness, and this dielectric layer covers isolation barrier layer (9) surface and groove (14) inwall.The process conditions of deposit SiN dielectric layer are: NH
3Flow be 2.5sccm, N
2Flow be 900sccm, SiH
4Flow be 200sccm, temperature is 300 ℃, pressure is 900mT, power is 25W.
Photoetching also etches source electrode, grid and drain region, and wherein source electrode and drain electrode are positioned at barrier layer (4) both sides, top, and source electrode and drain region begin to be etched to barrier layer (4) from the dielectric layer surface, and etching depth is 85nm; Area of grid is in groove, and till etched recesses medium layer to bottom portion of groove thickness of dielectric layers is 0nm, and to leave thickness of dielectric layers respectively be 5nm to both sides, groove inner grid zone.The process conditions that etching adopts are: reacting gas CF
4Flow be 20sccm, O
2Flow be 2sccm, pressure is 5mT, power is 50W.
Adopt electron beam evaporation technique at the source electrode and the drain region evaporated metal of etching, again at N
2Carry out rapid thermal annealing in the atmosphere, make source electrode 10 and drain electrode 12, wherein source electrode and drain metal adopt Ti/Al/Ni/Au to make up, and the thickness of Ti is 10nm, and the thickness of Al is 30nm, and the thickness of Ni is 20nm, and the thickness of Au is 60nm; The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～1000W, evaporation rate less than
The process conditions that rapid thermal annealing adopts are: temperature is 850 ℃, and the time is 60s.
Adopt electron beam evaporation technique at the area of grid evaporated metal of etching, gate metal adopts the Ni/Au combination, and wherein the thickness of Ni is 10nm, and the thickness of Au is 400nm.The process conditions that the deposit gate metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
Embodiment 2
Nucleating layer adopts AlN, and main channel layer, auxilliary channel layer and isolation channel layer adopt In
0.05Ga
0.95N, barrier layer and isolation barrier layer adopt Al
0.82In
0.18N.Manufacturing process is following:
Step 1, substrate adopt sapphire, and to adopt metallo-organic compound chemical vapor deposition MOCVD technology extension one layer thickness above that be the AlN nucleating layer of 30nm.The process conditions of extension AlN nucleating layer are: temperature is 980 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 1500sccm, and the aluminium source flux is 18 μ mol/min.
Step 2, on nucleating layer (2), adopting MOCVD technology epitaxial thickness is the In of 1 μ m
0.05Ga
0.95N master's channel layer (3).Extension In
0.05Ga
0.95The process conditions of N master's channel layer are: temperature is 500 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 10 μ mol/min, and the indium source flux is 2.8 μ mol/min.
Step 3, on main channel layer (3), adopting MOCVD technology epitaxial thickness is the Al of 20nm
0.82In
0.18N barrier layer (4).Extension Al
0.82In
0.18The process conditions of N barrier layer are: temperature is 600 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 18 μ mol/min, and the indium source flux is 1 μ mol/min.
Step 4, on barrier layer (4), adopting MOCVD technology epitaxial thickness is the In of 10nm
0.05Ga
0.95N assists channel layer (5).Extension In
0.05Ga
0.95The process conditions of the auxilliary channel layer of N are: temperature is 500 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 10 μ mol/min, and the indium source flux is 2.8 μ mol/min.
Step 5 is identical with the step 5 of embodiment 1.
Step 6 is identical with the step 6 of embodiment 1.
Step 7, on high barrier layer (7), adopting MOCVD technology epitaxial thickness is the In of 10nm
0.05Ga
0.95N isolation channel layer (8).Extension In
0.05Ga
0.95The process conditions of N isolation channel layer are: temperature is 500 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 10 μ mol/min, and the indium source flux is 2.8 μ mol/min.
Step 8, on isolation channel layer (8), adopting MOCVD technology epitaxial thickness is the Al of 20nm
0.82In
0.18N isolation barrier layer (9).Extension Al
0.82In
0.18The process conditions of N isolation barrier layer are: temperature is 600 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 18 μ mol/min, and the indium source flux is 1 μ mol/min.
Step 9 is identical with the step 9 of embodiment 1.
It is the SiN dielectric layer (13) of 500nm that step 10, using plasma strengthen chemical vapour deposition (CVD) PECVD equipment deposition thickness, and this dielectric layer covers isolation barrier layer (9) surface and groove (14) inwall.The process conditions of deposit SiN dielectric layer are: NH
3Flow be 2.5sccm, N
2Flow be 900sccm, SiH
4Flow be 200sccm, temperature is 300 ℃, pressure is 900mT, power is 25W.
Adopt electron beam evaporation technique at the area of grid evaporated metal of etching, gate metal adopts the Ni/Au combination, and wherein the thickness of Ni is 40nm, and the thickness of Au is 80nm.The process conditions that the deposit gate metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
Embodiment 3
Nucleating layer adopts Al
0.35Ga
0.65N, main channel layer, auxilliary channel layer and isolation channel layer adopt In
0.03Ga
0.97N, barrier layer and isolation barrier layer adopt Al
0.27In
0.03Ga
0.7N.Manufacturing process is following:
Step 1, substrate adopt sapphire, and to adopt metallo-organic compound chemical vapor deposition MOCVD technology extension one layer thickness above that be the Al of 60nm
0.35Ga
0.65The N nucleating layer.Extension Al
0.35Ga
0.65The process conditions of N nucleating layer are: temperature is 980 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 1500sccm, and the aluminium source flux is 18 μ mol/min, and the gallium source flux is 45 μ mol/min.
Step 2, on nucleating layer (2), adopting MOCVD technology epitaxial thickness is the In of 1.5 μ m
0.03Ga
0.97N master's channel layer (3).Extension In
0.03Ga
0.97The process conditions of N master's channel layer are: temperature is 600 ℃, and pressure is 150Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 10 μ mol/min, and the indium source flux is 2.2 μ mol/min.
Step 3, on main channel layer (3), adopting MOCVD technology epitaxial thickness is the Al of 20nm
0.27In
0.03Ga
0.7N barrier layer (4).Extension Al
0.27In
0.03Ga
0.7The process conditions of N barrier layer are: temperature is 700 ℃, and pressure is 100Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 3.5 μ mol/min, and the indium source flux is 2.4 μ mol/min, and the gallium source flux is 10 μ mol/min.
Step 4, on barrier layer (4), adopting MOCVD technology epitaxial thickness is the In of 10nm
0.03Ga
0.97N assists channel layer (5).Extension In
0.03Ga
0.97The process conditions of the auxilliary channel layer of N are: temperature is 600 ℃, and pressure is 150Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 10 μ mol/min, and the indium source flux is 2.2 μ mol/min.
Step 5 is identical with the step 5 of embodiment 1.
Step 6 is identical with the step 6 of embodiment 1.
Step 7, on high barrier layer (7), adopting MOCVD technology epitaxial thickness is the In of 10nm
0.03Ga
0.97N isolation channel layer (8).Extension In
0.03Ga
0.97The process conditions of N isolation channel layer are: temperature is 600 ℃, and pressure is 150Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the gallium source flux is 10 μ mol/min, and the indium source flux is 2.2 μ mol/min.
Step 8, on isolation channel layer (8), adopting MOCVD technology epitaxial thickness is the Al of 20nm
0.27In
0.03Ga
0.7N isolation barrier layer (9).Extension Al
0.27In
0.03Ga
0.7The process conditions of N isolation barrier layer are: temperature is 700 ℃, and pressure is 100Torr, and hydrogen flowing quantity is 500sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 3.5 μ mol/min, and the indium source flux is 2.4 μ mol/min, and the gallium source flux is 10 μ mol/min.
Step 9 is identical with the step 9 of embodiment 1.
It is the SiN dielectric layer (13) of 200nm that step 10, using plasma strengthen chemical vapour deposition (CVD) PECVD equipment deposition thickness, and this dielectric layer covers isolation barrier layer (9) surface and groove (14) inwall.The process conditions of deposit SiN dielectric layer are: NH
3Flow be 2.5sccm, N
2Flow be 900sccm, SiH
4Flow be 200sccm, temperature is 300 ℃, pressure is 900mT, power is 25W.
Adopt electron beam evaporation technique at the area of grid evaporated metal of etching, gate metal adopts the Ni/Au combination, and wherein the thickness of Ni is 30nm, and the thickness of Au is 200nm.The process conditions that the deposit gate metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
The foregoing description several preferred embodiments only of the present invention do not constitute any restriction of the present invention; Obviously to those skilled in the art; After having understood content of the present invention and principle; Can under the situation that does not deviate from the principle and scope of the present invention, carry out various corrections and change on form and the details according to the method for the invention, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Claims (5)
1. a HEMT comprises: substrate (1), nucleating layer (2), main channel layer (3), barrier layer (4), dielectric layer (13) from bottom to top; Barrier layer (4) both sides, top are respectively source electrode (10) and drain electrode (12); The centre is grid (11), it is characterized in that: increasing successively on the barrier layer (4) has auxilliary channel layer (5), gradual barrier layer (6), high barrier layer (7), isolation channel layer (8) and isolation barrier layer (9); Grid (11) is arranged in the groove (14) between barrier layer (4) and the isolation barrier layer (9), and the both sides of grid and bottom are provided with dielectric layer (13); This isolation barrier layer (9) and barrier layer (4) are Al
xIn
yGa
(1-x-y)N, and 0＜x＜1,0≤y≤0.18, x+y≤1; This isolation channel layer (8), auxilliary channel layer (5) and main channel layer (3) are In
zGa
1-zN, and 0≤z≤0.05; This high barrier layer (7) is Al
0.5Ga
0.5N; This gradual barrier layer (6) is Al
mGa
1-mN, 0≤m≤0.5, and from gradual barrier layer (6) and high barrier layer (7) interface to gradual barrier layer (6) and auxilliary channel layer (5) interface, the Al component m of gradual barrier layer (6) by 0.5 gradual be 0; This nucleating layer (2) is Al
mGa
1-mN, and 0≤m≤1.
2. HEMT according to claim 1; It is characterized in that; On isolation barrier layer (9) and isolation channel layer (8) interface, on gradual barrier layer (6) and auxilliary channel layer (5) interface, be formed with two-dimensional electron gas 2DEG respectively on barrier layer (4) and main channel layer (3) interface.
3. HEMT according to claim 1; It is characterized in that; Grid media of both sides layer thickness is 5～30nm in the groove (14), and the gate bottom thickness of dielectric layers is 0～5nm, and the thickness range of isolation barrier layer (9) top dielectric layer (13) is 30～500nm.
4. method of making HEMT comprises following process:
The first step, on substrate (1), adopting metallo-organic compound chemical vapor deposition MOCVD technology epitaxial thickness is the nucleating layer (2) of 30～100nm, wherein the composition of nucleating layer is Al
mGa
1-mN, and 0≤m≤1, the temperature that extension adopts is 980 ℃, pressure is 20Torr;
In second step, on nucleating layer (2), adopting MOCVD technology epitaxial thickness is the main channel layer (3) of 1～5 μ m, and wherein the composition in tap drain road is InzGa
1-zN, and 0≤z≤0.05, the temperature that extension adopts is 500～920 ℃, pressure is 40～200Torr;
In the 3rd step, on main channel layer (3), adopting MOCVD technology epitaxial thickness is the barrier layer (4) of 20nm, and wherein the composition of barrier layer (4) is Al
xIn
yGa
(1-x-y)N, and 0＜x＜1,0≤y≤0.18, x+y≤1, the temperature that extension adopts is 600～1000 ℃, pressure is 40～200Torr;
In the 4th step, on barrier layer (4), adopting MOCVD technology epitaxial thickness is the auxilliary channel layer (5) of 10nm, and wherein the composition of auxilliary channel layer is In
zGa
1-zN, and 0≤z≤0.05, the temperature that extension adopts is 500～920 ℃, pressure is 40～200Torr;
In the 5th step, on auxilliary channel layer (5), adopting MOCVD technology epitaxial thickness is the gradual barrier layer (6) of 10nm, and wherein the composition of gradual barrier layer is Al
mGa
1-mN, 0≤m≤0.5, al compsn from the substrate direction upwards by 0% gradual be 50%, the temperature that extension adopts is 920 ℃, pressure is 40Torr;
In the 6th step, on gradual barrier layer (6), adopting MOCVD technology epitaxial thickness is the high barrier layer (7) of 5nm, and wherein the composition of high barrier layer is Al
0.5Ga
0.5N, the temperature that extension adopts is 920 ℃, pressure is 40Torr;
In the 7th step, on high barrier layer (7), adopting MOCVD technology epitaxial thickness is the isolation channel layer (8) of 10nm, and wherein the composition of isolation channel layer is In
zGa
1-zN, and 0≤z≤0.05, the temperature that extension adopts is 500～920 ℃, pressure is 40～200Torr;
In the 8th step, on isolation channel layer (8), adopting MOCVD technology epitaxial thickness is the isolation barrier layer (9) of 20nm, and wherein the composition of isolation barrier layer is Al
xIn
yGa
(1-x-y)N, and 0＜x＜1,0≤y≤0.18, x+y≤1, the temperature that extension adopts is 600～1000 ℃, pressure is 40～200Torr;
In the 9th step, photoetching also adopts reactive ion etching RIE technology to etch groove (14), is etched to barrier layer (4), reacting gas CF
4Flow be 20sccm, O
2Flow be 5mT for 2sccm pressure, power is 50W;
In the tenth step, it is the dielectric layer (13) of 30～500nm that using plasma strengthens chemical vapour deposition (CVD) PECVD equipment deposition thickness, and this dielectric layer covers isolation barrier layer (9) surface and groove (14) inwall;
The 11 step; Photoetching also etches source electrode, grid and drain region; Wherein source electrode and drain region begin to be etched to barrier layer (4) from the dielectric layer surface; Area of grid is in groove (14), and etched recesses medium layer to bottom portion of groove thickness of dielectric layers is 0～5nm, and both sides, groove inner grid zone remain with dielectric layer respectively;
In the 12 step, evaporated metal forms source electrode, grid and drain electrode, and source electrode and drain metal adopt the Ti/Al/Ni/Au combination, and wherein the thickness of Ti is 10～40nm, and the thickness of Al is 30～160nm, and the thickness of Ni is 20～120nm, and the thickness of Au is 60～150nm; And gate metal adopts the Ni/Au combination, and wherein the thickness of Ni is 10～40nm, and the thickness of Au is 80～400nm.
5. method according to claim 4 is characterized in that, the thickness of dielectric layers that the groove both sides keep is 5～30nm.
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| US9837522B2 (en) * | 2015-11-02 | 2017-12-05 | Infineon Technologies Austria Ag | III-nitride bidirectional device |
| CN106653838B (en) * | 2015-11-04 | 2019-05-17 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of Terahertz light source device and preparation method thereof |
| WO2018054377A1 (en) * | 2016-09-26 | 2018-03-29 | 南方科技大学 | High-electron-mobility transistor and preparation method therefor |
| CN106449737B (en) * | 2016-12-01 | 2019-06-21 | 西安电子科技大学 | Low contact resistance type GaN base device and preparation method thereof |
| CN106711185B (en) * | 2016-12-01 | 2019-08-13 | 西安电子科技大学 | High linearity millimetric wave device and preparation method thereof |
| CN107833840B (en) * | 2017-10-27 | 2019-11-15 | 西安电子科技大学 | The method for testing junction temperature of AlGaN/GaN high electron mobility transistor |
| CN111868931B (en) * | 2018-02-14 | 2024-03-12 | Hrl实验室有限责任公司 | Highly scaled linear GaN HEMT structure |
| CN109888011A (en) * | 2019-03-12 | 2019-06-14 | 苏州汉骅半导体有限公司 | Semiconductor structure and its manufacturing method |
| CN112825329B (en) * | 2019-11-21 | 2022-07-22 | 西安电子科技大学 | GaN transistor device with high-linearity composite insulated side gate structure |
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| CN112736132B (en) * | 2021-01-06 | 2023-06-20 | 湖北文理学院 | InP PHEMT epitaxial structure and preparation method thereof |
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