WO2018103606A1 - Transistor du type à ailettes gan présentant une linéarité élevée et une grande mobilité d'électrons, et procédé de fabrication correspondant - Google Patents

Transistor du type à ailettes gan présentant une linéarité élevée et une grande mobilité d'électrons, et procédé de fabrication correspondant Download PDF

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WO2018103606A1
WO2018103606A1 PCT/CN2017/114456 CN2017114456W WO2018103606A1 WO 2018103606 A1 WO2018103606 A1 WO 2018103606A1 CN 2017114456 W CN2017114456 W CN 2017114456W WO 2018103606 A1 WO2018103606 A1 WO 2018103606A1
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gan
layer
passivation layer
fin
gate
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PCT/CN2017/114456
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Chinese (zh)
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张凯
孔月婵
周建军
陈堂胜
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中国电子科技集团公司第五十五研究所
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Publication of WO2018103606A1 publication Critical patent/WO2018103606A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the invention belongs to the technical field of semiconductor device fabrication, and in particular to a GaN fin high electron mobility transistor with high linearity and a manufacturing method thereof.
  • the third-generation semiconductor GaN-based high electron mobility transistor has the characteristics of high output power density, high efficiency, high temperature resistance, and radiation resistance. It has become a mainstream technology for manufacturing high-frequency, high-efficiency, high-power electronic devices. The performance of weapons and equipment represented by radar has increased. With the urgent need for high-linearity transistors for high-data-stream satellite communications and modern wireless communications applications such as 5G communications, high-linear devices are now a key development direction in the GaN field. High linearity will result in more efficient spectrum utilization and reduce the need for linearization modules, further increasing the efficiency and integration of the entire system.
  • the transconductance of the conventional GaN planar structure exhibits a typical peak characteristic, that is, the transconductance is severely degraded at a high current, resulting in rapid compression of the device gain at high input power, poor intermodulation characteristics, and low linearity.
  • the Hong Kong University of Science and Technology proposed the Al 0.05 Ga 0.95 N/GaN composite channel, which improved the cross-wire property to some extent by reducing the longitudinal electric field of the channel (see document Jie Liu et al., Highly Linear).
  • Al 0.3 Ga 0.7 N–Al 0.05 Ga 0.95 N–GaN Composite-Channel HEMTs IEEE Electron Device Lett., vol. 26, no. 3, pp. 145-147, 2005).
  • GaN HFETs GaN HFETs, IEEE Trans. Microw. Theory Tech., vol. 54, no. 5, pp. 2061-2067, 2006. Therefore, the composite channel structure is very limited in improving the linearity, and the channel thermal resistance is increased, and the output power, frequency, efficiency and the like of the device are significantly degraded.
  • GaN FinFET (or three-dimensional fin structure) has recently been closely watched by domestic and foreign research institutions. It has enhanced the control of channel electrons by introducing additional side gates on both sides of the channel, which is better than traditional structures. Subthreshold characteristics, off-state characteristics, and short-channel effects are also greatly suppressed (see Kota Ohi et al., Current Stability in Multi-Mesa-Channel AlGaN/GaN HEMTs, IEEE Trans. Electron Devices., vol. 60, No.10, pp. 2997-3004, 2013).
  • the fins are prepared in a self-aligned manner, the process is complicated, and the process compatibility with the conventional GaN device is poor; most importantly, the gate electrode of the device prepared by this process is a straight gate structure, and the gate resistance is large. The resulting high oscillation frequency is low, which ultimately limits its application in microwave power circuits.
  • the Chinese patent application discloses a multi-channel fin structure AlGaN/GaN high electron mobility transistor structure and fabrication method, which mainly solves the problems of poor gate control capability and low current of FinFET devices in the existing multi-channel devices.
  • the structure of the device includes a substrate (1), a first AlGaN/GaN heterojunction (2), a SiN passivation layer (4), and a source/drain gate electrode in this order from bottom to top, and the source and drain electrodes are respectively located in the SiN.
  • a top layer of the AlGaN barrier layer on both sides of the passivation layer wherein: a first layer of AlGaN/GaN heterojunction and a SiN passivation layer are provided with a GaN layer and an AlGaN barrier layer to form a second layer of AlGaN/GaN heterojunction (3); the gate electrode covers the top of the second layer heterojunction and the two sidewalls of the first layer and the second layer heterojunction.
  • the device has strong gate control capability, large saturation current and good subthreshold characteristics, and can be used for low power consumption and low noise microwave power devices with short gate length.
  • the Chinese patent application discloses a T-gate N-plane GaN/AlGaN fin type high electron mobility transistor, which mainly solves the problems of low oscillation frequency, large ohmic contact resistance and serious short channel effect of the existing microwave power device.
  • the structure of the device from bottom to top includes: substrate (1), GaN buffer layer (2), AlGaN barrier layer (3), GaN channel layer (4), gate dielectric layer (5), passivation layer ( 6) and source, drain, and gate electrodes, wherein the buffer layer and the channel layer are N-plane GaN materials; the GaN channel layer and the AlGaN barrier layer constitute a GaN/AlGaN heterojunction; the gate electrode is a T-gate and is wrapped A three-dimensional grid structure is formed on both sides and above the GaN/AlGaN heterojunction.
  • the device has the advantages of good gate control capability, small ohmic contact resistance and high maximum oscillation frequency, and can be used as a small-sized microwave power device.
  • the object of the present invention is to provide a GaN fin type high electron mobility transistor with high linearity and a manufacturing method thereof, which overcomes the deficiencies of the prior art, and the present invention has a high manufacturing process with a simplified manufacturing process. Linearity and maximum oscillation frequency can meet the application needs of GaN high linearity microwave power devices.
  • a GaN fin type high electron mobility transistor having high linearity including a substrate, a buffer layer, a barrier layer, and a passivation layer in order from bottom to top; the barrier layer The upper end is provided with a source and the other end is provided with a drain; a barrier layer is disposed above the barrier layer between the source and the drain, and the passivation layer is provided with a groove, the concave A T-type gate is disposed in the trench, and is characterized in that the barrier layer and the buffer layer in the region below the recess are etched with periodically arranged GaN-based three-dimensional fins, the GaN-based three-dimensional fins The length is equal to the length of the groove, and an isolation trench formed by etching is provided between adjacent GaN-based three-dimensional fins.
  • the GaN-based three-dimensional fins (8) have a height of 10 to 300 nm and a width of 10 to 1000 nm.
  • a portion of the T-type gate (9) covers both sides above the GaN-based three-dimensional fin (8), and another portion of the T-type gate (9) covers an adjacent GaN-based three-dimensional fin (8) Above the isolation trench, a further portion of the T-gate (9) overlies the passivation layer (6).
  • the invention provides a GaN fin type high electron mobility transistor with high linearity and a preparation method of the preferred solution, which comprises the following specific steps:
  • the present invention is based on the existing GaN groove gate device manufacturing process. After the passivation layer is opened, a fin photolithography mask is formed inside the groove, and then a GaN group is formed by etching. Three-dimensional fins, and finally the T-gate is completely wrapped around the GaN-based three-dimensional fins.
  • the preparation process of the present invention can reliably ensure that the GaN-based three-dimensional fin is limited to the underside of the groove and completely covered by the gate, and the other regions have no three-dimensional fins, so according to the transconductance high linearity principle, the linearity of the device of the present invention is high due to Using the same T-gate as the conventional process, the gate resistance is small, so the highest oscillation frequency of the device is high.
  • the process of the present invention is simple and reliable, and the object of the present invention can be achieved by adding a one-step fin preparation process based on the existing GaN groove gate process.
  • the device of the invention adopts a T-gate structure, which not only has high linearity, but also has the highest oscillation frequency, and can meet the requirements of the microwave power circuit.
  • the device of the present invention has higher current driving capability and output power capability because the degradation of the transconductance under high gate voltage is suppressed
  • the device of the present invention has low thermal resistance and is suitable for high power and high linearity microwave power devices.
  • FIG. 1 is a schematic view showing a three-dimensional structure of a GaN fin type high electron mobility transistor having high linearity according to the present invention.
  • FIG. 2 includes FIG. 2a, FIG. 2b, FIG. 2c, FIG. 2d, FIG. 2e, FIG. 2f, and FIG. 2g, which are one of the present invention.
  • FIG. 3 is a schematic diagram of DC transfer characteristics of a conventional GaN planar device.
  • FIG. 4 is a schematic illustration of the DC transfer characteristics of a high linearity GaN fin device fabricated in accordance with the present invention.
  • a GaN fin type high electron mobility transistor with high linearity proposed by the present invention is based on a group III nitride semiconductor, and has a structure including a substrate 1, a buffer layer 2, and a barrier layer 3 from bottom to top.
  • a passivation layer 6 one end of the barrier layer 3 is provided with a source 4 and the other end is provided with a drain 5; and a barrier layer 3 between the source 4 and the drain 5 is provided with a passivation
  • the layer 6 is provided with a recess 7 in the passivation layer 6 , and a T-shaped gate 9 is disposed in the recess 7 , and the barrier layer 3 and the buffer layer 2 are limited to the region below the recess 7 .
  • GaN-based three-dimensional fins 8 There are a plurality of periodically arranged GaN-based three-dimensional fins 8 which are only present under the recesses 7 and have no fins in other regions.
  • the length of the GaN-based three-dimensional fins 8 is The grooves 7 are of equal length, and an isolation trench formed by etching is provided between adjacent GaN-based three-dimensional fins. among them:
  • the GaN-based three-dimensional fin 8 has a height of 10 to 300 nm (including selection of 10 nm, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm, etc.) and a width of 10 to 1000 nm (including selection of 10 nm, 100 nm, 300 nm, 600 nm, or 1000 nm, etc.) Wherein the height of the GaN-based three-dimensional fin 8 is greater than the thickness of the barrier layer 3.
  • T-shaped gate 9 covers both sides above the three-dimensional fin 8, and another portion of the T-shaped gate 9 covers the isolation trench between adjacent GaN-based three-dimensional fins 8, T-type A further portion of the gate 9 overlies the passivation layer 6.
  • a method for fabricating a GaN fin high electron mobility transistor with high linearity includes the following specific steps:
  • the substrate 1 is made of any one of sapphire, SiC, Si, diamond or GaN self-supporting substrates.
  • the buffer layer 2 is one or a combination of GaN, AlGaN, AlN, and InGaN; and the barrier layer 3 is one or a combination of AlGaN, InAlN, InAlGaN, and AlN.
  • the metals of the source 4 and the drain 5 include, but are not limited to, Ti/Al, Ti/Au, Ti/Al/W, Ti/Al/Mo/Au, Ti/Al/Ni/Au, Si/Ti. Any of the multilayer metals of /Al/Ni/Au, Ti/Al/TiN.
  • the material of the passivation layer 6 is one or a combination of SiN, SiO 2 , SiON, AlN, and the thickness is 30 to 300 nm (including selection of 30 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, etc.), the growth method is plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD).
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • LPCVD low pressure chemical vapor deposition
  • the GaN-based fin mask is fabricated by optical lithography or electron beam direct writing, and the barrier layer 3 and the buffer layer 2 are etched by dry methods such as RIE and ICP. Etching method
  • the gate metal includes but is not limited to Ni/Au, Ni /Au/Ni, Pt/Au, Ni/Pt/Au, W/Ti/Au, Ni/Pt/Au/Pt/Ti, TiN/Ti/Al/Ti/TiN, any of the multilayer metals,
  • the thickness of the gate metal is 50 to 700 nm (including selection of 50 nm, 100 nm, 300 nm, 500 nm or 700 nm, etc.).
  • An interconnect metal region mask is defined on the passivation layer 6, and a interconnect metal is formed by an evaporation and lift-off process.
  • the present invention provides the following two embodiments, but is not limited to these embodiments.
  • Example 1 Preparation of SiC substrate, buffer layer is AlN/GaN, barrier layer is AlGaN, passivation layer is SiN, GaN-based three-dimensional fin width is 100 nm, and gate metal is Ni/Au/Ni with high linearity Degree of GaN fin high electron mobility transistor, the process is:
  • MOCVD metal organic chemical vapor deposition
  • the deposited metal is Ti, Al, Ni, and Au from bottom to top, and has thicknesses of 20 nm, 150 nm, 60 nm, and 50 nm, respectively.
  • the conditions for electron beam evaporation are as follows: vacuum degree ⁇ 2.0 ⁇ 10 -6 Torr, deposition rate is less than
  • the process conditions for rapid thermal annealing are: temperature 840 ° C, time 30 s.
  • the deposition process conditions are: SiH 4 , NH 3 , He and N 2 , respectively, flow rates of 8 sccm, 2 sccm, 100 sccm, and 200 sccm, respectively.
  • the pressure was 500 mTorr
  • the temperature was 260 ° C
  • the power was 25 W
  • the thickness of the passivation layer was 100 nm.
  • An active region mask is formed on the passivation layer 6, and then device isolation is performed by ion implantation to form an active region.
  • the implantation conditions were as follows: ion was B + , current was 10 ⁇ A, energy was 100 KeV, and dose was 5e14.
  • a mask is formed on the upper portion of the passivation layer 6, and a recess 7 is formed in the passivation layer 6 between the source 4 and the drain 5 by a plasma enhanced etching technique RIE.
  • the process conditions for etching the groove are: gas is SF 6 , flow rate is 20 sccm, pressure is 0.2 Pa, and time is 200 s.
  • etching conditions were as follows: gas was BCl 3 and Cl 2 respectively, flow rates were 25 sccm and 5 sccm, pressure was 30 mTorr, temperature was 25 ° C, upper electrode power was 100 W, lower electrode was 3 W, etching time was 5 minutes, and etching depth was 50 nm.
  • the process condition for depositing the metal stack is: vacuum degree ⁇ 1.5 ⁇ 10 -6 Torr, the deposition rate is less than
  • the deposited metal stack is Ni, Au, Ni from bottom to top, and the thicknesses are 20 nm, 500 nm and 30 nm, respectively.
  • An interconnect opening area lithography mask is defined on the passivation layer 6, and interconnect openings are formed by RIE dry etching.
  • the etching process conditions were as follows: the gas was SF 6 , the flow rate was 20 sccm, the pressure was 0.2 Pa, and the time was 200 s.
  • An interconnect metal region mask is defined on the passivation layer 6, and a interconnect metal is formed by an evaporation and lift-off process.
  • the process conditions for depositing the metal stack are: vacuum degree ⁇ 1.5 ⁇ 10 -6 Torr, and the deposition rate is less than
  • the deposited metal stack was Ti and Au from bottom to top and had thicknesses of 30 nm and 500 nm, respectively.
  • Example 2 A Si substrate was prepared, the buffer layer was an AlN/AlGaN/GaN layer, the barrier layer was AlN/InAlN, the passivation layer was SiO 2 , the GaN-based three-dimensional fin width was 400 nm, and the gate metal was TiN/Ti/ Al/Ti/TiN high-linearity GaN fin high electron mobility transistor, the process is:
  • a metal organic chemical vapor deposition technique MOCVD is used to grow 200 nm of AlN at 1050 ° C, and then grow a 1 ⁇ m unintentionally doped AlGaN layer (Al group 15%) at 1000 ° C and A 500 nm GaN layer was formed to form a buffer layer 2, and then an AlN layer having a thickness of 1 nm and 8 nm of InAlN were grown on the buffer layer 2 at 800 ° C to form a barrier layer 3 having an Al composition of 83%.
  • the metal stack is Ti, Al and TiN from bottom to top, and the thickness thereof is 20 nm, 200 nm and 100 nm, respectively;
  • the conditions for electron beam evaporation are: vacuum degree ⁇ 2.0 ⁇ 10 -6 Torr , the deposition rate is less than
  • the process conditions for rapid thermal annealing are: temperature 550 ° C, time 90 s.
  • a passivation layer 6 is formed by depositing SiO 2 on the barrier layer 3 by a PECVD technique.
  • the deposition process conditions were as follows: gas was SiH 4 , N 2 O, flow rate was 120 sccm, 200 sccm, pressure was 500 mTorr, temperature was 320 ° C, power was 35 W, and the thickness of the passivation layer was 150 nm.
  • the fourth step of the second embodiment is the same as the fourth step of the first embodiment.
  • a fin mask is formed inside the recess 7 by deep ultraviolet lithography, AlGaN/GaN is dry-etched by ICP, and the photoresist mask is removed to form a fin 8 having a width of 400 nm.
  • the etching process conditions are: gas is BCl 3 and Cl 2 respectively, flow rate is 25sccm and 5sccm respectively, pressure is 30mTorr, temperature is 25°C, upper electrode power is 100W, lower electrode is 3W, etching time is 5 minutes, etching depth 50nm.
  • a gate mask is formed on the upper portion of the passivation layer 6, a metal laminate is deposited by electron beam evaporation, and a T-gate 9 is formed by a lift-off process.
  • the process conditions for depositing the metal stack are: vacuum degree ⁇ 1.5 ⁇ 10 -6 Torr, and the deposition rate is less than
  • the deposited metal stack was TiN/Ti/Al/Ti/TiN from bottom to top and had thicknesses of 20 nm, 30 nm, 300 nm, 30 nm, and 100 nm, respectively.
  • the etching process condition is: the gas is SF 6 , the flow rate is 20 sccm, and the pressure is 0.2 Pa. Time is 600s.
  • the ninth step of the second embodiment is the same as the ninth step of the first embodiment.
  • Figure 3 shows the DC transfer characteristics of a GaN planar device. It can be seen that the device transconductance exhibits typical peak characteristics with a maximum current of 1.2 A/mm and a maximum transconductance G m of 0.48 S/mm. 4 is a DC transfer characteristic of a high linearity GaN fin device prepared according to the present invention, the device transconductance G m is flatter, the linearity is greatly improved, and the maximum current is 2 A/mm, and the maximum transconductance G m is 0.74 S/mm. . As can be seen from the above comparison, the maximum current and transconductance values of the high linearity GaN fin device of the present invention are greatly improved compared with the planar device, and the cross-wire property is greatly improved.
  • the invention has been verified by repeated experiments and has achieved satisfactory trial results.

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Abstract

L'invention concerne un transistor du type à ailettes GaN présentant une linéarité élevée et une grande mobilité d'électrons, et un procédé de fabrication correspondant. Le transistor comporte une structure comprenant, du bas vers le haut : un substrat (1), une couche tampon (2), une couche d'appauvrissement (3) et une couche de passivation (6). Une électrode de source (4) est placée au-dessus d'une extrémité de la couche d'appauvrissement, et une électrode de drain (5) est placée au-dessus de l'autre extrémité de la couche d'appauvrissement. La couche de passivation est placée au-dessus de la couche d'appauvrissement, entre l'électrode de source et l'électrode de drain. Un évidement (7) formé au niveau de la couche de passivation contient un réseau en forme de T (9), placé à l'intérieur de celui-ci. La couche de passivation est caractérisée en ce que : des ailettes tridimensionnelles (8) à base de GaN sont gravées sur la couche tampon et la couche d'appauvrissement, à la seule exception d'une région située au-dessous de l'évidement, et présentent un agencement périodique ; les ailettes tridimensionnelles à base de GaN ont des longueurs identiques à celles de l'évidement ; et un évidement isolant formé par gravure se situe entre les ailettes tridimensionnelles à base de GaN. Ce dispositif présente une linéarité élevée et un courant de sortie élevé, une forte commande de grille, une performance de dissipation de chaleur favorable et une caractéristique haute fréquence. Le procédé de fabrication de ce dispositif est simple et fiable, et convient pour un dispositif à énergie micro-onde de grande puissance à linéarité élevée.
PCT/CN2017/114456 2016-12-08 2017-12-04 Transistor du type à ailettes gan présentant une linéarité élevée et une grande mobilité d'électrons, et procédé de fabrication correspondant WO2018103606A1 (fr)

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CN201611122851.9A CN106684141A (zh) 2016-12-08 2016-12-08 一种具有高线性度的GaN鳍式高电子迁移率晶体管及其制造方法

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WO2021012340A1 (fr) * 2019-07-19 2021-01-28 中国电子科技集团公司第五十五研究所 Transistor gan à haute mobilité d'électrons ayant un dispositif secondaire d'épissage et son procédé de fabrication
CN112713185A (zh) * 2020-12-21 2021-04-27 西安电子科技大学 具有支撑结构的t型栅及其制备方法和半导体功率器件
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CN114725094A (zh) * 2022-01-26 2022-07-08 西安电子科技大学广州研究院 一种Si-GaN单片异质集成反相器及其制备方法
CN114883396A (zh) * 2022-07-11 2022-08-09 成都功成半导体有限公司 一种凹陷式Fin-JFET栅结构HEMT及制作方法
WO2024113528A1 (fr) * 2022-11-30 2024-06-06 扬州扬杰电子科技股份有限公司 Dispositif gan-hemt à base de si amélioré par canal conducteur vertical et son procédé de fabrication

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CN106684141A (zh) * 2016-12-08 2017-05-17 中国电子科技集团公司第五十五研究所 一种具有高线性度的GaN鳍式高电子迁移率晶体管及其制造方法
CN107919386B (zh) * 2017-11-21 2021-05-28 中国科学院微电子研究所 基于应变调控的增强型GaN基FinFET结构
CN110098255B (zh) * 2018-01-29 2022-10-28 中国电子科技集团公司第五十五研究所 一种局域化沟道的场效应晶体管及其制备方法
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